[all-commits] [llvm/llvm-project] 18782d: [RISCV] Improve instruction selection for most sig...

[Piotr Fusik via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 18782db4c95b80fd3a619826558db118bb874325
      https://github.com/llvm/llvm-project/commit/18782db4c95b80fd3a619826558db118bb874325
  Author: Piotr Fusik <p.fusik at samsung.com>
  Date:   2025-08-14 (Thu, 14 Aug 2025)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVInstrInfo.td
    M llvm/test/CodeGen/RISCV/GlobalISel/double-fcmp.ll
    M llvm/test/CodeGen/RISCV/GlobalISel/float-fcmp.ll
    M llvm/test/CodeGen/RISCV/alu64.ll
    M llvm/test/CodeGen/RISCV/arith-with-overflow.ll
    M llvm/test/CodeGen/RISCV/bittest.ll
    M llvm/test/CodeGen/RISCV/condbinops.ll
    M llvm/test/CodeGen/RISCV/double-convert.ll
    M llvm/test/CodeGen/RISCV/double-fcmp-strict.ll
    M llvm/test/CodeGen/RISCV/double-fcmp.ll
    M llvm/test/CodeGen/RISCV/float-convert.ll
    M llvm/test/CodeGen/RISCV/float-fcmp-strict.ll
    M llvm/test/CodeGen/RISCV/float-fcmp.ll
    M llvm/test/CodeGen/RISCV/float-intrinsics.ll
    M llvm/test/CodeGen/RISCV/fold-addi-loadstore.ll
    M llvm/test/CodeGen/RISCV/forced-atomics.ll
    M llvm/test/CodeGen/RISCV/fpclamptosat.ll
    M llvm/test/CodeGen/RISCV/half-convert.ll
    M llvm/test/CodeGen/RISCV/memcmp-optsize.ll
    M llvm/test/CodeGen/RISCV/memcmp.ll
    M llvm/test/CodeGen/RISCV/min-max.ll
    M llvm/test/CodeGen/RISCV/pr84653_pr85190.ll
    M llvm/test/CodeGen/RISCV/rv32zbb-zbkb.ll
    M llvm/test/CodeGen/RISCV/rv32zbs.ll
    M llvm/test/CodeGen/RISCV/rv64-double-convert.ll
    M llvm/test/CodeGen/RISCV/rv64-float-convert.ll
    M llvm/test/CodeGen/RISCV/rv64-half-convert.ll
    M llvm/test/CodeGen/RISCV/rvv/fpclamptosat_vec.ll
    M llvm/test/CodeGen/RISCV/rvv/vxrm-insert-out-of-loop.ll
    M llvm/test/CodeGen/RISCV/sadd_sat.ll
    M llvm/test/CodeGen/RISCV/sadd_sat_plus.ll
    M llvm/test/CodeGen/RISCV/select-binop-identity.ll
    M llvm/test/CodeGen/RISCV/select-cc.ll
    M llvm/test/CodeGen/RISCV/select-constant-xor.ll
    M llvm/test/CodeGen/RISCV/selectcc-to-shiftand.ll
    M llvm/test/CodeGen/RISCV/stack-folding.ll
    M llvm/test/CodeGen/RISCV/xaluo.ll
    M llvm/test/CodeGen/RISCV/xqcia.ll
    M llvm/test/CodeGen/RISCV/zbb-cmp-combine.ll

  Log Message:
  -----------
  [RISCV] Improve instruction selection for most significant bit extraction (#151687)

    (seteq (and X, 1<<XLEN-1), 0) -> (xori (srli X, XLEN-1), 1)
    (seteq (and X, 1<<31), 0) -> (xori (srliw X, 31), 1) // RV64
    (setlt X, 0) -> (srli X, XLEN-1) // SRLI is compressible
    (setlt (sext X), 0) -> (srliw X, 31) // RV64



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