[all-commits] [llvm/llvm-project] 71b066: [RISCV] Add CodeGen support for qc.insbi and qc.in...

[quic_hchandel via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 71b066e3a2512d582e34a0b5257e12b1177d4bcc
      https://github.com/llvm/llvm-project/commit/71b066e3a2512d582e34a0b5257e12b1177d4bcc
  Author: quic_hchandel <quic_hchandel at quicinc.com>
  Date:   2025-08-14 (Thu, 14 Aug 2025)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
    M llvm/lib/Target/RISCV/RISCVISelDAGToDAG.h
    A llvm/test/CodeGen/RISCV/xqcibm-insbi.ll

  Log Message:
  -----------
  [RISCV] Add CodeGen support for qc.insbi and qc.insb insert instructions (#152447)

This patch adds CodeGen support for qc.insbi and qc.insb instructions
defined in the Qualcomm uC Xqcibm extension. qc.insbi and qc.insb
inserts bits into destination register from immediate and register
operand respectively.
A sequence of `xor`, `and` & `xor` depending on appropriate conditions
are converted to `qc.insbi` or `qc.insb` which depends on the
immediate's value.



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