[all-commits] [llvm/llvm-project] 348f01: [WebAssembly] Combine i128 to v16i8 for setcc & ex...
Stanislav Mekhanoshin via All-commits
all-commits at lists.llvm.org
Tue Aug 12 11:45:14 PDT 2025
Branch: refs/heads/users/rampitec/08-12-_amdgpu_remove_dead_vop1_real_no_dpp_op_sel_with_name._nfc
Home: https://github.com/llvm/llvm-project
Commit: 348f01f89c272c08e46bbdc1779d658323f17214
https://github.com/llvm/llvm-project/commit/348f01f89c272c08e46bbdc1779d658323f17214
Author: Jasmine Tang <jjasmine at igalia.com>
Date: 2025-08-12 (Tue, 12 Aug 2025)
Changed paths:
M llvm/lib/Target/WebAssembly/WebAssemblyISelLowering.cpp
M llvm/lib/Target/WebAssembly/WebAssemblyTargetTransformInfo.cpp
M llvm/test/CodeGen/WebAssembly/memcmp-expand.ll
A llvm/test/CodeGen/WebAssembly/simd-setcc.ll
Log Message:
-----------
[WebAssembly] Combine i128 to v16i8 for setcc & expand memcmp for 16 byte loads with simd128 (#149461)
Fixes https://github.com/llvm/llvm-project/issues/149230
Previously, even with simd enabled via `-mattr=+simd128`, the compiler
cannot utilize v128 to optimize loads and setcc of i128, instead
legalizing it to consecutive i64s.
This PR then adds support for setcc of i128 by converting them to
v16i8's anytrue and alltrue; consequently, this benefits memcmp of 16
bytes or more (when simd128 is present).
The check for enabling this optimization is if the comparison operand is
either a load or an integer in i128, with the comparison code being
either `EQ | NE`, without `NoImplicitFloat` function flag.
Inspiration taken from RISCV's isel lowering.
Commit: c430e06fb58692d25284257c95ad77a33ed03438
https://github.com/llvm/llvm-project/commit/c430e06fb58692d25284257c95ad77a33ed03438
Author: Daniel Paoliello <danpao at microsoft.com>
Date: 2025-08-12 (Tue, 12 Aug 2025)
Changed paths:
M llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp
M llvm/lib/CodeGen/SelectionDAG/FastISel.cpp
A llvm/test/CodeGen/AArch64/arm64ec-dont-call.ll
M llvm/test/CodeGen/X86/attr-dontcall.ll
Log Message:
-----------
[win][arm64ec] Fix duplicate errors with the dontcall attribute (#152810)
Since the `dontcall-*` attributes are checked both by
`FastISel`/`GlobalISel` and `SelectionDAGBuilder`, and both `FastISel`
and `GlobalISel` bail for calls on Arm64EC for AFTER doing the check, we
ended up emitting duplicate copies of this error.
This change moves the checking for `dontcall-*` in `FastISel` and
`GlobalISel` to after it has been successfully lowered.
Commit: 9b93ccbcbe34750136a06eef4dd23a59d42fe99e
https://github.com/llvm/llvm-project/commit/9b93ccbcbe34750136a06eef4dd23a59d42fe99e
Author: Sam Elliott <aelliott at qti.qualcomm.com>
Date: 2025-08-12 (Tue, 12 Aug 2025)
Changed paths:
M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
M llvm/test/CodeGen/RISCV/xqcibi.ll
Log Message:
-----------
[RISCV] Fix Immediate Check for Xqcibi UGT (#153141)
The check should be about unsigned 16-bit immediates, not signed ones.
This is not a bug per-se, as the old codegen was correct for the
uint16_max case, it just didn't end up using `qc.e.bgeui`, which we
would prefer it did.
Commit: 4d629f9744827b87b9853d0815617e6e8d9ea05e
https://github.com/llvm/llvm-project/commit/4d629f9744827b87b9853d0815617e6e8d9ea05e
Author: Philip Reames <preames at rivosinc.com>
Date: 2025-08-12 (Tue, 12 Aug 2025)
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M llvm/include/llvm/CodeGen/MIRYamlMapping.h
M llvm/lib/CodeGen/MIRParser/MIRParser.cpp
M llvm/lib/CodeGen/MIRPrinter.cpp
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M llvm/test/CodeGen/AArch64/emit_fneg_with_non_register_operand.mir
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M llvm/test/CodeGen/AArch64/jump-table-duplicate.mir
M llvm/test/CodeGen/AArch64/ldst-nopreidx-sp-redzone.mir
M llvm/test/CodeGen/AArch64/ldst_update_cfpath.mir
M llvm/test/CodeGen/AArch64/live-debugvalues-sve.mir
M llvm/test/CodeGen/AArch64/loop-sink-limit.mir
M llvm/test/CodeGen/AArch64/loop-sink.mir
M llvm/test/CodeGen/AArch64/machine-latecleanup-inlineasm.mir
M llvm/test/CodeGen/AArch64/nested-iv-regalloc.mir
M llvm/test/CodeGen/AArch64/regalloc-last-chance-recolor-with-split.mir
M llvm/test/CodeGen/AArch64/shrinkwrap-split-restore-point.mir
M llvm/test/CodeGen/AArch64/sink-and-fold-drop-dbg.mir
M llvm/test/CodeGen/AArch64/sink-and-fold-illegal-shift.mir
M llvm/test/CodeGen/AArch64/sink-and-fold-preserve-debugloc.mir
M llvm/test/CodeGen/AArch64/split-deadloop.mir
M llvm/test/CodeGen/AArch64/stack-probing-last-in-block.mir
M llvm/test/CodeGen/AArch64/tail-dup-redundant-phi.mir
M llvm/test/CodeGen/AArch64/taildup-addrtaken.mir
M llvm/test/CodeGen/AArch64/wineh-frame-predecrement.mir
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M llvm/test/CodeGen/Thumb2/LowOverheadLoops/biquad-cascade-default.mir
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M llvm/test/CodeGen/Thumb2/mve-vpt-3-blocks-kill-vpr.mir
M llvm/test/CodeGen/Thumb2/mve-vpt-block-1-ins.mir
M llvm/test/CodeGen/Thumb2/mve-vpt-block-2-ins.mir
M llvm/test/CodeGen/Thumb2/mve-vpt-block-4-ins.mir
M llvm/test/CodeGen/Thumb2/mve-vpt-block-elses.mir
M llvm/test/CodeGen/Thumb2/mve-vpt-block-fold-vcmp.mir
M llvm/test/CodeGen/Thumb2/mve-vpt-block-optnone.mir
M llvm/test/CodeGen/Thumb2/mve-vpt-preuse.mir
M llvm/test/CodeGen/Thumb2/pipeliner-preserve-ties.mir
M llvm/test/CodeGen/VE/Scalar/fold-imm-addsl.mir
M llvm/test/CodeGen/VE/Scalar/fold-imm-cmpsl.mir
M llvm/test/CodeGen/WebAssembly/multivalue-dont-move-def-past-use.mir
M llvm/test/CodeGen/X86/PR37310.mir
M llvm/test/CodeGen/X86/StackColoring-use-between-allocas.mir
M llvm/test/CodeGen/X86/align-basic-block-sections.mir
M llvm/test/CodeGen/X86/amx_tile_pair_configure_O0.mir
M llvm/test/CodeGen/X86/amx_tile_pair_configure_O2.mir
M llvm/test/CodeGen/X86/amx_tile_pair_copy.mir
M llvm/test/CodeGen/X86/amx_tile_pair_preconfigure_O0.mir
M llvm/test/CodeGen/X86/amx_tile_pair_preconfigure_O2.mir
M llvm/test/CodeGen/X86/apx/domain-reassignment.mir
M llvm/test/CodeGen/X86/apx/memfold-nd2rmw.mir
M llvm/test/CodeGen/X86/attr-function-return.mir
M llvm/test/CodeGen/X86/avoid-sfb-g-no-change.mir
M llvm/test/CodeGen/X86/avoid-sfb-g-no-change2.mir
M llvm/test/CodeGen/X86/avoid-sfb-g-no-change3.mir
M llvm/test/CodeGen/X86/avoid-sfb-offset.mir
M llvm/test/CodeGen/X86/avx512f-256-set0.mir
M llvm/test/CodeGen/X86/basic-block-address-map-mir-parse.mir
M llvm/test/CodeGen/X86/basic-block-sections-mir-parse.mir
M llvm/test/CodeGen/X86/break-false-dep-crash.mir
M llvm/test/CodeGen/X86/callbr-asm-outputs-regallocfast.mir
M llvm/test/CodeGen/X86/cf-opt-memops.mir
M llvm/test/CodeGen/X86/cfi-epilogue-with-return.mir
M llvm/test/CodeGen/X86/cfi-epilogue-without-return.mir
M llvm/test/CodeGen/X86/conditional-tailcall-samedest.mir
M llvm/test/CodeGen/X86/cse-two-preds.mir
M llvm/test/CodeGen/X86/domain-reassignment.mir
M llvm/test/CodeGen/X86/movtopush.mir
M llvm/test/CodeGen/X86/peephole-test-after-add.mir
M llvm/test/CodeGen/X86/pr30821.mir
M llvm/test/CodeGen/X86/pr38952.mir
M llvm/test/CodeGen/X86/pr48064.mir
M llvm/test/CodeGen/X86/scheduler-asm-moves.mir
M llvm/test/CodeGen/X86/shrink_wrap_dbg_value.mir
M llvm/test/CodeGen/X86/statepoint-fixup-call.mir
M llvm/test/CodeGen/X86/statepoint-fixup-copy-prop-neg.mir
M llvm/test/CodeGen/X86/statepoint-fixup-invoke.mir
M llvm/test/CodeGen/X86/statepoint-fixup-shared-ehpad.mir
M llvm/test/CodeGen/X86/statepoint-fixup-undef-def.mir
M llvm/test/CodeGen/X86/statepoint-fixup-undef.mir
M llvm/test/CodeGen/X86/statepoint-invoke-ra-enter-at-end.mir
M llvm/test/CodeGen/X86/statepoint-invoke-ra-hoist-copies.mir
M llvm/test/CodeGen/X86/statepoint-invoke-ra-inline-spiller.mir
M llvm/test/CodeGen/X86/statepoint-invoke-ra-remove-back-copies.mir
M llvm/test/CodeGen/X86/statepoint-invoke-ra.mir
M llvm/test/CodeGen/X86/statepoint-vreg-folding.mir
M llvm/test/CodeGen/X86/tied-depbreak.mir
M llvm/test/CodeGen/X86/unfoldMemoryOperand.mir
M llvm/test/CodeGen/X86/win64-eh-empty-block-2.mir
M llvm/test/CodeGen/X86/zero-call-used-regs-debug-info.mir
M llvm/test/DebugInfo/ARM/machine-cp-updates-dbg-reg.mir
M llvm/test/DebugInfo/ARM/move-dbg-values-imm-test.mir
M llvm/test/DebugInfo/MIR/AArch64/implicit-def-dead-scope.mir
M llvm/test/DebugInfo/MIR/ARM/live-debug-values-reg-copy.mir
M llvm/test/DebugInfo/MIR/InstrRef/livedebugvalues-transfer-variadic-instr-ref.mir
M llvm/test/DebugInfo/MIR/Mips/last-inst-bundled.mir
M llvm/test/DebugInfo/MIR/Mips/live-debug-values-reg-copy.mir
M llvm/test/DebugInfo/MIR/X86/dbg-call-site-spilled-arg.mir
M llvm/test/DebugInfo/MIR/X86/debug-loc-0.mir
M llvm/test/DebugInfo/MIR/X86/instr-ref-join-def-vphi.mir
M llvm/test/DebugInfo/MIR/X86/kill-after-spill.mir
M llvm/test/DebugInfo/MIR/X86/live-debug-values-reg-copy.mir
M llvm/test/DebugInfo/MIR/X86/live-debug-values-restore.mir
M llvm/test/DebugInfo/MIR/X86/live-debug-vars-unused-arg-debugonly.mir
M llvm/test/DebugInfo/MIR/X86/live-debug-vars-unused-arg.mir
M llvm/test/DebugInfo/X86/instr-ref-track-clobbers.mir
M llvm/test/DebugInfo/X86/live-debug-vars-dse.mir
M llvm/test/MachineVerifier/verify-inlineasmbr.mir
M llvm/test/tools/UpdateTestChecks/update_mir_test_checks/Inputs/x86-MIFlags.mir
M llvm/test/tools/UpdateTestChecks/update_mir_test_checks/Inputs/x86-MIFlags.mir.expected
M llvm/test/tools/llvm-reduce/mir/preserve-frame-info.mir
M llvm/unittests/CodeGen/DroppedVariableStatsMIRTest.cpp
Log Message:
-----------
[MIR] Remove std::variant from multiple save/restore point handling [nfc] (#153226)
In review of bbde6b, I had originally proposed that we support the
legacy text format. As review evolved, it bacame clear this had been a
bad idea (too much complexity), but in order to let that patch finally
move forward, I approved the change with the variant. This change undoes
the variant, and updates all the tests to just use the array form.
Commit: 21473462f762a9a2d3140eb8ecaea034f83d9a7c
https://github.com/llvm/llvm-project/commit/21473462f762a9a2d3140eb8ecaea034f83d9a7c
Author: Nick Smith <127986401+nsmithtt at users.noreply.github.com>
Date: 2025-08-12 (Tue, 12 Aug 2025)
Changed paths:
M mlir/test/mlir-tblgen/enums-python-bindings.td
M mlir/tools/mlir-tblgen/EnumPythonBindingGen.cpp
Log Message:
-----------
[MLIR][Python] MLIR Enum Python bindings infinite recursion (#151584) (#151588)
Fixes an infinite recursion bug when using I32BitEnumAttrCaseGroup with
python bindings.
For more info, see issue:
- https://github.com/llvm/llvm-project/issues/151584
Commit: d70e50b0da85970ddcbb632e6068d558a7cce5e6
https://github.com/llvm/llvm-project/commit/d70e50b0da85970ddcbb632e6068d558a7cce5e6
Author: Nikolas Klauser <nikolasklauser at berlin.de>
Date: 2025-08-12 (Tue, 12 Aug 2025)
Changed paths:
M libcxx/include/__type_traits/invoke.h
Log Message:
-----------
[libc++] Don't try to used noexcept in C++03
`__is_nothrow_invocable` isn't used in C++03, so we never noticed that
it's not `constexpr`. This is caught by the clang-tidy ADL check
with LLVM 22, since it's treated like a normal function call in C++03.
It's only caught with LLVM 22, since `__builtin_invoke` wasn't available
before.
Commit: c9b00d554f6f906d960f2914ebcebeba2b558d24
https://github.com/llvm/llvm-project/commit/c9b00d554f6f906d960f2914ebcebeba2b558d24
Author: Stanislav Mekhanoshin <Stanislav.Mekhanoshin at amd.com>
Date: 2025-08-12 (Tue, 12 Aug 2025)
Changed paths:
M libcxx/include/__type_traits/invoke.h
M llvm/include/llvm/CodeGen/MIRYamlMapping.h
M llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp
M llvm/lib/CodeGen/MIRParser/MIRParser.cpp
M llvm/lib/CodeGen/MIRPrinter.cpp
M llvm/lib/CodeGen/SelectionDAG/FastISel.cpp
M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
M llvm/lib/Target/WebAssembly/WebAssemblyISelLowering.cpp
M llvm/lib/Target/WebAssembly/WebAssemblyTargetTransformInfo.cpp
M llvm/test/CodeGen/AArch64/GlobalISel/store-merging-debug.mir
M llvm/test/CodeGen/AArch64/aarch64-ldst-no-premature-sp-pop.mir
M llvm/test/CodeGen/AArch64/aarch64-mov-debug-locs.mir
M llvm/test/CodeGen/AArch64/aarch64st1.mir
A llvm/test/CodeGen/AArch64/arm64ec-dont-call.ll
M llvm/test/CodeGen/AArch64/cfi-fixup-multi-block-prologue.mir
M llvm/test/CodeGen/AArch64/cfi-fixup-multi-section.mir
M llvm/test/CodeGen/AArch64/cfi-fixup.mir
M llvm/test/CodeGen/AArch64/early-ifcvt-regclass-mismatch.mir
M llvm/test/CodeGen/AArch64/emit_fneg_with_non_register_operand.mir
M llvm/test/CodeGen/AArch64/irg-nomem.mir
M llvm/test/CodeGen/AArch64/jump-table-duplicate.mir
M llvm/test/CodeGen/AArch64/ldst-nopreidx-sp-redzone.mir
M llvm/test/CodeGen/AArch64/ldst_update_cfpath.mir
M llvm/test/CodeGen/AArch64/live-debugvalues-sve.mir
M llvm/test/CodeGen/AArch64/loop-sink-limit.mir
M llvm/test/CodeGen/AArch64/loop-sink.mir
M llvm/test/CodeGen/AArch64/machine-latecleanup-inlineasm.mir
M llvm/test/CodeGen/AArch64/nested-iv-regalloc.mir
M llvm/test/CodeGen/AArch64/regalloc-last-chance-recolor-with-split.mir
M llvm/test/CodeGen/AArch64/shrinkwrap-split-restore-point.mir
M llvm/test/CodeGen/AArch64/sink-and-fold-drop-dbg.mir
M llvm/test/CodeGen/AArch64/sink-and-fold-illegal-shift.mir
M llvm/test/CodeGen/AArch64/sink-and-fold-preserve-debugloc.mir
M llvm/test/CodeGen/AArch64/split-deadloop.mir
M llvm/test/CodeGen/AArch64/stack-probing-last-in-block.mir
M llvm/test/CodeGen/AArch64/tail-dup-redundant-phi.mir
M llvm/test/CodeGen/AArch64/taildup-addrtaken.mir
M llvm/test/CodeGen/AArch64/wineh-frame-predecrement.mir
M llvm/test/CodeGen/AArch64/wineh-frame-scavenge.mir
M llvm/test/CodeGen/AArch64/wineh-frame1.mir
M llvm/test/CodeGen/AArch64/wineh-frame2.mir
M llvm/test/CodeGen/AArch64/wineh-frame3.mir
M llvm/test/CodeGen/AArch64/wineh-frame4.mir
M llvm/test/CodeGen/AArch64/wineh-frame5.mir
M llvm/test/CodeGen/AArch64/wineh-frame6.mir
M llvm/test/CodeGen/AArch64/wineh-frame7.mir
M llvm/test/CodeGen/AArch64/wineh-frame8.mir
M llvm/test/CodeGen/AArch64/wineh-save-lrpair1.mir
M llvm/test/CodeGen/AArch64/wineh-save-lrpair2.mir
M llvm/test/CodeGen/AArch64/wineh-save-lrpair3.mir
M llvm/test/CodeGen/AArch64/wineh2.mir
M llvm/test/CodeGen/AArch64/wineh3.mir
M llvm/test/CodeGen/AArch64/wineh4.mir
M llvm/test/CodeGen/AArch64/wineh5.mir
M llvm/test/CodeGen/AArch64/wineh6.mir
M llvm/test/CodeGen/AArch64/wineh7.mir
M llvm/test/CodeGen/AArch64/wineh8.mir
M llvm/test/CodeGen/AArch64/wineh9.mir
M llvm/test/CodeGen/AArch64/wineh_shrinkwrap.mir
M llvm/test/CodeGen/AMDGPU/memory-legalizer-multiple-mem-operands-nontemporal-1.mir
M llvm/test/CodeGen/AMDGPU/memory-legalizer-multiple-mem-operands-nontemporal-2.mir
M llvm/test/CodeGen/AMDGPU/triton_regression_no_waterfall.mir
M llvm/test/CodeGen/ARM/cmse-vlldm-no-reorder.mir
M llvm/test/CodeGen/ARM/codesize-ifcvt.mir
M llvm/test/CodeGen/ARM/constant-island-movwt.mir
M llvm/test/CodeGen/ARM/constant-islands-cfg.mir
M llvm/test/CodeGen/ARM/constant-islands-split-IT.mir
M llvm/test/CodeGen/ARM/execute-only-save-cpsr.mir
M llvm/test/CodeGen/ARM/fp16-litpool2-arm.mir
M llvm/test/CodeGen/ARM/fp16-litpool3-arm.mir
M llvm/test/CodeGen/ARM/inlineasmbr-if-cvt.mir
M llvm/test/CodeGen/ARM/invalidated-save-point.ll
M llvm/test/CodeGen/ARM/jump-table-dbg-value.mir
M llvm/test/CodeGen/ARM/stack_frame_offset.mir
M llvm/test/CodeGen/Hexagon/cext-opt-block-addr.mir
M llvm/test/CodeGen/Hexagon/early-if-predicator.mir
M llvm/test/CodeGen/Hexagon/hwloop-dist-check.mir
M llvm/test/CodeGen/Hexagon/machine-sink-float-usr.mir
M llvm/test/CodeGen/Hexagon/pipeliner/swp-phi-start.mir
M llvm/test/CodeGen/Hexagon/rdf-copy-clobber.mir
M llvm/test/CodeGen/Hexagon/rdf-phi-clobber.mir
M llvm/test/CodeGen/MIR/ARM/thumb2-sub-sp-t3.mir
M llvm/test/CodeGen/MIR/Generic/frame-info.mir
M llvm/test/CodeGen/MIR/Hexagon/addrmode-opt-nonreaching.mir
M llvm/test/CodeGen/MIR/RISCV/machine-function-info.mir
M llvm/test/CodeGen/MIR/X86/branch-folder-with-label.mir
M llvm/test/CodeGen/MIR/X86/diexpr-win32.mir
M llvm/test/CodeGen/MIR/X86/fake-use-tailcall.mir
M llvm/test/CodeGen/MIR/X86/frame-info-save-restore-points.mir
M llvm/test/CodeGen/MIR/X86/inline-asm-rm-exhaustion.mir
M llvm/test/CodeGen/Mips/delay-slot-filler-bundled-insts-def-use.mir
M llvm/test/CodeGen/Mips/delay-slot-filler-bundled-insts.mir
M llvm/test/CodeGen/Mips/indirect-jump-hazard/guards-verify-call.mir
M llvm/test/CodeGen/Mips/indirect-jump-hazard/guards-verify-tailcall.mir
M llvm/test/CodeGen/Mips/instverify/dext-pos.mir
M llvm/test/CodeGen/Mips/instverify/dext-size.mir
M llvm/test/CodeGen/Mips/instverify/dextm-pos-size.mir
M llvm/test/CodeGen/Mips/instverify/dextm-pos.mir
M llvm/test/CodeGen/Mips/instverify/dextm-size.mir
M llvm/test/CodeGen/Mips/instverify/dextu-pos-size.mir
M llvm/test/CodeGen/Mips/instverify/dextu-pos.mir
M llvm/test/CodeGen/Mips/instverify/dextu-size-valid.mir
M llvm/test/CodeGen/Mips/instverify/dextu-size.mir
M llvm/test/CodeGen/Mips/instverify/dins-pos-size.mir
M llvm/test/CodeGen/Mips/instverify/dins-pos.mir
M llvm/test/CodeGen/Mips/instverify/dins-size.mir
M llvm/test/CodeGen/Mips/instverify/dinsm-pos-size.mir
M llvm/test/CodeGen/Mips/instverify/dinsm-pos.mir
M llvm/test/CodeGen/Mips/instverify/dinsm-size.mir
M llvm/test/CodeGen/Mips/instverify/dinsu-pos-size.mir
M llvm/test/CodeGen/Mips/instverify/dinsu-pos.mir
M llvm/test/CodeGen/Mips/instverify/dinsu-size.mir
M llvm/test/CodeGen/Mips/instverify/ext-pos-size.mir
M llvm/test/CodeGen/Mips/instverify/ext-pos.mir
M llvm/test/CodeGen/Mips/instverify/ext-size.mir
M llvm/test/CodeGen/Mips/instverify/ins-pos-size.mir
M llvm/test/CodeGen/Mips/instverify/ins-pos.mir
M llvm/test/CodeGen/Mips/instverify/ins-size.mir
M llvm/test/CodeGen/Mips/longbranch/branch-limits-fp-micromips.mir
M llvm/test/CodeGen/Mips/longbranch/branch-limits-fp-micromipsr6.mir
M llvm/test/CodeGen/Mips/longbranch/branch-limits-fp-mips.mir
M llvm/test/CodeGen/Mips/longbranch/branch-limits-fp-mipsr6.mir
M llvm/test/CodeGen/Mips/longbranch/branch-limits-int-microMIPS.mir
M llvm/test/CodeGen/Mips/longbranch/branch-limits-int-micromipsr6.mir
M llvm/test/CodeGen/Mips/longbranch/branch-limits-int-mips64.mir
M llvm/test/CodeGen/Mips/longbranch/branch-limits-int-mips64r6.mir
M llvm/test/CodeGen/Mips/longbranch/branch-limits-int-mipsr6.mir
M llvm/test/CodeGen/Mips/longbranch/branch-limits-int.mir
M llvm/test/CodeGen/Mips/longbranch/branch-limits-msa.mir
M llvm/test/CodeGen/Mips/micromips-eva.mir
M llvm/test/CodeGen/Mips/micromips-short-delay-slot.mir
M llvm/test/CodeGen/Mips/micromips-sizereduction/micromips-lwp-swp.mir
M llvm/test/CodeGen/Mips/micromips-sizereduction/micromips-no-lwp-swp.mir
M llvm/test/CodeGen/Mips/mirparser/target-flags-pic-mxgot-tls.mir
M llvm/test/CodeGen/Mips/mirparser/target-flags-pic-o32.mir
M llvm/test/CodeGen/Mips/mirparser/target-flags-pic.mir
M llvm/test/CodeGen/Mips/mirparser/target-flags-static-tls.mir
M llvm/test/CodeGen/Mips/msa/emergency-spill.mir
M llvm/test/CodeGen/Mips/sll-micromips-r6-encoding.mir
M llvm/test/CodeGen/Mips/unaligned-memops-mapping.mir
M llvm/test/CodeGen/NVPTX/proxy-reg-erasure.mir
M llvm/test/CodeGen/PowerPC/DisableHoistingDueToBlockHotnessNoProfileData.mir
M llvm/test/CodeGen/PowerPC/DisableHoistingDueToBlockHotnessProfileData.mir
M llvm/test/CodeGen/PowerPC/NoCRFieldRedefWhenSpillingCRBIT.mir
M llvm/test/CodeGen/PowerPC/alignlongjumptest.mir
M llvm/test/CodeGen/PowerPC/block-placement-1.mir
M llvm/test/CodeGen/PowerPC/block-placement.mir
M llvm/test/CodeGen/PowerPC/collapse-rotates.mir
M llvm/test/CodeGen/PowerPC/convert-rr-to-ri-instrs-R0-special-handling.mir
M llvm/test/CodeGen/PowerPC/convert-rr-to-ri-instrs-out-of-range.mir
M llvm/test/CodeGen/PowerPC/convert-rr-to-ri-instrs.mir
M llvm/test/CodeGen/PowerPC/ctrloop-do-not-duplicate-mi.mir
M llvm/test/CodeGen/PowerPC/livevars-crash2.mir
M llvm/test/CodeGen/PowerPC/peephole-phi-acc.mir
M llvm/test/CodeGen/PowerPC/peephole-replaceInstr-after-eliminate-extsw.mir
M llvm/test/CodeGen/PowerPC/phi-eliminate.mir
M llvm/test/CodeGen/PowerPC/remove-copy-crunsetcrbit.mir
M llvm/test/CodeGen/PowerPC/remove-implicit-use.mir
M llvm/test/CodeGen/PowerPC/remove-redundant-li-skip-imp-kill.mir
M llvm/test/CodeGen/PowerPC/remove-self-copies.mir
M llvm/test/CodeGen/PowerPC/rlwinm_rldicl_to_andi.mir
M llvm/test/CodeGen/PowerPC/schedule-addi-load.mir
M llvm/test/CodeGen/PowerPC/setcr_bc.mir
M llvm/test/CodeGen/PowerPC/setcr_bc2.mir
M llvm/test/CodeGen/PowerPC/setcr_bc3.mir
M llvm/test/CodeGen/PowerPC/tls_get_addr_fence1.mir
M llvm/test/CodeGen/PowerPC/tls_get_addr_fence2.mir
M llvm/test/CodeGen/PowerPC/two-address-crash.mir
M llvm/test/CodeGen/RISCV/live-sp.mir
M llvm/test/CodeGen/RISCV/pr53662.mir
M llvm/test/CodeGen/RISCV/rvv/addi-rvv-stack-object.mir
M llvm/test/CodeGen/RISCV/rvv/emergency-slot.mir
M llvm/test/CodeGen/RISCV/rvv/large-rvv-stack-size.mir
M llvm/test/CodeGen/RISCV/rvv/rvv-stack-align.mir
M llvm/test/CodeGen/RISCV/rvv/undef-earlyclobber-chain.mir
M llvm/test/CodeGen/RISCV/rvv/wrong-stack-offset-for-rvv-object.mir
M llvm/test/CodeGen/RISCV/stack-probing-frame-setup.mir
M llvm/test/CodeGen/RISCV/stack-slot-coloring.mir
M llvm/test/CodeGen/RISCV/xqcibi.ll
M llvm/test/CodeGen/RISCV/zcmp-prolog-epilog-crash.mir
M llvm/test/CodeGen/Thumb2/LowOverheadLoops/add_reduce.mir
M llvm/test/CodeGen/Thumb2/LowOverheadLoops/begin-vpt-without-inst.mir
M llvm/test/CodeGen/Thumb2/LowOverheadLoops/biquad-cascade-default.mir
M llvm/test/CodeGen/Thumb2/LowOverheadLoops/biquad-cascade-optsize-strd-lr.mir
M llvm/test/CodeGen/Thumb2/LowOverheadLoops/biquad-cascade-optsize.mir
M llvm/test/CodeGen/Thumb2/LowOverheadLoops/cond-mov.mir
M llvm/test/CodeGen/Thumb2/LowOverheadLoops/disjoint-vcmp.mir
M llvm/test/CodeGen/Thumb2/LowOverheadLoops/dont-ignore-vctp.mir
M llvm/test/CodeGen/Thumb2/LowOverheadLoops/dont-remove-loop-update.mir
M llvm/test/CodeGen/Thumb2/LowOverheadLoops/emptyblock.mir
M llvm/test/CodeGen/Thumb2/LowOverheadLoops/end-positive-offset.mir
M llvm/test/CodeGen/Thumb2/LowOverheadLoops/extract-element.mir
M llvm/test/CodeGen/Thumb2/LowOverheadLoops/incorrect-sub-16.mir
M llvm/test/CodeGen/Thumb2/LowOverheadLoops/incorrect-sub-32.mir
M llvm/test/CodeGen/Thumb2/LowOverheadLoops/incorrect-sub-8.mir
M llvm/test/CodeGen/Thumb2/LowOverheadLoops/inloop-vpnot-1.mir
M llvm/test/CodeGen/Thumb2/LowOverheadLoops/inloop-vpnot-2.mir
M llvm/test/CodeGen/Thumb2/LowOverheadLoops/inloop-vpnot-3.mir
M llvm/test/CodeGen/Thumb2/LowOverheadLoops/inloop-vpsel-1.mir
M llvm/test/CodeGen/Thumb2/LowOverheadLoops/inloop-vpsel-2.mir
M llvm/test/CodeGen/Thumb2/LowOverheadLoops/it-block-chain-store.mir
M llvm/test/CodeGen/Thumb2/LowOverheadLoops/it-block-chain.mir
M llvm/test/CodeGen/Thumb2/LowOverheadLoops/it-block-itercount.mir
M llvm/test/CodeGen/Thumb2/LowOverheadLoops/it-block-random.mir
M llvm/test/CodeGen/Thumb2/LowOverheadLoops/loop-dec-copy-chain.mir
M llvm/test/CodeGen/Thumb2/LowOverheadLoops/loop-dec-copy-prev-iteration.mir
M llvm/test/CodeGen/Thumb2/LowOverheadLoops/loop-dec-liveout.mir
M llvm/test/CodeGen/Thumb2/LowOverheadLoops/lstp-insertion-position.mir
M llvm/test/CodeGen/Thumb2/LowOverheadLoops/massive.mir
M llvm/test/CodeGen/Thumb2/LowOverheadLoops/matrix-debug.mir
M llvm/test/CodeGen/Thumb2/LowOverheadLoops/matrix.mir
M llvm/test/CodeGen/Thumb2/LowOverheadLoops/mov-after-dls.mir
M llvm/test/CodeGen/Thumb2/LowOverheadLoops/mov-after-dlstp.mir
M llvm/test/CodeGen/Thumb2/LowOverheadLoops/mov-lr-terminator.mir
M llvm/test/CodeGen/Thumb2/LowOverheadLoops/move-def-before-start.mir
M llvm/test/CodeGen/Thumb2/LowOverheadLoops/move-start-after-def.mir
M llvm/test/CodeGen/Thumb2/LowOverheadLoops/multiblock-massive.mir
M llvm/test/CodeGen/Thumb2/LowOverheadLoops/multiple-do-loops.mir
M llvm/test/CodeGen/Thumb2/LowOverheadLoops/mve-reduct-livein-arg.mir
M llvm/test/CodeGen/Thumb2/LowOverheadLoops/no-dec-cbnz.mir
M llvm/test/CodeGen/Thumb2/LowOverheadLoops/no-dec-reorder.mir
M llvm/test/CodeGen/Thumb2/LowOverheadLoops/no-dec.mir
M llvm/test/CodeGen/Thumb2/LowOverheadLoops/no-vpsel-liveout.mir
M llvm/test/CodeGen/Thumb2/LowOverheadLoops/non-masked-load.mir
M llvm/test/CodeGen/Thumb2/LowOverheadLoops/non-masked-store.mir
M llvm/test/CodeGen/Thumb2/LowOverheadLoops/out-of-range-cbz.mir
M llvm/test/CodeGen/Thumb2/LowOverheadLoops/remove-elem-moves.mir
M llvm/test/CodeGen/Thumb2/LowOverheadLoops/revert-after-call.mir
M llvm/test/CodeGen/Thumb2/LowOverheadLoops/revert-after-read.mir
M llvm/test/CodeGen/Thumb2/LowOverheadLoops/revert-after-write.mir
M llvm/test/CodeGen/Thumb2/LowOverheadLoops/revert-non-header.mir
M llvm/test/CodeGen/Thumb2/LowOverheadLoops/revert-non-loop.mir
M llvm/test/CodeGen/Thumb2/LowOverheadLoops/revert-while.mir
M llvm/test/CodeGen/Thumb2/LowOverheadLoops/safe-def-no-mov.mir
M llvm/test/CodeGen/Thumb2/LowOverheadLoops/safe-retaining.mir
M llvm/test/CodeGen/Thumb2/LowOverheadLoops/size-limit.mir
M llvm/test/CodeGen/Thumb2/LowOverheadLoops/skip-debug.mir
M llvm/test/CodeGen/Thumb2/LowOverheadLoops/skip-vpt-debug.mir
M llvm/test/CodeGen/Thumb2/LowOverheadLoops/switch.mir
M llvm/test/CodeGen/Thumb2/LowOverheadLoops/unrolled-and-vector.mir
M llvm/test/CodeGen/Thumb2/LowOverheadLoops/unsafe-cpsr-loop-def.mir
M llvm/test/CodeGen/Thumb2/LowOverheadLoops/unsafe-cpsr-loop-use.mir
M llvm/test/CodeGen/Thumb2/LowOverheadLoops/unsafe-use-after.mir
M llvm/test/CodeGen/Thumb2/LowOverheadLoops/vaddv.mir
M llvm/test/CodeGen/Thumb2/LowOverheadLoops/vctp-add-operand-liveout.mir
M llvm/test/CodeGen/Thumb2/LowOverheadLoops/vctp-in-vpt-2.mir
M llvm/test/CodeGen/Thumb2/LowOverheadLoops/vctp-in-vpt.mir
M llvm/test/CodeGen/Thumb2/LowOverheadLoops/vctp-subi3.mir
M llvm/test/CodeGen/Thumb2/LowOverheadLoops/vctp-subri.mir
M llvm/test/CodeGen/Thumb2/LowOverheadLoops/vctp-subri12.mir
M llvm/test/CodeGen/Thumb2/LowOverheadLoops/vctp16-reduce.mir
M llvm/test/CodeGen/Thumb2/LowOverheadLoops/vmaxmin_vpred_r.mir
M llvm/test/CodeGen/Thumb2/LowOverheadLoops/vmldava_in_vpt.mir
M llvm/test/CodeGen/Thumb2/LowOverheadLoops/vpt-block-debug.mir
M llvm/test/CodeGen/Thumb2/LowOverheadLoops/vpt-blocks.mir
M llvm/test/CodeGen/Thumb2/LowOverheadLoops/while-negative-offset.mir
M llvm/test/CodeGen/Thumb2/LowOverheadLoops/while.mir
M llvm/test/CodeGen/Thumb2/LowOverheadLoops/wlstp.mir
M llvm/test/CodeGen/Thumb2/LowOverheadLoops/wrong-liveout-lsr-shift.mir
M llvm/test/CodeGen/Thumb2/LowOverheadLoops/wrong-vctp-opcode-liveout.mir
M llvm/test/CodeGen/Thumb2/LowOverheadLoops/wrong-vctp-operand-liveout.mir
M llvm/test/CodeGen/Thumb2/bti-pac-replace-1.mir
M llvm/test/CodeGen/Thumb2/ifcvt-neon-deprecated.mir
M llvm/test/CodeGen/Thumb2/mve-vpt-2-blocks-1-pred.mir
M llvm/test/CodeGen/Thumb2/mve-vpt-2-blocks-2-preds.mir
M llvm/test/CodeGen/Thumb2/mve-vpt-2-blocks-ctrl-flow.mir
M llvm/test/CodeGen/Thumb2/mve-vpt-2-blocks-non-consecutive-ins.mir
M llvm/test/CodeGen/Thumb2/mve-vpt-2-blocks.mir
M llvm/test/CodeGen/Thumb2/mve-vpt-3-blocks-kill-vpr.mir
M llvm/test/CodeGen/Thumb2/mve-vpt-block-1-ins.mir
M llvm/test/CodeGen/Thumb2/mve-vpt-block-2-ins.mir
M llvm/test/CodeGen/Thumb2/mve-vpt-block-4-ins.mir
M llvm/test/CodeGen/Thumb2/mve-vpt-block-elses.mir
M llvm/test/CodeGen/Thumb2/mve-vpt-block-fold-vcmp.mir
M llvm/test/CodeGen/Thumb2/mve-vpt-block-optnone.mir
M llvm/test/CodeGen/Thumb2/mve-vpt-preuse.mir
M llvm/test/CodeGen/Thumb2/pipeliner-preserve-ties.mir
M llvm/test/CodeGen/VE/Scalar/fold-imm-addsl.mir
M llvm/test/CodeGen/VE/Scalar/fold-imm-cmpsl.mir
M llvm/test/CodeGen/WebAssembly/memcmp-expand.ll
M llvm/test/CodeGen/WebAssembly/multivalue-dont-move-def-past-use.mir
A llvm/test/CodeGen/WebAssembly/simd-setcc.ll
M llvm/test/CodeGen/X86/PR37310.mir
M llvm/test/CodeGen/X86/StackColoring-use-between-allocas.mir
M llvm/test/CodeGen/X86/align-basic-block-sections.mir
M llvm/test/CodeGen/X86/amx_tile_pair_configure_O0.mir
M llvm/test/CodeGen/X86/amx_tile_pair_configure_O2.mir
M llvm/test/CodeGen/X86/amx_tile_pair_copy.mir
M llvm/test/CodeGen/X86/amx_tile_pair_preconfigure_O0.mir
M llvm/test/CodeGen/X86/amx_tile_pair_preconfigure_O2.mir
M llvm/test/CodeGen/X86/apx/domain-reassignment.mir
M llvm/test/CodeGen/X86/apx/memfold-nd2rmw.mir
M llvm/test/CodeGen/X86/attr-dontcall.ll
M llvm/test/CodeGen/X86/attr-function-return.mir
M llvm/test/CodeGen/X86/avoid-sfb-g-no-change.mir
M llvm/test/CodeGen/X86/avoid-sfb-g-no-change2.mir
M llvm/test/CodeGen/X86/avoid-sfb-g-no-change3.mir
M llvm/test/CodeGen/X86/avoid-sfb-offset.mir
M llvm/test/CodeGen/X86/avx512f-256-set0.mir
M llvm/test/CodeGen/X86/basic-block-address-map-mir-parse.mir
M llvm/test/CodeGen/X86/basic-block-sections-mir-parse.mir
M llvm/test/CodeGen/X86/break-false-dep-crash.mir
M llvm/test/CodeGen/X86/callbr-asm-outputs-regallocfast.mir
M llvm/test/CodeGen/X86/cf-opt-memops.mir
M llvm/test/CodeGen/X86/cfi-epilogue-with-return.mir
M llvm/test/CodeGen/X86/cfi-epilogue-without-return.mir
M llvm/test/CodeGen/X86/conditional-tailcall-samedest.mir
M llvm/test/CodeGen/X86/cse-two-preds.mir
M llvm/test/CodeGen/X86/domain-reassignment.mir
M llvm/test/CodeGen/X86/movtopush.mir
M llvm/test/CodeGen/X86/peephole-test-after-add.mir
M llvm/test/CodeGen/X86/pr30821.mir
M llvm/test/CodeGen/X86/pr38952.mir
M llvm/test/CodeGen/X86/pr48064.mir
M llvm/test/CodeGen/X86/scheduler-asm-moves.mir
M llvm/test/CodeGen/X86/shrink_wrap_dbg_value.mir
M llvm/test/CodeGen/X86/statepoint-fixup-call.mir
M llvm/test/CodeGen/X86/statepoint-fixup-copy-prop-neg.mir
M llvm/test/CodeGen/X86/statepoint-fixup-invoke.mir
M llvm/test/CodeGen/X86/statepoint-fixup-shared-ehpad.mir
M llvm/test/CodeGen/X86/statepoint-fixup-undef-def.mir
M llvm/test/CodeGen/X86/statepoint-fixup-undef.mir
M llvm/test/CodeGen/X86/statepoint-invoke-ra-enter-at-end.mir
M llvm/test/CodeGen/X86/statepoint-invoke-ra-hoist-copies.mir
M llvm/test/CodeGen/X86/statepoint-invoke-ra-inline-spiller.mir
M llvm/test/CodeGen/X86/statepoint-invoke-ra-remove-back-copies.mir
M llvm/test/CodeGen/X86/statepoint-invoke-ra.mir
M llvm/test/CodeGen/X86/statepoint-vreg-folding.mir
M llvm/test/CodeGen/X86/tied-depbreak.mir
M llvm/test/CodeGen/X86/unfoldMemoryOperand.mir
M llvm/test/CodeGen/X86/win64-eh-empty-block-2.mir
M llvm/test/CodeGen/X86/zero-call-used-regs-debug-info.mir
M llvm/test/DebugInfo/ARM/machine-cp-updates-dbg-reg.mir
M llvm/test/DebugInfo/ARM/move-dbg-values-imm-test.mir
M llvm/test/DebugInfo/MIR/AArch64/implicit-def-dead-scope.mir
M llvm/test/DebugInfo/MIR/ARM/live-debug-values-reg-copy.mir
M llvm/test/DebugInfo/MIR/InstrRef/livedebugvalues-transfer-variadic-instr-ref.mir
M llvm/test/DebugInfo/MIR/Mips/last-inst-bundled.mir
M llvm/test/DebugInfo/MIR/Mips/live-debug-values-reg-copy.mir
M llvm/test/DebugInfo/MIR/X86/dbg-call-site-spilled-arg.mir
M llvm/test/DebugInfo/MIR/X86/debug-loc-0.mir
M llvm/test/DebugInfo/MIR/X86/instr-ref-join-def-vphi.mir
M llvm/test/DebugInfo/MIR/X86/kill-after-spill.mir
M llvm/test/DebugInfo/MIR/X86/live-debug-values-reg-copy.mir
M llvm/test/DebugInfo/MIR/X86/live-debug-values-restore.mir
M llvm/test/DebugInfo/MIR/X86/live-debug-vars-unused-arg-debugonly.mir
M llvm/test/DebugInfo/MIR/X86/live-debug-vars-unused-arg.mir
M llvm/test/DebugInfo/X86/instr-ref-track-clobbers.mir
M llvm/test/DebugInfo/X86/live-debug-vars-dse.mir
M llvm/test/MachineVerifier/verify-inlineasmbr.mir
M llvm/test/tools/UpdateTestChecks/update_mir_test_checks/Inputs/x86-MIFlags.mir
M llvm/test/tools/UpdateTestChecks/update_mir_test_checks/Inputs/x86-MIFlags.mir.expected
M llvm/test/tools/llvm-reduce/mir/preserve-frame-info.mir
M llvm/unittests/CodeGen/DroppedVariableStatsMIRTest.cpp
M mlir/test/mlir-tblgen/enums-python-bindings.td
M mlir/tools/mlir-tblgen/EnumPythonBindingGen.cpp
Log Message:
-----------
Merge branch 'main' into users/rampitec/08-12-_amdgpu_remove_dead_vop1_real_no_dpp_op_sel_with_name._nfc
Compare: https://github.com/llvm/llvm-project/compare/d62e41dae049...c9b00d554f6f
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