[all-commits] [llvm/llvm-project] b6e336: [AArch64][ISel] Select constructive EXT_ZZI pseudo...

[Gaëtan Bossu via All-commits]

  Branch: refs/heads/users/gbossu.vector.extract.movprfx.3
  Home:   https://github.com/llvm/llvm-project
  Commit: b6e3365b8573617f25495b5215be212cb3986f37
      https://github.com/llvm/llvm-project/commit/b6e3365b8573617f25495b5215be212cb3986f37
  Author: Gaëtan Bossu <gaetan.bossu at arm.com>
  Date:   2025-08-12 (Tue, 12 Aug 2025)

  Changed paths:
    M llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
    M llvm/test/CodeGen/AArch64/named-vector-shuffles-sve.ll
    M llvm/test/CodeGen/AArch64/sve-fixed-length-extract-subvector.ll
    M llvm/test/CodeGen/AArch64/sve-fixed-length-fp-to-int.ll
    M llvm/test/CodeGen/AArch64/sve-fixed-length-int-extends.ll
    M llvm/test/CodeGen/AArch64/sve-fixed-length-int-rem.ll
    M llvm/test/CodeGen/AArch64/sve-fixed-length-int-to-fp.ll
    M llvm/test/CodeGen/AArch64/sve-fixed-length-limit-duplane.ll
    M llvm/test/CodeGen/AArch64/sve-fixed-length-masked-loads.ll
    M llvm/test/CodeGen/AArch64/sve-fixed-length-partial-reduce.ll
    M llvm/test/CodeGen/AArch64/sve-fixed-length-shuffles.ll
    M llvm/test/CodeGen/AArch64/sve-fixed-vector-llrint.ll
    M llvm/test/CodeGen/AArch64/sve-fixed-vector-lrint.ll
    M llvm/test/CodeGen/AArch64/sve-pr92779.ll
    M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-fp-extend-trunc.ll
    M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-fp-to-int.ll
    M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-int-extends.ll
    M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-int-rem.ll
    M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-int-to-fp.ll
    M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-limit-duplane.ll
    M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-masked-load.ll
    M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-masked-store.ll
    M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-reductions.ll

  Log Message:
  -----------
  [AArch64][ISel] Select constructive EXT_ZZI pseudo instruction

The patch adds patterns to select the EXT_ZZI_CONSTRUCTIVE pseudo
instead of the EXT_ZZI destructive instruction for vector_splice. This
only works when the two inputs to vector_splice are identical.

Given that registers aren't tied anymore, this gives the register
allocator more freedom and a lot of MOVs get replaced with MOVPRFX.

In some cases however, we could have just chosen the same input and
output register, but regalloc preferred not to. This means we end up
with some test cases now having more instructions: there is now a
MOVPRFX while no MOV was previously needed.



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