[all-commits] [llvm/llvm-project] e6b4da: [AArch64] Support MI and PL (#150314)

[AZero13 via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: e6b4daf48c1a7e5c7578ee5de4a2f65de6f36967
      https://github.com/llvm/llvm-project/commit/e6b4daf48c1a7e5c7578ee5de4a2f65de6f36967
  Author: AZero13 <gfunni234 at gmail.com>
  Date:   2025-08-11 (Mon, 11 Aug 2025)

  Changed paths:
    M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
    M llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp
    M llvm/test/CodeGen/AArch64/16bit-float-promotion-with-nofp.ll
    M llvm/test/CodeGen/AArch64/GlobalISel/opt-and-tbnz-tbz.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/postlegalizer-lowering-adjust-icmp-imm.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/select-tbnz-from-cmp.mir
    M llvm/test/CodeGen/AArch64/arm64-ccmp.ll
    M llvm/test/CodeGen/AArch64/arm64-fmax.ll
    M llvm/test/CodeGen/AArch64/arm64-fp128.ll
    M llvm/test/CodeGen/AArch64/arm64-vabs.ll
    M llvm/test/CodeGen/AArch64/check-sign-bit-before-extension.ll
    M llvm/test/CodeGen/AArch64/combine-sdiv.ll
    M llvm/test/CodeGen/AArch64/csel-cmp-cse.ll
    M llvm/test/CodeGen/AArch64/fast-isel-sdiv.ll
    M llvm/test/CodeGen/AArch64/fcmp-fp128.ll
    M llvm/test/CodeGen/AArch64/fcmp.ll
    M llvm/test/CodeGen/AArch64/fp-intrinsics.ll
    M llvm/test/CodeGen/AArch64/fpclamptosat.ll
    M llvm/test/CodeGen/AArch64/fpclamptosat_vec.ll
    M llvm/test/CodeGen/AArch64/fptosi-sat-scalar.ll
    M llvm/test/CodeGen/AArch64/fptosi-sat-vector.ll
    M llvm/test/CodeGen/AArch64/fptoui-sat-scalar.ll
    M llvm/test/CodeGen/AArch64/fptoui-sat-vector.ll
    M llvm/test/CodeGen/AArch64/logical_shifted_reg.ll
    M llvm/test/CodeGen/AArch64/min-max-combine.ll
    M llvm/test/CodeGen/AArch64/pr72777.ll
    M llvm/test/CodeGen/AArch64/sdivpow2.ll
    M llvm/test/CodeGen/AArch64/select-constant-xor.ll
    M llvm/test/CodeGen/AArch64/selectcc-to-shiftand.ll
    M llvm/test/CodeGen/AArch64/signbit-shift.ll
    M llvm/test/CodeGen/AArch64/smul_fix_sat.ll
    M llvm/test/CodeGen/AArch64/srem-pow2.ll
    M llvm/test/CodeGen/AArch64/sshl_sat.ll
    M llvm/test/CodeGen/AArch64/stack-hazard.ll
    M llvm/test/CodeGen/AArch64/tbz-tbnz.ll
    M llvm/test/CodeGen/AArch64/vecreduce-bool.ll
    M llvm/test/CodeGen/AArch64/vecreduce-fmin-legalization.ll

  Log Message:
  -----------
  [AArch64] Support MI and PL (#150314)

Now, why would we want to do this?

There are a small number of places where this works:
1. It helps peepholeopt when less flag checking.
2. It allows the folding of things such as x - 0x80000000 < 0 to be
folded to cmp x, register holding this value
3. We can refine the other passes over time for this.



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