[all-commits] [llvm/llvm-project] c65308: AMDGPU: Add new VA inline asm constraint for AV re...

[Matt Arsenault via All-commits]

  Branch: refs/heads/users/arsenm/amdgpu/add-VA-inline-asm-constraint-av-class
  Home:   https://github.com/llvm/llvm-project
  Commit: c653089ed3464423be881942a19bb3e85ffb1d27
      https://github.com/llvm/llvm-project/commit/c653089ed3464423be881942a19bb3e85ffb1d27
  Author: Matt Arsenault <Matthew.Arsenault at amd.com>
  Date:   2025-08-08 (Fri, 08 Aug 2025)

  Changed paths:
    M llvm/docs/LangRef.rst
    M llvm/lib/Target/AMDGPU/SIISelLowering.cpp
    A llvm/test/CodeGen/AMDGPU/inline-asm-av-constraint-err.ll
    A llvm/test/CodeGen/AMDGPU/inline-asm-av-constraint.ll

  Log Message:
  -----------
  AMDGPU: Add new VA inline asm constraint for AV registers

Add a new constraint corresponding to the AV_* register classes
for operands which can allocate AGPRs or VGPRs. This applies
to load and stores on gfx90a+, and srcA / srcB for MFMA instructions.

The error emitted on unsupported targets isn't ideal, it is
produced by the register allocator without a rationale, but it is
consistent with the existing errors.

I mostly want this for writing allocation tests.



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