[all-commits] [llvm/llvm-project] 707447: [RISCV] Enable tail folding by default (#151681)

[Luke Lau via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 707447159341f7b5678dee4f47731af50524b9ae
      https://github.com/llvm/llvm-project/commit/707447159341f7b5678dee4f47731af50524b9ae
  Author: Luke Lau <luke at igalia.com>
  Date:   2025-08-08 (Fri, 08 Aug 2025)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVTargetTransformInfo.h
    M llvm/test/Transforms/LoopVectorize/RISCV/bf16.ll
    M llvm/test/Transforms/LoopVectorize/RISCV/blend-any-of-reduction-cost.ll
    M llvm/test/Transforms/LoopVectorize/RISCV/blocks-with-dead-instructions.ll
    M llvm/test/Transforms/LoopVectorize/RISCV/dead-ops-cost.ll
    M llvm/test/Transforms/LoopVectorize/RISCV/defaults.ll
    M llvm/test/Transforms/LoopVectorize/RISCV/divrem.ll
    M llvm/test/Transforms/LoopVectorize/RISCV/f16.ll
    M llvm/test/Transforms/LoopVectorize/RISCV/fminimumnum.ll
    M llvm/test/Transforms/LoopVectorize/RISCV/force-vect-msg.ll
    M llvm/test/Transforms/LoopVectorize/RISCV/induction-costs.ll
    M llvm/test/Transforms/LoopVectorize/RISCV/interleaved-accesses.ll
    M llvm/test/Transforms/LoopVectorize/RISCV/interleaved-cost.ll
    M llvm/test/Transforms/LoopVectorize/RISCV/lmul.ll
    M llvm/test/Transforms/LoopVectorize/RISCV/low-trip-count.ll
    M llvm/test/Transforms/LoopVectorize/RISCV/mask-index-type.ll
    M llvm/test/Transforms/LoopVectorize/RISCV/masked_gather_scatter.ll
    M llvm/test/Transforms/LoopVectorize/RISCV/partial-reduce-dot-product.ll
    M llvm/test/Transforms/LoopVectorize/RISCV/pr87378-vpinstruction-or-drop-poison-generating-flags.ll
    M llvm/test/Transforms/LoopVectorize/RISCV/reductions.ll
    M llvm/test/Transforms/LoopVectorize/RISCV/reg-usage-bf16.ll
    M llvm/test/Transforms/LoopVectorize/RISCV/reg-usage-f16.ll
    M llvm/test/Transforms/LoopVectorize/RISCV/reg-usage.ll
    M llvm/test/Transforms/LoopVectorize/RISCV/remark-reductions.ll
    M llvm/test/Transforms/LoopVectorize/RISCV/riscv-vector-reverse.ll
    M llvm/test/Transforms/LoopVectorize/RISCV/safe-dep-distance.ll
    M llvm/test/Transforms/LoopVectorize/RISCV/scalable-basics.ll
    M llvm/test/Transforms/LoopVectorize/RISCV/select-cmp-reduction.ll
    M llvm/test/Transforms/LoopVectorize/RISCV/short-trip-count.ll
    M llvm/test/Transforms/LoopVectorize/RISCV/strided-accesses.ll
    M llvm/test/Transforms/LoopVectorize/RISCV/truncate-to-minimal-bitwidth-cost.ll
    M llvm/test/Transforms/LoopVectorize/RISCV/uniform-load-store.ll
    M llvm/test/Transforms/LoopVectorize/RISCV/vf-will-not-generate-any-vector-insts.ll
    M llvm/test/Transforms/LoopVectorize/RISCV/vplan-riscv-vector-reverse.ll

  Log Message:
  -----------
  [RISCV] Enable tail folding by default (#151681)

We have been tracking the performance of EVL tail folding in the loop
vectorizer on RISC-V for a while now, and after much hard work from
various contributors we think it should be generally profitable to
enable by default now.

With tail folding there is a 21% improvement on 525.x264_r on SPEC CPU
2017 on the BPI-F3 (-march=rva22u64_v -O3 -flto), as well as a 30%
geomean codesize reduction on SPEC and TSVC, with no significant
regressions detected.

Now that we are early into the LLVM 22.x development cycle it seems like
a good time to enable it to catch any issues. There are still more EVL
related items of work being tracked in #123069, which should continue to
improve performance.



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