[all-commits] [llvm/llvm-project] 4ad6ac: [AArch64] WIP Regalloc hints for EXT_ZZZI

[Gaëtan Bossu via All-commits]

  Branch: refs/heads/users/gbossu.vector.extract.movprfx.3
  Home:   https://github.com/llvm/llvm-project
  Commit: 4ad6acfeb2db77dd2bd64958cf3fa877c2af528c
      https://github.com/llvm/llvm-project/commit/4ad6acfeb2db77dd2bd64958cf3fa877c2af528c
  Author: Gaëtan Bossu <gaetan.bossu at arm.com>
  Date:   2025-08-07 (Thu, 07 Aug 2025)

  Changed paths:
    M llvm/lib/Target/AArch64/AArch64PostCoalescerPass.cpp
    M llvm/test/CodeGen/AArch64/named-vector-shuffles-sve.ll

  Log Message:
  -----------
  [AArch64] WIP Regalloc hints for EXT_ZZZI

This tries to ensure that the dst and first src register are mapped to
the same physical register. This isn't always possible because the
MachineScheduler has already moved instructions in a way that causes
interferences if both virt regs get mapped to the same phys reg.

WIP because there is probably a better place to do this.



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