[all-commits] [llvm/llvm-project] 426120: [Intrinsics][AArch64] Add intrinsic to mask off al...
Sam Tebbs via All-commits
all-commits at lists.llvm.org
Thu Aug 7 02:19:07 PDT 2025
Branch: refs/heads/users/SamTebbs33/alias-intrinsic
Home: https://github.com/llvm/llvm-project
Commit: 426120a0dc6c3c35897b6535069fc138e9900d3b
https://github.com/llvm/llvm-project/commit/426120a0dc6c3c35897b6535069fc138e9900d3b
Author: Sam Tebbs <samuel.tebbs at arm.com>
Date: 2025-08-05 (Tue, 05 Aug 2025)
Changed paths:
M llvm/docs/LangRef.rst
M llvm/include/llvm/CodeGen/TargetLowering.h
M llvm/include/llvm/IR/Intrinsics.td
M llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
M llvm/lib/Target/AArch64/AArch64ISelLowering.h
M llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
M llvm/lib/Target/AArch64/SVEInstrFormats.td
A llvm/test/CodeGen/AArch64/alias_mask.ll
A llvm/test/CodeGen/AArch64/alias_mask_scalable.ll
Log Message:
-----------
[Intrinsics][AArch64] Add intrinsic to mask off aliasing vector lanes
It can be unsafe to load a vector from an address and write a vector to
an address if those two addresses have overlapping lanes within a
vectorised loop iteration.
This PR adds an intrinsic designed to create a mask with lanes disabled
if they overlap between the two pointer arguments, so that only safe
lanes are loaded, operated on and stored.
Along with the two pointer parameters, the intrinsic also takes an
immediate that represents the size in bytes of the vector element
types, as well as an immediate i1 that is true if there is a write
after-read-hazard or false if there is a read-after-write hazard.
This will be used by #100579 and replaces the existing lowering for
whilewr since that isn't needed now we have the intrinsic.
Commit: 19dd02933c8f40047baeb3044718a64f652e1e94
https://github.com/llvm/llvm-project/commit/19dd02933c8f40047baeb3044718a64f652e1e94
Author: Sam Tebbs <samuel.tebbs at arm.com>
Date: 2025-08-05 (Tue, 05 Aug 2025)
Changed paths:
M llvm/include/llvm/CodeGen/ISDOpcodes.h
M llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
M llvm/lib/CodeGen/SelectionDAG/LegalizeTypes.h
M llvm/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp
M llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
M llvm/lib/CodeGen/SelectionDAG/SelectionDAGDumper.cpp
M llvm/lib/CodeGen/TargetLoweringBase.cpp
M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
M llvm/lib/Target/AArch64/AArch64ISelLowering.h
M llvm/test/CodeGen/AArch64/alias_mask.ll
M llvm/test/CodeGen/AArch64/alias_mask_scalable.ll
Log Message:
-----------
Rework lowering location
Commit: 1f8b4beada7748136f19111e5186feb0232fc678
https://github.com/llvm/llvm-project/commit/1f8b4beada7748136f19111e5186feb0232fc678
Author: Samuel Tebbs <samuel.tebbs at arm.com>
Date: 2025-08-05 (Tue, 05 Aug 2025)
Changed paths:
M llvm/lib/CodeGen/SelectionDAG/SelectionDAGDumper.cpp
M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
M llvm/lib/Target/AArch64/AArch64ISelLowering.h
Log Message:
-----------
Fix ISD node name string and remove shouldExpand function
Commit: 5298aa025b880cfd95fff248694bebaec8a2330c
https://github.com/llvm/llvm-project/commit/5298aa025b880cfd95fff248694bebaec8a2330c
Author: Samuel Tebbs <samuel.tebbs at arm.com>
Date: 2025-08-05 (Tue, 05 Aug 2025)
Changed paths:
M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
Log Message:
-----------
Format
Commit: 13a64e536f0170ef6f3c68a3bfeba90c92f6acbd
https://github.com/llvm/llvm-project/commit/13a64e536f0170ef6f3c68a3bfeba90c92f6acbd
Author: Sam Tebbs <samuel.tebbs at arm.com>
Date: 2025-08-05 (Tue, 05 Aug 2025)
Changed paths:
M llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
Log Message:
-----------
Move promote case
Commit: 48af641992fd8b711e324d79d0628eea44b1ee31
https://github.com/llvm/llvm-project/commit/48af641992fd8b711e324d79d0628eea44b1ee31
Author: Sam Tebbs <samuel.tebbs at arm.com>
Date: 2025-08-05 (Tue, 05 Aug 2025)
Changed paths:
M llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
Log Message:
-----------
Fix tablegen comment
Commit: e398a01bba838f8a4c37522a3e1303e45aa1da57
https://github.com/llvm/llvm-project/commit/e398a01bba838f8a4c37522a3e1303e45aa1da57
Author: Sam Tebbs <samuel.tebbs at arm.com>
Date: 2025-08-05 (Tue, 05 Aug 2025)
Changed paths:
M llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
Log Message:
-----------
Remove DAGTypeLegalizer::
Commit: 8e27911a40ee34b5f3fcf9586f385922c3c51cf7
https://github.com/llvm/llvm-project/commit/8e27911a40ee34b5f3fcf9586f385922c3c51cf7
Author: Sam Tebbs <samuel.tebbs at arm.com>
Date: 2025-08-05 (Tue, 05 Aug 2025)
Changed paths:
M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
Log Message:
-----------
Use getConstantOperandVal
Commit: 8e2a8a7befcae55f15c688e13a3b223c9527d056
https://github.com/llvm/llvm-project/commit/8e2a8a7befcae55f15c688e13a3b223c9527d056
Author: Samuel Tebbs <samuel.tebbs at arm.com>
Date: 2025-08-05 (Tue, 05 Aug 2025)
Changed paths:
M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
Log Message:
-----------
Remove isPredicateCCSettingOp case
Commit: a3f0ca2fe83c9d3db5c7f2a8dbb97847f40d68a6
https://github.com/llvm/llvm-project/commit/a3f0ca2fe83c9d3db5c7f2a8dbb97847f40d68a6
Author: Samuel Tebbs <samuel.tebbs at arm.com>
Date: 2025-08-05 (Tue, 05 Aug 2025)
Changed paths:
M llvm/docs/LangRef.rst
M llvm/include/llvm/IR/Intrinsics.td
M llvm/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp
M llvm/test/CodeGen/AArch64/alias_mask.ll
M llvm/test/CodeGen/AArch64/alias_mask_scalable.ll
Log Message:
-----------
Remove overloads for pointer and element size parameters
Commit: 1d4ed61a7c3c5afca609532db1543c15a89f5a48
https://github.com/llvm/llvm-project/commit/1d4ed61a7c3c5afca609532db1543c15a89f5a48
Author: Samuel Tebbs <samuel.tebbs at arm.com>
Date: 2025-08-05 (Tue, 05 Aug 2025)
Changed paths:
M llvm/docs/LangRef.rst
Log Message:
-----------
Clarify elementSize and writeAfterRead = 0
Commit: 08afd28599d4adc901cb63055e36f0eedf4192fa
https://github.com/llvm/llvm-project/commit/08afd28599d4adc901cb63055e36f0eedf4192fa
Author: Samuel Tebbs <samuel.tebbs at arm.com>
Date: 2025-08-05 (Tue, 05 Aug 2025)
Changed paths:
M llvm/docs/LangRef.rst
Log Message:
-----------
Add i=0 to VF-1
Commit: dc22872db713389d39f84257056225c203ae5a0f
https://github.com/llvm/llvm-project/commit/dc22872db713389d39f84257056225c203ae5a0f
Author: Samuel Tebbs <samuel.tebbs at arm.com>
Date: 2025-08-05 (Tue, 05 Aug 2025)
Changed paths:
M llvm/docs/LangRef.rst
M llvm/include/llvm/CodeGen/ISDOpcodes.h
M llvm/include/llvm/IR/Intrinsics.td
M llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
M llvm/lib/CodeGen/SelectionDAG/LegalizeTypes.h
M llvm/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp
M llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
M llvm/lib/CodeGen/SelectionDAG/SelectionDAGDumper.cpp
M llvm/lib/CodeGen/TargetLoweringBase.cpp
M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
M llvm/lib/Target/AArch64/AArch64ISelLowering.h
M llvm/test/CodeGen/AArch64/alias_mask.ll
M llvm/test/CodeGen/AArch64/alias_mask_scalable.ll
Log Message:
-----------
Rename to get.nonalias.lane.mask
Commit: 46807c0cb541bb3687684449ef7469753c72a01e
https://github.com/llvm/llvm-project/commit/46807c0cb541bb3687684449ef7469753c72a01e
Author: Samuel Tebbs <samuel.tebbs at arm.com>
Date: 2025-08-05 (Tue, 05 Aug 2025)
Changed paths:
M llvm/docs/LangRef.rst
Log Message:
-----------
Fix pointer types in example
Commit: 3c9e437076430f9656434315dbcf1f6347db1165
https://github.com/llvm/llvm-project/commit/3c9e437076430f9656434315dbcf1f6347db1165
Author: Samuel Tebbs <samuel.tebbs at arm.com>
Date: 2025-08-05 (Tue, 05 Aug 2025)
Changed paths:
M llvm/include/llvm/CodeGen/TargetLowering.h
Log Message:
-----------
Remove shouldExpandGetAliasLaneMask
Commit: 83c5404bd466ecf27680956218423235755b7f88
https://github.com/llvm/llvm-project/commit/83c5404bd466ecf27680956218423235755b7f88
Author: Samuel Tebbs <samuel.tebbs at arm.com>
Date: 2025-08-05 (Tue, 05 Aug 2025)
Changed paths:
M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
Log Message:
-----------
Lower to ISD node rather than intrinsic
Commit: f0976197d640ad56b3a22ed94f1c92633d7f112d
https://github.com/llvm/llvm-project/commit/f0976197d640ad56b3a22ed94f1c92633d7f112d
Author: Sam Tebbs <samuel.tebbs at arm.com>
Date: 2025-08-05 (Tue, 05 Aug 2025)
Changed paths:
M llvm/docs/LangRef.rst
M llvm/include/llvm/CodeGen/ISDOpcodes.h
M llvm/include/llvm/IR/Intrinsics.td
M llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
M llvm/lib/CodeGen/SelectionDAG/LegalizeTypes.h
M llvm/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp
M llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
M llvm/lib/CodeGen/SelectionDAG/SelectionDAGDumper.cpp
M llvm/lib/CodeGen/TargetLoweringBase.cpp
M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
M llvm/lib/Target/AArch64/AArch64ISelLowering.h
M llvm/test/CodeGen/AArch64/alias_mask.ll
M llvm/test/CodeGen/AArch64/alias_mask_scalable.ll
Log Message:
-----------
Rename to noalias
Commit: e17b06f4fb3fb1d762d806aea49fabf9d0891ab5
https://github.com/llvm/llvm-project/commit/e17b06f4fb3fb1d762d806aea49fabf9d0891ab5
Author: Samuel Tebbs <samuel.tebbs at arm.com>
Date: 2025-08-05 (Tue, 05 Aug 2025)
Changed paths:
M llvm/include/llvm/CodeGen/ISDOpcodes.h
M llvm/include/llvm/IR/Intrinsics.td
M llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
M llvm/lib/CodeGen/SelectionDAG/LegalizeTypes.h
M llvm/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp
M llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
M llvm/lib/CodeGen/SelectionDAG/SelectionDAGDumper.cpp
M llvm/lib/CodeGen/TargetLoweringBase.cpp
M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
M llvm/lib/Target/AArch64/AArch64ISelLowering.h
M llvm/test/CodeGen/AArch64/alias_mask.ll
M llvm/test/CodeGen/AArch64/alias_mask_scalable.ll
Log Message:
-----------
Rename to loop.dependence.raw/war.mask
Commit: 68816d7bf6aa7bdacd239a84a9bb402e83c7e980
https://github.com/llvm/llvm-project/commit/68816d7bf6aa7bdacd239a84a9bb402e83c7e980
Author: Samuel Tebbs <samuel.tebbs at arm.com>
Date: 2025-08-05 (Tue, 05 Aug 2025)
Changed paths:
M llvm/docs/LangRef.rst
Log Message:
-----------
Rename in langref
Commit: b43f31dc638564de4038df8b7345de4d94e2af49
https://github.com/llvm/llvm-project/commit/b43f31dc638564de4038df8b7345de4d94e2af49
Author: Sam Tebbs <samuel.tebbs at arm.com>
Date: 2025-08-05 (Tue, 05 Aug 2025)
Changed paths:
M llvm/docs/LangRef.rst
Log Message:
-----------
Reword argument description
Commit: 7dbdf5218e53f84e0d0ea8eaa2922c7221adf0ce
https://github.com/llvm/llvm-project/commit/7dbdf5218e53f84e0d0ea8eaa2922c7221adf0ce
Author: Samuel Tebbs <samuel.tebbs at arm.com>
Date: 2025-08-05 (Tue, 05 Aug 2025)
Changed paths:
M llvm/docs/LangRef.rst
Log Message:
-----------
Fixup langref
Commit: bb79200125299e4c003e71402851329c79a807b2
https://github.com/llvm/llvm-project/commit/bb79200125299e4c003e71402851329c79a807b2
Author: Samuel Tebbs <samuel.tebbs at arm.com>
Date: 2025-08-05 (Tue, 05 Aug 2025)
Changed paths:
M llvm/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp
M llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
Log Message:
-----------
IsWriteAfterRead -> IsReadAfterWrite and avoid using ops vector
Commit: c164ff0bbd4dd3d43d4721dd827bf5d5e7528d8f
https://github.com/llvm/llvm-project/commit/c164ff0bbd4dd3d43d4721dd827bf5d5e7528d8f
Author: Samuel Tebbs <samuel.tebbs at arm.com>
Date: 2025-08-05 (Tue, 05 Aug 2025)
Changed paths:
M llvm/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp
M llvm/test/CodeGen/AArch64/alias_mask.ll
Log Message:
-----------
Extend vXi1 setcc to account for intrinsic VT promotion
Commit: 328f0154f2d7c41123b30cb7ec2a306a8755d78a
https://github.com/llvm/llvm-project/commit/328f0154f2d7c41123b30cb7ec2a306a8755d78a
Author: Sam Tebbs <samuel.tebbs at arm.com>
Date: 2025-08-05 (Tue, 05 Aug 2025)
Changed paths:
M llvm/docs/LangRef.rst
M llvm/include/llvm/CodeGen/ISDOpcodes.h
M llvm/include/llvm/IR/Intrinsics.td
M llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
M llvm/lib/CodeGen/SelectionDAG/LegalizeTypes.h
M llvm/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp
M llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
M llvm/lib/CodeGen/SelectionDAG/SelectionDAGDumper.cpp
M llvm/lib/CodeGen/TargetLoweringBase.cpp
M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
M llvm/test/CodeGen/AArch64/alias_mask.ll
M llvm/test/CodeGen/AArch64/alias_mask_scalable.ll
Log Message:
-----------
Remove experimental from intrinsic name
Commit: 0ca7dd6da3d109bbc8d286a3287451afade78473
https://github.com/llvm/llvm-project/commit/0ca7dd6da3d109bbc8d286a3287451afade78473
Author: Sam Tebbs <samuel.tebbs at arm.com>
Date: 2025-08-05 (Tue, 05 Aug 2025)
Changed paths:
M llvm/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp
M llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
Log Message:
-----------
Clean up vector type creation
Commit: 3b40d862b945bab62e6952839881be0c1f1866d2
https://github.com/llvm/llvm-project/commit/3b40d862b945bab62e6952839881be0c1f1866d2
Author: Sam Tebbs <samuel.tebbs at arm.com>
Date: 2025-08-05 (Tue, 05 Aug 2025)
Changed paths:
M llvm/docs/LangRef.rst
M llvm/include/llvm/Target/TargetSelectionDAG.td
M llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
M llvm/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp
M llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
M llvm/lib/CodeGen/TargetLoweringBase.cpp
M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
M llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
M llvm/lib/Target/AArch64/SVEInstrFormats.td
M llvm/test/CodeGen/AArch64/alias_mask.ll
M llvm/test/CodeGen/AArch64/alias_mask_scalable.ll
Log Message:
-----------
Address review
Compare: https://github.com/llvm/llvm-project/compare/8822b8fcffab...3b40d862b945
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