[all-commits] [llvm/llvm-project] b9e133: [AArch64][SVE] Use FeatureUseFixedOverScalableIfEq...

[Ties Stuij via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: b9e133d5b6e41b652ba579bcb8850c00f72d0f01
      https://github.com/llvm/llvm-project/commit/b9e133d5b6e41b652ba579bcb8850c00f72d0f01
  Author: Ties Stuij <ties.stuij at arm.com>
  Date:   2025-08-07 (Thu, 07 Aug 2025)

  Changed paths:
    M llvm/lib/Target/AArch64/AArch64Processors.td
    M llvm/test/Transforms/LoopVectorize/AArch64/sve-fixed-width-inorder-core.ll

  Log Message:
  -----------
  [AArch64][SVE] Use FeatureUseFixedOverScalableIfEqualCost for A320 (#152156)

With this new A320 in-order core, we follow adding the
FeatureUseFixedOverScalableIfEqualCost feature to A510 and A520
(#132246), which reaps the same code generation benefits of preferring
fixed over scalable when the cost is equal.

So when we have:
```
void foo(float* a, float* b, float* dst, unsigned n) {
    for (unsigned i = 0; i < n; ++i)
        dst[i] = a[i] + b[i];
}
```

When compiling without the feature enabled, we get:
```
...
    ld1b    { z0.b }, p0/z, [x0, x10]
    ld1b    { z2.b }, p0/z, [x1, x10]
    add     x12, x0, x10
    ldr     z1, [x12, #1, mul vl]
    add     x12, x1, x10
    ldr     z3, [x12, #1, mul vl]
    fadd    z0.s, z2.s, z0.s
    add     x12, x2, x10
    fadd    z1.s, z3.s, z1.s
    dech    x11
    st1b    { z0.b }, p0, [x2, x10]
    incb    x10, all, mul #2
    str     z1, [x12, #1, mul vl]
...
```

When compiling with, we get:
```
...
  	ldp	    q0, q1, [x12, #-16]
	ldp	    q2, q3, [x11, #-16]
	subs	x13, x13, #8
	fadd	v0.4s, v2.4s, v0.4s
	fadd	v1.4s, v3.4s, v1.4s
	add	    x11, x11, #32
	add	    x12, x12, #32
	stp	    q0, q1, [x10, #-16]
	add	    x10, x10, #32

...
```



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