[all-commits] [llvm/llvm-project] 9f7f3d: [CIR] Implemented get/set for volatile bitfields (...
Stanislav Mekhanoshin via All-commits
all-commits at lists.llvm.org
Mon Aug 4 15:29:56 PDT 2025
Branch: refs/heads/users/rampitec/08-04-_amdgpu_gfx1250_v_wmma_scale_16__f32_16x16x128_f8f6f4_codegen
Home: https://github.com/llvm/llvm-project
Commit: 9f7f3d65483769cba287242120362f8e21407e8d
https://github.com/llvm/llvm-project/commit/9f7f3d65483769cba287242120362f8e21407e8d
Author: Andres-Salamanca <andrealebarbaritos at gmail.com>
Date: 2025-08-04 (Mon, 04 Aug 2025)
Changed paths:
M clang/lib/CIR/CodeGen/CIRGenBuilder.h
M clang/lib/CIR/CodeGen/CIRGenExpr.cpp
M clang/lib/CIR/CodeGen/CIRGenRecordLayoutBuilder.cpp
M clang/test/CIR/CodeGen/aapcs-volatile-bitfields.c
Log Message:
-----------
[CIR] Implemented get/set for volatile bitfields (#151875)
This PR adds support for loading and storing volatile bit-field members
according to the AAPCS specification.
> A volatile bit-field must always be accessed using an access width
appropriate to the type of its container, except when any of the
following are true:
>
> * The bit-field container overlaps with a zero-length bit-field.
> * The bit-field container overlaps with a non-bit-field member.
For example, if a bit-field is declared as `int`, the load/store must
use a 32-bit access, even if the field itself is only 3 bits wide.
Commit: 8b3559f36b0b382634fc64ba133c66647fc5cd13
https://github.com/llvm/llvm-project/commit/8b3559f36b0b382634fc64ba133c66647fc5cd13
Author: Stanislav Mekhanoshin <Stanislav.Mekhanoshin at amd.com>
Date: 2025-08-04 (Mon, 04 Aug 2025)
Changed paths:
M clang/lib/CIR/CodeGen/CIRGenBuilder.h
M clang/lib/CIR/CodeGen/CIRGenExpr.cpp
M clang/lib/CIR/CodeGen/CIRGenRecordLayoutBuilder.cpp
M clang/test/CIR/CodeGen/aapcs-volatile-bitfields.c
Log Message:
-----------
Merge branch 'main' into users/rampitec/08-04-_amdgpu_gfx1250_v_wmma_scale_16__f32_16x16x128_f8f6f4_codegen
Compare: https://github.com/llvm/llvm-project/compare/3fc777f4f0ef...8b3559f36b0b
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