[all-commits] [llvm/llvm-project] 401e72: [RISCV] Add intrinsics for strided segment loads w...

[Min-Yih Hsu via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 401e72c830e4ac7ea334e9e62366bc50f72fbfeb
      https://github.com/llvm/llvm-project/commit/401e72c830e4ac7ea334e9e62366bc50f72fbfeb
  Author: Min-Yih Hsu <min.hsu at sifive.com>
  Date:   2025-08-01 (Fri, 01 Aug 2025)

  Changed paths:
    M llvm/include/llvm/IR/IntrinsicsRISCV.td
    M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
    A llvm/test/CodeGen/RISCV/rvv/fixed-vectors-ssegN-load.ll

  Log Message:
  -----------
  [RISCV] Add intrinsics for strided segment loads with fixed vectors (#151611)

These intrinsics are the strided version of `llvm.riscv.segN.load`
intrinsics.



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