[all-commits] [llvm/llvm-project] f573d2: [AArch64][ISel] Select constructive SVE2 ext instr...

[Gaëtan Bossu via All-commits]

  Branch: refs/heads/users/gbossu.vector.extract.2
  Home:   https://github.com/llvm/llvm-project
  Commit: f573d2e983e34a2f99a37976d4956e7aa7c62acd
      https://github.com/llvm/llvm-project/commit/f573d2e983e34a2f99a37976d4956e7aa7c62acd
  Author: Gaëtan Bossu <gaetan.bossu at arm.com>
  Date:   2025-08-01 (Fri, 01 Aug 2025)

  Changed paths:
    M llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
    M llvm/test/CodeGen/AArch64/get-active-lane-mask-extract.ll
    M llvm/test/CodeGen/AArch64/sve-fixed-length-partial-reduce.ll
    M llvm/test/CodeGen/AArch64/sve-pr92779.ll
    M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-ext-loads.ll
    M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-extract-subvector.ll
    M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-fp-extend-trunc.ll
    M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-int-div.ll
    M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-int-extends.ll
    M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-int-rem.ll
    M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-limit-duplane.ll
    M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-reductions.ll
    A llvm/test/CodeGen/AArch64/sve-vector-splice.ll
    M llvm/test/CodeGen/AArch64/sve2-fixed-length-extract-subvector.ll

  Log Message:
  -----------
  [AArch64][ISel] Select constructive SVE2 ext instruction

This adds patterns for selecting EXT_ZZI_B.

They are tested for fixed vectors using extract shuffles, and for
scalable vectors using llvm.vector.splice intrinsics.

We will get better codegen when enabling subreg liveness. Without it,
any use of a zpr2 tuple is always considered as using both zpr registers
of the pair.



To unsubscribe from these emails, change your notification settings at https://github.com/llvm/llvm-project/settings/notifications