[all-commits] [llvm/llvm-project] 7250b6: [VPlan] Create AVL as a phi from TC -> 0 with EVL ...

[Luke Lau via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 7250b66240f18ba16c7a511602dd559d224b37c0
      https://github.com/llvm/llvm-project/commit/7250b66240f18ba16c7a511602dd559d224b37c0
  Author: Luke Lau <luke at igalia.com>
  Date:   2025-08-01 (Fri, 01 Aug 2025)

  Changed paths:
    M llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp
    M llvm/lib/Transforms/Vectorize/VPlanVerifier.cpp
    M llvm/test/Transforms/LoopVectorize/RISCV/evl-compatible-loops.ll
    M llvm/test/Transforms/LoopVectorize/RISCV/inloop-reduction.ll
    M llvm/test/Transforms/LoopVectorize/RISCV/interleaved-masked-access.ll
    M llvm/test/Transforms/LoopVectorize/RISCV/pr88802.ll
    M llvm/test/Transforms/LoopVectorize/RISCV/scalable-tailfold.ll
    M llvm/test/Transforms/LoopVectorize/RISCV/tail-folding-bin-unary-ops-args.ll
    M llvm/test/Transforms/LoopVectorize/RISCV/tail-folding-call-intrinsics.ll
    M llvm/test/Transforms/LoopVectorize/RISCV/tail-folding-cast-intrinsics.ll
    M llvm/test/Transforms/LoopVectorize/RISCV/tail-folding-cond-reduction.ll
    M llvm/test/Transforms/LoopVectorize/RISCV/tail-folding-div.ll
    M llvm/test/Transforms/LoopVectorize/RISCV/tail-folding-fixed-order-recurrence.ll
    M llvm/test/Transforms/LoopVectorize/RISCV/tail-folding-gather-scatter.ll
    M llvm/test/Transforms/LoopVectorize/RISCV/tail-folding-inloop-reduction.ll
    M llvm/test/Transforms/LoopVectorize/RISCV/tail-folding-interleave.ll
    M llvm/test/Transforms/LoopVectorize/RISCV/tail-folding-intermediate-store.ll
    M llvm/test/Transforms/LoopVectorize/RISCV/tail-folding-iv32.ll
    M llvm/test/Transforms/LoopVectorize/RISCV/tail-folding-known-no-overflow.ll
    M llvm/test/Transforms/LoopVectorize/RISCV/tail-folding-masked-loadstore.ll
    M llvm/test/Transforms/LoopVectorize/RISCV/tail-folding-ordered-reduction.ll
    M llvm/test/Transforms/LoopVectorize/RISCV/tail-folding-reduction.ll
    M llvm/test/Transforms/LoopVectorize/RISCV/tail-folding-reverse-load-store.ll
    M llvm/test/Transforms/LoopVectorize/RISCV/tail-folding-safe-dep-distance.ll
    M llvm/test/Transforms/LoopVectorize/RISCV/tail-folding-uniform-store.ll
    M llvm/test/Transforms/LoopVectorize/RISCV/truncate-to-minimal-bitwidth-cost.ll
    M llvm/test/Transforms/LoopVectorize/RISCV/truncate-to-minimal-bitwidth-evl-crash.ll
    M llvm/test/Transforms/LoopVectorize/RISCV/type-info-cache-evl-crash.ll
    M llvm/test/Transforms/LoopVectorize/RISCV/uniform-load-store.ll
    M llvm/test/Transforms/LoopVectorize/RISCV/vectorize-vp-intrinsics.ll
    M llvm/test/Transforms/LoopVectorize/RISCV/vplan-vp-call-intrinsics.ll
    M llvm/test/Transforms/LoopVectorize/RISCV/vplan-vp-cast-intrinsics.ll
    M llvm/test/Transforms/LoopVectorize/RISCV/vplan-vp-intrinsics-fixed-order-recurrence.ll
    M llvm/test/Transforms/LoopVectorize/RISCV/vplan-vp-intrinsics-reduction.ll
    M llvm/test/Transforms/LoopVectorize/RISCV/vplan-vp-intrinsics.ll

  Log Message:
  -----------
  [VPlan] Create AVL as a phi from TC -> 0 with EVL tail folding (#151481)

This implements the first half of #151459, by changing the AVL so it's
no longer computed as `trip-count - EVL-based IV`, but instead a
separate scalar phi that is decremented by EVL each iteration.

This shortens the dependency chain for computing the AVL and should
eventually allow us to convert the branch condition to `branch-count
avl-next, 0`.

`simplifyBranchConditionForVFAndUF` had to be updated to prevent a
regression because this introduces a VPPhi in the header block.



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