[all-commits] [llvm/llvm-project] 49b001: [mlir][llvm] adds an attribute for the module leve...

[gitoleg via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 49b001474229cd935bf71340bb327f03721d9d00
      https://github.com/llvm/llvm-project/commit/49b001474229cd935bf71340bb327f03721d9d00
  Author: gitoleg <forown at yandex.ru>
  Date:   2025-07-31 (Thu, 31 Jul 2025)

  Changed paths:
    M mlir/include/mlir/Dialect/LLVMIR/LLVMDialect.td
    M mlir/include/mlir/Target/LLVMIR/ModuleImport.h
    M mlir/lib/Target/LLVMIR/ModuleImport.cpp
    M mlir/lib/Target/LLVMIR/ModuleTranslation.cpp
    A mlir/test/Target/LLVMIR/Import/module-asm.ll
    M mlir/test/Target/LLVMIR/invalid-module.mlir
    A mlir/test/Target/LLVMIR/module-asm.mlir

  Log Message:
  -----------
  [mlir][llvm] adds an attribute for the module level assembly (#151318)

Adds support for the module level assembly in the LLVM IR dialect.

---------

Co-authored-by: Tobias Gysi <tobias.gysi at nextsilicon.com>



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