[all-commits] [llvm/llvm-project] 180281: [AMDGPU] Fix op_sel settings for v_cvt_scale32_* a...

[Changpeng Fang via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 180281b8eccfa8e1ec4ebc58df7685497f9ccb26
      https://github.com/llvm/llvm-project/commit/180281b8eccfa8e1ec4ebc58df7685497f9ccb26
  Author: Changpeng Fang <changpeng.fang at amd.com>
  Date:   2025-07-30 (Wed, 30 Jul 2025)

  Changed paths:
    M llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
    M llvm/lib/Target/AMDGPU/VOP3Instructions.td
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.scalef32.pk.gfx950.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.scalef32.sr.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.scalef32.sr.pk.gfx950.ll

  Log Message:
  -----------
  [AMDGPU] Fix op_sel settings for v_cvt_scale32_* and v_cvt_sr_* (#151286)

For OPF_OPSEL_SRCBYTE: Vector instruction uses OPSEL[1:0] to specify a
byte
select for the first source operand. So op_sel [0, 0], [1, 0], [0, 1]
and [1, 1] should map
to byte 0, 1, 2 and 3, respectively.

For OPF_OPSEL_DSTBYTE: OPSEL is used as a destination byte select.
OPSEL[2:3]
specify which byte of the destination to write to. Note that the order
of the bits is different
from that of OPF_OPSEL_SRCBYT. So the mapping should be: op_sel [0, 0],
[0, 1], [1, 0]
and [1, 1] map to byte 0, 1, 2 and 3, respectively.

Fixes: SWDEV-544901



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