[all-commits] [llvm/llvm-project] 3c3523: Revert "[compiler-rt] Remove %T from tests (#151265)"
Vitaly Buka via All-commits
all-commits at lists.llvm.org
Wed Jul 30 07:06:34 PDT 2025
Branch: refs/heads/users/vitalybuka/spr/ltonfc-switch-lto-api-from-output-parameter-to-return-value
Home: https://github.com/llvm/llvm-project
Commit: 3c3523c15850f3c42de35ae725288368414e4e91
https://github.com/llvm/llvm-project/commit/3c3523c15850f3c42de35ae725288368414e4e91
Author: Aiden Grossman <aidengrossman at google.com>
Date: 2025-07-30 (Wed, 30 Jul 2025)
Changed paths:
M compiler-rt/test/asan/TestCases/Linux/long-object-path.cpp
M compiler-rt/test/fuzzer/afl-driver-stderr.test
M compiler-rt/test/sanitizer_common/TestCases/suffix-log-path_test.c
M compiler-rt/test/xray/TestCases/Posix/fdr-mode-inmemory.cpp
M compiler-rt/test/xray/TestCases/Posix/fdr-mode-multiple.cpp
Log Message:
-----------
Revert "[compiler-rt] Remove %T from tests (#151265)"
This reverts commit 05bfcd8ae3f1764145b0d7f491f059bcf8537da3.
This broke some buildbots.
https://lab.llvm.org/buildbot/#/builders/66/builds/17200
https://lab.llvm.org/buildbot/#/builders/72/builds/13632
https://lab.llvm.org/buildbot/#/builders/199/builds/4902
Commit: f2a476d79a8b00f57cdda247580ef72c49fd21a0
https://github.com/llvm/llvm-project/commit/f2a476d79a8b00f57cdda247580ef72c49fd21a0
Author: Muhammad Bassiouni <60100307+bassiounix at users.noreply.github.com>
Date: 2025-07-30 (Wed, 30 Jul 2025)
Changed paths:
M libc/shared/math.h
A libc/shared/math/atanf.h
M libc/src/__support/math/CMakeLists.txt
A libc/src/__support/math/atanf.h
M libc/src/math/generic/CMakeLists.txt
M libc/src/math/generic/atanf.cpp
M libc/test/shared/CMakeLists.txt
M libc/test/shared/shared_math_test.cpp
M utils/bazel/llvm-project-overlay/libc/BUILD.bazel
Log Message:
-----------
[libc][math] Refactor atanf implementation to header-only in src/__support/math folder. (#150854)
Part of #147386
in preparation for: https://discourse.llvm.org/t/rfc-make-clang-builtin-math-functions-constexpr-with-llvm-libc-to-support-c-23-constexpr-math-functions/86450
Commit: e9259a47a8f80465e3da66d1b48e1693fb208ed7
https://github.com/llvm/llvm-project/commit/e9259a47a8f80465e3da66d1b48e1693fb208ed7
Author: Yuxuan Chen <ych at fb.com>
Date: 2025-07-29 (Tue, 29 Jul 2025)
Changed paths:
M clang/lib/CodeGen/CGCoroutine.cpp
M clang/test/CodeGenCoroutines/coro-await.cpp
Log Message:
-----------
[Clang] fix coroutine await suspend wrapper linkage types (#151224)
Commit: 1f66724725c18f7e117e29b113472a9b61f64217
https://github.com/llvm/llvm-project/commit/1f66724725c18f7e117e29b113472a9b61f64217
Author: David Green <david.green at arm.com>
Date: 2025-07-30 (Wed, 30 Jul 2025)
Changed paths:
M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
Log Message:
-----------
[AArch64] Create a performRNDRCombine to pull code out of PerformDAGCombine. NFC
Commit: a7e029bd0bee6304c3654dd41aee04984d2b6edc
https://github.com/llvm/llvm-project/commit/a7e029bd0bee6304c3654dd41aee04984d2b6edc
Author: ronlieb <ron.lieberman at amd.com>
Date: 2025-07-29 (Tue, 29 Jul 2025)
Changed paths:
M clang/lib/Basic/Targets/WebAssembly.cpp
M clang/lib/Basic/Targets/WebAssembly.h
M clang/test/Driver/wasm-features.c
M clang/test/Preprocessor/wasm-target-features.c
M llvm/lib/Target/WebAssembly/WebAssembly.td
M llvm/lib/Target/WebAssembly/WebAssemblyInstrInfo.td
M llvm/lib/Target/WebAssembly/WebAssemblySubtarget.h
M llvm/test/CodeGen/WebAssembly/target-features-cpus.ll
Log Message:
-----------
Revert "[WebAssembly] Add gc target feature to addBleedingEdgeFeatures" (#151268)
Reverts llvm/llvm-project#151107
Commit: 7f470586e10543aa12efc7e04d4d4ac814eaca35
https://github.com/llvm/llvm-project/commit/7f470586e10543aa12efc7e04d4d4ac814eaca35
Author: Keno Fischer <keno at juliahub.com>
Date: 2025-07-30 (Wed, 30 Jul 2025)
Changed paths:
M clang/lib/Driver/ToolChains/MinGW.cpp
M clang/test/Driver/mingw-msvcrt.c
Log Message:
-----------
[Driver][MinGW] Always put libc argument last, even if non-standard (#149434)
I was attempting to build openblas with clang in msys2's `ucrt64`
environment (I'm aware of the `clang64` environment, but I wanted
libstdc++). The openblas link failed with the following:
```
clang -march=native -mtune=native -m64 -O2 -fno-asynchronous-unwind-tables -O2 -DSMALL_MATRIX_OPT -DMS_ABI -DMAX_STACK_ALLOC=2048 -Wall -m64 -DF_INTERFACE_GFORT -DDYNAMIC_ARCH -DSMP_SERVER -DNO_WARMUP -DMAX_CPU_NUMBER=512 -DMAX_PARALLEL_NUMBER=1 -DBUILD_SINGLE=1 -DBUILD_DOUBLE=1 -DBUILD_COMPLEX=1 -DBUILD_COMPLEX16=1 -DVERSION=\"0.3.29\" -UASMNAME -UASMFNAME -UNAME -UCNAME -UCHAR_NAME -UCHAR_CNAME -DASMNAME= -DASMFNAME=_ -DNAME=_ -DCNAME= -DCHAR_NAME=\"_\" -DCHAR_CNAME=\"\" -DNO_AFFINITY -I.. libopenblas64_.def dllinit.obj \
-shared -o ../libopenblas64_.dll -Wl,--out-implib,../libopenblas64_.dll.a \
-Wl,--whole-archive ../libopenblas64_p-r0.3.29.a -Wl,--no-whole-archive -LC:/msys64/ucrt64/bin/../lib/gcc/x86_64-w64-mingw32/15.1.0 -LC:/msys64/ucrt64/bin/../lib/gcc -LC:/msys64/ucrt64/bin/../lib/gcc/x86_64-w64-mingw32/15.1.0/../../../../x86_64-w64-mingw32/lib/../lib -LC:/msys64/ucrt64/bin/../lib/gcc/x86_64-w64-mingw32/15.1.0/../../../../lib -LC:/msys64/ucrt64/bin/../lib/gcc/x86_64-w64-mingw32/15.1.0/../../../../x86_64-w64-mingw32/lib -LC:/msys64/ucrt64/bin/../lib/gcc/x86_64-w64-mingw32/15.1.0/../../.. -lgfortran -lmingwex -lmsvcrt -lquadmath -lm -lpthread -lmingwex -lmsvcrt -defaultlib:advapi32 -lgfortran -defaultlib:advapi32 -lgfortran
C:/msys64/ucrt64/bin/ld: C:/msys64/ucrt64/bin/../lib/gcc/x86_64-w64-mingw32/15.1.0/../../../../lib/libmingw32.a(lib64_libmingw32_a-pseudo-reloc.o): in function `__report_error':
D:/W/B/src/mingw-w64/mingw-w64-crt/crt/pseudo-reloc.c:157:(.text+0x59): undefined reference to `abort'
C:/msys64/ucrt64/bin/ld: C:/msys64/ucrt64/bin/../lib/gcc/x86_64-w64-mingw32/15.1.0/../../../../lib/libmingw32.a(lib64_libmingw32_a-tlsthrd.o): in function `___w64_mingwthr_add_key_dtor':
D:/W/B/src/mingw-w64/mingw-w64-crt/crt/tlsthrd.c:48:(.text+0xa5): undefined reference to `calloc'
C:/msys64/ucrt64/bin/ld: C:/msys64/ucrt64/bin/../lib/gcc/x86_64-w64-mingw32/15.1.0/../../../../lib/libmingw32.a(lib64_libmingw32_a-pesect.o): in function `_FindPESectionByName':
D:/W/B/src/mingw-w64/mingw-w64-crt/crt/pesect.c:79:(.text+0xfd): undefined reference to `strncmp'
```
These symbols come from the `-lmingw32` dep that the driver added and
are ordinarily found in `-lmsvcrt`, which got skipped here, because
openblas passed `-lmsvcrt` explicitly earlier in the link line. Since we
always add these libraries at the end here, I think that clang is "at
fault" (as opposed to a user or packaging mistake) and should have added
some crt here.
To preserve the intent of letting the user override which crt is chosen,
duplicate the (first) user chosen crt `-l` into this position, although
we should perhaps consider an explicit `-mcrtdll` like gcc has as well.
Commit: 74763608ef0da6bdcf6032f0457d1e7a156bad6a
https://github.com/llvm/llvm-project/commit/74763608ef0da6bdcf6032f0457d1e7a156bad6a
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2025-07-30 (Wed, 30 Jul 2025)
Changed paths:
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.mfma.xf32.gfx942.ll
Log Message:
-----------
AMDGPU: Test VGPR and AGPR case for xf32 mfmas (#150891)
Commit: 4ee6943eeb1de19e182b56fde34d134d43aceb67
https://github.com/llvm/llvm-project/commit/4ee6943eeb1de19e182b56fde34d134d43aceb67
Author: Madhur Amilkanthwar <madhura at nvidia.com>
Date: 2025-07-30 (Wed, 30 Jul 2025)
Changed paths:
M llvm/test/Transforms/GVN/PRE/load-metadata.ll
M llvm/test/Transforms/GVN/PRE/load-pre-across-backedge.ll
M llvm/test/Transforms/GVN/PRE/load-pre-nonlocal.ll
M llvm/test/Transforms/GVN/PRE/lpre-call-wrap.ll
M llvm/test/Transforms/GVN/PRE/rle-addrspace-cast.ll
M llvm/test/Transforms/GVN/PRE/rle-semidominated.ll
Log Message:
-----------
[GVN][Tests] Add MSSA coverage to some PRE tests 3/N (#150603)
Previous patch in this series
https://github.com/llvm/llvm-project/pull/137814
Commit: f527b319e377202e44b14b6875584a558a628803
https://github.com/llvm/llvm-project/commit/f527b319e377202e44b14b6875584a558a628803
Author: Abhinav Garg <39309352+abhigargrepo at users.noreply.github.com>
Date: 2025-07-30 (Wed, 30 Jul 2025)
Changed paths:
M llvm/lib/Analysis/UniformityAnalysis.cpp
Log Message:
-----------
[Uniformity Analysis] Fix print method to dump uniformity info (#151130)
Commit: 2a5ac19605ae49d6628ac3af55d6b528cb13ed2e
https://github.com/llvm/llvm-project/commit/2a5ac19605ae49d6628ac3af55d6b528cb13ed2e
Author: Luke Lau <luke at igalia.com>
Date: 2025-07-30 (Wed, 30 Jul 2025)
Changed paths:
M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
M llvm/lib/Target/RISCV/RISCVISelLowering.h
M llvm/lib/Target/RISCV/RISCVInterleavedAccess.cpp
M llvm/lib/Target/RISCV/RISCVTargetTransformInfo.h
M llvm/test/Analysis/CostModel/RISCV/masked_ldst.ll
Log Message:
-----------
Revert "[RISCV] Cost bf16/f16 vector non-unit memory accesses as legal without zvfhmin/zvfbfmin (#150882)"
This reverts commit fe4f6c1a58ab4f00a88a97af01000b6783b573ee, but leaves
the tests that were added.
The original commit mistakenly assumed that if regular bf16/f16 loads
and stores could be lowered without zvfbfmin/zvfhmin, then so too could
masked loads/stores and gathers/scatters.
However SelectionDAG can't actually type-legalize masked.load/stores
since it needs to be done in ScalarizeMaskedMemIntrinPass.
This was causing crashes on IREE because we now returned true for
isLegalMaskedLoadStore.
The original intent of this was to remove a discrepancy in the loop
vectorizer tests whenever predication was enabled, but this has gone
away after 92d09245d61dce80d3e68a27cc34d5fc6f062c93. So I don't think we
need to reapply this patch.
Commit: eddd34227ec2770c81d260826e2c31f4d5136f8f
https://github.com/llvm/llvm-project/commit/eddd34227ec2770c81d260826e2c31f4d5136f8f
Author: Craig Topper <craig.topper at sifive.com>
Date: 2025-07-29 (Tue, 29 Jul 2025)
Changed paths:
M llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
Log Message:
-----------
[TargetLowering] Use getShiftAmountConstant in CTTZTableLookup. NFC
Commit: 8f187c74b3ad77ef8a15bc3d2d718ccd88edb873
https://github.com/llvm/llvm-project/commit/8f187c74b3ad77ef8a15bc3d2d718ccd88edb873
Author: Sameer Sahasrabuddhe <sameer.sahasrabuddhe at amd.com>
Date: 2025-07-30 (Wed, 30 Jul 2025)
Changed paths:
M llvm/lib/Target/AMDGPU/SIInsertWaitcnts.cpp
M llvm/lib/Target/AMDGPU/SIMemoryLegalizer.cpp
M llvm/lib/Target/AMDGPU/SOPInstructions.td
M llvm/test/CodeGen/AMDGPU/GlobalISel/memory-legalizer-atomic-fence.ll
A llvm/test/CodeGen/AMDGPU/insert-waitcnts-fence-soft.mir
A llvm/test/CodeGen/AMDGPU/lds-dma-workgroup-release.ll
Log Message:
-----------
[AMDGPU] introduce S_WAITCNT_LDS_DIRECT in the memory legalizer (#150887)
The new instruction represents the unknown number of waitcnts needed at a
release operation to ensure that prior direct loads to LDS (formerly called LDS
DMA) are completed. The instruction is replaced in SIInsertWaitcnts with a
suitable value for vmcnt().
Co-authored-by: Austin Kerbow <austin.kerbow at amd.com>.
Commit: a9d491b17f4f0a131f68a5dbdac8d34c7c8427db
https://github.com/llvm/llvm-project/commit/a9d491b17f4f0a131f68a5dbdac8d34c7c8427db
Author: Younan Zhang <zyn7109 at gmail.com>
Date: 2025-07-30 (Wed, 30 Jul 2025)
Changed paths:
M clang/lib/Sema/SemaConcept.cpp
M clang/lib/Sema/SemaTemplate.cpp
M clang/test/SemaTemplate/concepts.cpp
Log Message:
-----------
[Clang] Don't allow implicit this access when checking function constraints (#151276)
We allowed implicit this access when checking associated constraints
after CWG2369. As a result, some of the invalid function call
expressions were not properly SFINAE'ed out and ended up as hard errors
at evaluation time.
We tried fixing that by mucking around the CurContext, but that spawned
additional breakages and I think it's probably safe to revert to the
previous behavior to avoid churns.
Though there is CWG2589, which justifies the previous change, it's not
what we're pursuing now.
Fixes https://github.com/llvm/llvm-project/issues/151271
Fixes https://github.com/llvm/llvm-project/issues/145505
Commit: 957ae8ad46d401b4e263bf786b1eafde06894125
https://github.com/llvm/llvm-project/commit/957ae8ad46d401b4e263bf786b1eafde06894125
Author: Fabian Ritter <fabian.ritter at amd.com>
Date: 2025-07-30 (Wed, 30 Jul 2025)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
M llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeHelper.cpp
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-call-abi-attribute-hints.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-call-implicit-args.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-call-return-values.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-call-sret.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-call.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-indirect-call.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-addrspacecast.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-load.mir
Log Message:
-----------
[AMDGPU][GISel] Use buildObjectPtrOffset instead of buildPtrAdd (#150899)
This concerns offset computations for kernargs and
RegBankLegalizeHelper::splitLoad, which should all be within the bounds of a
memory object. See #150392 for the motivation for introducing the
buildObjectPtrOffset function.
For SWDEV-516125.
Commit: d3b2bda19c8074d0f2e867ee82a90b52734f5bc4
https://github.com/llvm/llvm-project/commit/d3b2bda19c8074d0f2e867ee82a90b52734f5bc4
Author: woruyu <99597449+woruyu at users.noreply.github.com>
Date: 2025-07-30 (Wed, 30 Jul 2025)
Changed paths:
M llvm/test/CodeGen/ARM/fcopysign.ll
M llvm/utils/UpdateTestChecks/asm.py
Log Message:
-----------
[utils][UpdateTestChecks] update_llc_test_checks.py - armv7-apple-darwin triple no longer working (#150906)
### Summary
This PR resolves https://github.com/llvm/llvm-project/issues/150207
Commit: 27f777e9c06daeb03efad9230fe080df2a3a94c5
https://github.com/llvm/llvm-project/commit/27f777e9c06daeb03efad9230fe080df2a3a94c5
Author: Michael Kruse <llvm-project at meinersbur.de>
Date: 2025-07-30 (Wed, 30 Jul 2025)
Changed paths:
M flang/lib/Lower/OpenMP/OpenMP.cpp
M flang/test/Lower/OpenMP/unroll-heuristic01.f90
M flang/test/Lower/OpenMP/unroll-heuristic02.f90
A flang/test/Lower/OpenMP/unroll-heuristic03.f90
Log Message:
-----------
[Flang][OpenMP] Skip DSA for canonical loops (#150593)
OpenMP loop transformations to not have data-sharing attributes and do
not explicitly privatize the loop variable. The DataSharingProcessor was
still used in #144785 because `createAndSetPrivatizedLoopVar` expected
it.
We skip that function and directly write to the loop variable. If the
loop variable is implicitly or explicitly privatized, it will be due to
surrounding OpenMP constructs such as `parallel`.
Commit: a86ad73064e71f0f09803a7ade13a32cf316ca94
https://github.com/llvm/llvm-project/commit/a86ad73064e71f0f09803a7ade13a32cf316ca94
Author: Joachim <jenke at itc.rwth-aachen.de>
Date: 2025-07-30 (Wed, 30 Jul 2025)
Changed paths:
M offload/tools/offload-tblgen/CMakeLists.txt
Log Message:
-----------
[offload] Add missing build dependency (#149326)
libc++ headers must be generated before compiling part of liboffload.
The build error occurs if clang is configured to use libc++ by default.
Fixes issue #149324
Commit: e50bd78d54a228757de369a3951534244c6af36a
https://github.com/llvm/llvm-project/commit/e50bd78d54a228757de369a3951534244c6af36a
Author: Vikram Hegde <Vikram.Hegde at amd.com>
Date: 2025-07-30 (Wed, 30 Jul 2025)
Changed paths:
M llvm/include/llvm/Passes/CodeGenPassBuilder.h
M llvm/include/llvm/Target/CGPassBuilderOption.h
M llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
M llvm/lib/Target/AMDGPU/CMakeLists.txt
M llvm/lib/Target/X86/CMakeLists.txt
M llvm/test/CodeGen/AMDGPU/llc-pipeline-npm.ll
Log Message:
-----------
Reapply "[CodeGen][NPM] Stitch up loop passes in codegen pipeline" (#151098)
Reapplies https://github.com/llvm/llvm-project/pull/148114
includes shared lib build failure fixes for AMDGPU and X86.
Commit: fb49c6784ad425a332bd528567b9c26624fff5b0
https://github.com/llvm/llvm-project/commit/fb49c6784ad425a332bd528567b9c26624fff5b0
Author: Timm Baeder <tbaeder at redhat.com>
Date: 2025-07-30 (Wed, 30 Jul 2025)
Changed paths:
M clang/lib/AST/ByteCode/Disasm.cpp
M clang/lib/AST/ByteCode/DynamicAllocator.cpp
M clang/lib/AST/ByteCode/InterpBlock.cpp
M clang/lib/AST/ByteCode/InterpState.cpp
M clang/lib/AST/ByteCode/Pointer.cpp
M clang/lib/AST/ByteCode/Pointer.h
Log Message:
-----------
[clang][bytecode] Move Pointer::{Prev,Next} into BlockPointer (#151097)
They are only relevant for block pointers.
Commit: c4b155709714fb3381049b6d523c1f518dc363f5
https://github.com/llvm/llvm-project/commit/c4b155709714fb3381049b6d523c1f518dc363f5
Author: Pierre van Houtryve <pierre.vanhoutryve at amd.com>
Date: 2025-07-30 (Wed, 30 Jul 2025)
Changed paths:
M llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
A llvm/test/CodeGen/AMDGPU/merged-bfx-opt.ll
M llvm/test/CodeGen/AMDGPU/workitem-intrinsic-opts.ll
Log Message:
-----------
[DAG] Fold (setcc ((x | x >> c0 | ...) & mask)) sequences (#146054)
Fold sequences where we extract a bunch of contiguous bits from a value,
merge them into the low bit and then check if the low bits are zero or
not.
Usually the and would be on the outside (the leaves) of the expression,
but the DAG canonicalizes it to a single `and` at the root of the
expression.
The reason I put this in DAGCombiner instead of the target combiner is
because this is a generic, valid transform that's also fairly niche, so
there isn't much risk of a combine loop I think.
See #136727
Commit: 7a0024d694b9137eb8e105c0c3b20dea03fed34f
https://github.com/llvm/llvm-project/commit/7a0024d694b9137eb8e105c0c3b20dea03fed34f
Author: Ricardo Jesus <rjj at nvidia.com>
Date: 2025-07-30 (Wed, 30 Jul 2025)
Changed paths:
M llvm/lib/Target/AArch64/AArch64MIPeepholeOpt.cpp
Log Message:
-----------
[AArch64] Refactor AND/ANDS bitmask splitting (NFC). (#150619)
This patch generalises the logic for splitting bitmasks for AND/ANDS
immediate instructions, to prepare it to handle more opcodes, as in
#150394.
Commit: 058d96f2d68d3496ae52774c06177d4a9039a134
https://github.com/llvm/llvm-project/commit/058d96f2d68d3496ae52774c06177d4a9039a134
Author: Pengcheng Wang <wangpengcheng.pp at bytedance.com>
Date: 2025-07-30 (Wed, 30 Jul 2025)
Changed paths:
M llvm/docs/LangRef.rst
M llvm/lib/Target/RISCV/RISCVCallingConv.td
M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
M llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp
A llvm/test/CodeGen/RISCV/calling-conv-preserve-most.ll
Log Message:
-----------
[RISCV] Support PreserveMost calling convention (#148214)
This adds the simplest implementation of `PreserveMost` calling
convention and we preserve `x5-x31` (except x6/x7/x28) registers.
Fixes #148147.
Commit: 743177c1ef1e0e43584854191f8a11b22b85e951
https://github.com/llvm/llvm-project/commit/743177c1ef1e0e43584854191f8a11b22b85e951
Author: Phoebe Wang <phoebe.wang at intel.com>
Date: 2025-07-30 (Wed, 30 Jul 2025)
Changed paths:
M llvm/lib/Target/X86/X86ISelLowering.cpp
M llvm/test/CodeGen/X86/apx/cf.ll
Log Message:
-----------
[X86][APX] Use TEST instruction for CLOAD/CSTORE (#151160)
Commit: 4ec8503e4c480f52426ddd03619b017f19a2f452
https://github.com/llvm/llvm-project/commit/4ec8503e4c480f52426ddd03619b017f19a2f452
Author: Zhaoxin Yang <yangzhaoxin at loongson.cn>
Date: 2025-07-30 (Wed, 30 Jul 2025)
Changed paths:
M lld/ELF/Arch/LoongArch.cpp
M lld/test/ELF/loongarch-relax-pc-hi20-lo12.s
Log Message:
-----------
[lld][LoongArch] Check that the relocation addend is zero before applying relaxation to R_LARCH_GOT_PC_{HI20,LO12} (#151264)
Linker relaxation to R_LARCH_GOT_PC_{HI20,LO12} is only possible when
the addend of the relocation is zero.
Note: For `ld.bfd`, GOT references with non-zero addends will trigger an
assert in LoongArch, but `lld` handles these cases without any errors.
```
ld.bfd: BFD (GNU Binutils) 2.44.0 assertion fail
/usr/src/debug/binutils/binutils-gdb/bfd/elfnn-loongarch.c:4248
```
Commit: 33e978fbfa25fa98bd521222298e903c3f324a60
https://github.com/llvm/llvm-project/commit/33e978fbfa25fa98bd521222298e903c3f324a60
Author: Christian Kandeler <christian.kandeler at qt.io>
Date: 2025-07-30 (Wed, 30 Jul 2025)
Changed paths:
M clang-tools-extra/clangd/FindSymbols.cpp
M clang-tools-extra/clangd/unittests/FindSymbolsTests.cpp
Log Message:
-----------
[clangd] Make inline friend functions appear in document symbols (#150629)
Otherwise, that definition would not show up in the document outline.
Commit: cc8c941e17558ba427de06e72c8ad96d7b17ced1
https://github.com/llvm/llvm-project/commit/cc8c941e17558ba427de06e72c8ad96d7b17ced1
Author: Shih-Po Hung <shihpo.hung at sifive.com>
Date: 2025-07-30 (Wed, 30 Jul 2025)
Changed paths:
M llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
M llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp
M llvm/lib/Transforms/Vectorize/VPlanTransforms.h
M llvm/lib/Transforms/Vectorize/VPlanVerifier.cpp
M llvm/test/Transforms/LoopVectorize/RISCV/evl-compatible-loops.ll
M llvm/test/Transforms/LoopVectorize/RISCV/inloop-reduction.ll
M llvm/test/Transforms/LoopVectorize/RISCV/interleaved-masked-access.ll
M llvm/test/Transforms/LoopVectorize/RISCV/pr88802.ll
M llvm/test/Transforms/LoopVectorize/RISCV/scalable-tailfold.ll
M llvm/test/Transforms/LoopVectorize/RISCV/tail-folding-bin-unary-ops-args.ll
M llvm/test/Transforms/LoopVectorize/RISCV/tail-folding-call-intrinsics.ll
M llvm/test/Transforms/LoopVectorize/RISCV/tail-folding-cast-intrinsics.ll
M llvm/test/Transforms/LoopVectorize/RISCV/tail-folding-cond-reduction.ll
M llvm/test/Transforms/LoopVectorize/RISCV/tail-folding-div.ll
M llvm/test/Transforms/LoopVectorize/RISCV/tail-folding-fixed-order-recurrence.ll
M llvm/test/Transforms/LoopVectorize/RISCV/tail-folding-gather-scatter.ll
M llvm/test/Transforms/LoopVectorize/RISCV/tail-folding-inloop-reduction.ll
M llvm/test/Transforms/LoopVectorize/RISCV/tail-folding-interleave.ll
M llvm/test/Transforms/LoopVectorize/RISCV/tail-folding-intermediate-store.ll
M llvm/test/Transforms/LoopVectorize/RISCV/tail-folding-iv32.ll
M llvm/test/Transforms/LoopVectorize/RISCV/tail-folding-known-no-overflow.ll
M llvm/test/Transforms/LoopVectorize/RISCV/tail-folding-masked-loadstore.ll
M llvm/test/Transforms/LoopVectorize/RISCV/tail-folding-ordered-reduction.ll
M llvm/test/Transforms/LoopVectorize/RISCV/tail-folding-reduction.ll
M llvm/test/Transforms/LoopVectorize/RISCV/tail-folding-reverse-load-store.ll
M llvm/test/Transforms/LoopVectorize/RISCV/tail-folding-safe-dep-distance.ll
M llvm/test/Transforms/LoopVectorize/RISCV/tail-folding-uniform-store.ll
M llvm/test/Transforms/LoopVectorize/RISCV/truncate-to-minimal-bitwidth-cost.ll
M llvm/test/Transforms/LoopVectorize/RISCV/truncate-to-minimal-bitwidth-evl-crash.ll
M llvm/test/Transforms/LoopVectorize/RISCV/type-info-cache-evl-crash.ll
M llvm/test/Transforms/LoopVectorize/RISCV/uniform-load-store.ll
A llvm/test/Transforms/LoopVectorize/RISCV/vector-loop-backedge-elimination-with-evl.ll
M llvm/test/Transforms/LoopVectorize/RISCV/vectorize-vp-intrinsics.ll
Log Message:
-----------
[VPlan] Convert EVL loops to variable-length stepping after dissolution (#147222)
Loop regions require fixed-length steps and rounded-up trip counts, but
after dissolution creates explicit control flow, EVL loops can leverage
variable-length stepping with original trip counts.
This patch adds a post-dissolution transform pass to convert EVL loops
from fixed-length to variable-length stepping .
Commit: c6f7fa74376634619eb4e8ea9e9580fd3e220fe7
https://github.com/llvm/llvm-project/commit/c6f7fa74376634619eb4e8ea9e9580fd3e220fe7
Author: Florian Hahn <flo at fhahn.com>
Date: 2025-07-30 (Wed, 30 Jul 2025)
Changed paths:
A llvm/test/Analysis/ScalarEvolution/zext-add.ll
Log Message:
-----------
[SCEV] Add test for pushing constant add into zext.
Adds a SCEV-only tests for
https://github.com/llvm/llvm-project/pull/151227.
Commit: ded255e56ee1f2ef27e85b013f572fca34ca57bc
https://github.com/llvm/llvm-project/commit/ded255e56ee1f2ef27e85b013f572fca34ca57bc
Author: Pavel Labath <pavel at labath.sk>
Date: 2025-07-30 (Wed, 30 Jul 2025)
Changed paths:
M llvm/include/llvm/BinaryFormat/SFrame.h
M llvm/include/llvm/BinaryFormat/SFrameConstants.def
M llvm/include/llvm/Object/SFrameParser.h
M llvm/lib/BinaryFormat/SFrame.cpp
M llvm/lib/Object/SFrameParser.cpp
A llvm/test/tools/llvm-readobj/ELF/sframe-fde.test
M llvm/test/tools/llvm-readobj/ELF/sframe-header.test
M llvm/tools/llvm-readobj/ELFDumper.cpp
Log Message:
-----------
[Object] Parsing and dumping of SFrame FDEs (#149828)
Also known as Function Description Entries. The entries occupy a
contiguous piece of the section, so the code is mostly straight-forward.
For more information about the SFrame unwind format, see the
[specification](https://sourceware.org/binutils/wiki/sframe) and the
related [RFC](https://discourse.llvm.org/t/rfc-adding-sframe-support-to-llvm/86900).
Commit: c5327b935b15548792cfce48a79e5f639b20b9d2
https://github.com/llvm/llvm-project/commit/c5327b935b15548792cfce48a79e5f639b20b9d2
Author: Lewis Crawford <lcrawford at nvidia.com>
Date: 2025-07-30 (Wed, 30 Jul 2025)
Changed paths:
M llvm/include/llvm/IR/NVVMIntrinsicUtils.h
M llvm/lib/Analysis/ConstantFolding.cpp
Log Message:
-----------
[ConstantFolding] Fix typo in GetNVVMDenormMode (#151297)
Fix typo in function name of GetNVVMDenormMode
(Denrom vs Denorm).
Commit: 2ec91a5ec41c93e79a16ddca02de14b07d593c2c
https://github.com/llvm/llvm-project/commit/2ec91a5ec41c93e79a16ddca02de14b07d593c2c
Author: David Green <david.green at arm.com>
Date: 2025-07-30 (Wed, 30 Jul 2025)
Changed paths:
M llvm/test/CodeGen/AArch64/aarch64-isel-csinc-type.ll
M llvm/test/CodeGen/AArch64/add-extract.ll
M llvm/test/CodeGen/AArch64/addsub.ll
M llvm/test/CodeGen/AArch64/arm64-vmul.ll
M llvm/test/CodeGen/AArch64/logical_shifted_reg.ll
M llvm/test/CodeGen/AArch64/neg-abs.ll
M llvm/test/CodeGen/AArch64/neg-selects.ll
M llvm/test/CodeGen/AArch64/neon-dot-product.ll
M llvm/test/CodeGen/AArch64/reassocmls.ll
Log Message:
-----------
[AArch64][GlobalISel] Add extra GISel test coverage. NFC
This is essentially from performAddSubCombine. addsub.ll has been cleaned up a
little in the process.
Commit: 62744f368166f223740e5f6105aeb11ea854728d
https://github.com/llvm/llvm-project/commit/62744f368166f223740e5f6105aeb11ea854728d
Author: Amina Chabane <amina.chabane at arm.com>
Date: 2025-07-30 (Wed, 30 Jul 2025)
Changed paths:
M clang/test/CodeGen/AArch64/neon-scalar-copy.c
M clang/test/CodeGen/AArch64/neon-vget.c
M clang/test/CodeGen/AArch64/poly64.c
M clang/utils/TableGen/NeonEmitter.cpp
Log Message:
-----------
[AArch64][NEON] NEON intrinsic compilation error with -fno-lax-vector-conversion flag fix (#149329)
Issue originally raised in
https://github.com/llvm/llvm-project/issues/71362#issuecomment-3028515618.
Certain NEON intrinsics that operate on poly types (e.g. poly8x8_t)
failed to compile with the -fno-lax-vector-conversions flag. This patch
updates NeonEmitter.cpp to insert an explicit __builtin_bit_cast from
poly types to the required signed integer vector types when generating
lane-related intrinsics. A test 'neon-bitcast-poly.ll' is included.
Commit: 497d17737518d417f6411d46aef1334f642ccd81
https://github.com/llvm/llvm-project/commit/497d17737518d417f6411d46aef1334f642ccd81
Author: Dmitry Vasilyev <dvassiliev at accesssoftek.com>
Date: 2025-07-30 (Wed, 30 Jul 2025)
Changed paths:
M bolt/lib/Core/Relocation.cpp
Log Message:
-----------
[BOLT] Allow to compile with MSVC (#151189)
This change is necessary to build BOLT with MSVC on Windows.
Commit: dba558b474199142b8b2c88e9e4110ab1b8cf8e3
https://github.com/llvm/llvm-project/commit/dba558b474199142b8b2c88e9e4110ab1b8cf8e3
Author: Jakub Chlanda <jakub at codeplay.com>
Date: 2025-07-30 (Wed, 30 Jul 2025)
Changed paths:
A clang/include/clang/Driver/CudaInstallationDetector.h
A clang/include/clang/Driver/LazyDetector.h
A clang/include/clang/Driver/RocmInstallationDetector.h
A clang/include/clang/Driver/SyclInstallationDetector.h
M clang/lib/Driver/ToolChains/AMDGPU.h
M clang/lib/Driver/ToolChains/Clang.cpp
M clang/lib/Driver/ToolChains/CommonArgs.cpp
M clang/lib/Driver/ToolChains/Cuda.h
M clang/lib/Driver/ToolChains/Darwin.h
M clang/lib/Driver/ToolChains/Gnu.h
M clang/lib/Driver/ToolChains/HIPAMD.h
R clang/lib/Driver/ToolChains/LazyDetector.h
M clang/lib/Driver/ToolChains/MSVC.h
M clang/lib/Driver/ToolChains/MinGW.h
R clang/lib/Driver/ToolChains/ROCm.h
M clang/lib/Driver/ToolChains/SYCL.h
Log Message:
-----------
[Clang][Driver] Installation detectors in user facing include dir (#151114)
This patch moves `LazyDetector` and target specific (Cuda, Hip, SYCL)
installation detectors to clang's include directory. It was problematic
for downstream to use headers from clang's lib dir. The use of lib
headers could lead to subtle errors, as some of the symbols there are
annotated with `LLVM_LIBRARY_VISIBILITY`. For instance
[`ROCMToolChain::getCommonDeviceLibNames`](https://github.com/jchlanda/llvm-project/blob/jakub/installation_detectors/clang/lib/Driver/ToolChains/AMDGPU.h#L147)
is c++ public, but because of the annotation it ends up as ELF hidden
symbol, which causes errors when accessed from another shared library.
Commit: 4687a7647f86f852e6a4e600aa2ec6dc4b0871ac
https://github.com/llvm/llvm-project/commit/4687a7647f86f852e6a4e600aa2ec6dc4b0871ac
Author: David Green <david.green at arm.com>
Date: 2025-07-30 (Wed, 30 Jul 2025)
Changed paths:
M llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp
M llvm/test/CodeGen/AArch64/neon-dot-product.ll
Log Message:
-----------
[AArch64][GlobalISel] Lower udot/sdot intrinsics to G_UDOT/G_SDOT
This allows them to be selected using the same pathways as normal lowering.
USDOT is not handled yet as we do not yet have a node for it.
Commit: 16d5db71b3c38f21aa17783a8758f947dca5883f
https://github.com/llvm/llvm-project/commit/16d5db71b3c38f21aa17783a8758f947dca5883f
Author: Victor Campos <victor.campos at arm.com>
Date: 2025-07-30 (Wed, 30 Jul 2025)
Changed paths:
M clang/include/clang/Basic/DiagnosticSemaKinds.td
M clang/lib/Sema/SemaTypeTraits.cpp
M clang/test/CXX/drs/cwg18xx.cpp
M clang/test/SemaCXX/overload-resolution-deferred-templates.cpp
M clang/test/SemaCXX/type-traits-unsatisfied-diags-std.cpp
M clang/test/SemaCXX/type-traits-unsatisfied-diags.cpp
M libcxx/test/libcxx/utilities/expected/expected.expected/and_then.mandates.verify.cpp
M libcxx/test/libcxx/utilities/expected/expected.expected/or_else.mandates.verify.cpp
M libcxx/test/libcxx/utilities/expected/expected.expected/value.observers.verify.cpp
M libcxx/test/libcxx/utilities/expected/expected.void/and_then.mandates.verify.cpp
M libcxx/test/std/containers/sequences/array/array.creation/to_array.verify.cpp
M libcxx/test/std/containers/views/mdspan/mdspan/conversion.verify.cpp
M libcxx/test/std/utilities/function.objects/func.bind.partial/bind_back.verify.cpp
M libcxx/test/std/utilities/function.objects/func.bind_front/bind_front.verify.cpp
Log Message:
-----------
Revert "[libc++][Clang] Added explanation why is_constructible evaluated to false. Updated the diagnostics checks in libc++ tests. (#144220)"
This reverts commit e476f968bc8e438a0435d10934f148de570db8eb.
It has introduced a failure tracked by https://github.com/llvm/llvm-project/issues/150601
One libcxx test fail if libcxx is build with no exceptions and no RTTI:
- libcxx/utilities/expected/expected.expected/value.observers.verify.cpp
Commit: ece7a72aa28975e5ed71cecabf15c9b138b1f277
https://github.com/llvm/llvm-project/commit/ece7a72aa28975e5ed71cecabf15c9b138b1f277
Author: ZhaoQi <zhaoqi01 at loongson.cn>
Date: 2025-07-30 (Wed, 30 Jul 2025)
Changed paths:
M llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp
M llvm/test/CodeGen/LoongArch/lasx/ir-instruction/insertelement.ll
M llvm/test/CodeGen/LoongArch/lsx/ir-instruction/insertelement.ll
Log Message:
-----------
[LoongArch] Optimize insertelement containing variable index using compare+select (#151131)
Commit: 984ec022360805c308c105dccb594be218d57243
https://github.com/llvm/llvm-project/commit/984ec022360805c308c105dccb594be218d57243
Author: Nikita Popov <npopov at redhat.com>
Date: 2025-07-30 (Wed, 30 Jul 2025)
Changed paths:
M clang/include/clang/AST/Expr.h
Log Message:
-----------
[Clang] Replace include with forward declaration (NFC) (#151292)
After https://github.com/llvm/llvm-project/pull/142541.
Commit: 13f38c97d597f3b07fb674d9b8c2b1db2bc0724f
https://github.com/llvm/llvm-project/commit/13f38c97d597f3b07fb674d9b8c2b1db2bc0724f
Author: Paul Walker <paul.walker at arm.com>
Date: 2025-07-30 (Wed, 30 Jul 2025)
Changed paths:
M llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
M llvm/test/CodeGen/AArch64/combine-and-like.ll
M llvm/test/CodeGen/AMDGPU/saddsat.ll
M llvm/test/CodeGen/AMDGPU/uaddsat.ll
M llvm/test/CodeGen/AMDGPU/vector-reduce-smax.ll
M llvm/test/CodeGen/AMDGPU/vector-reduce-smin.ll
M llvm/test/CodeGen/AMDGPU/vector-reduce-umax.ll
M llvm/test/CodeGen/AMDGPU/vector-reduce-umin.ll
M llvm/test/CodeGen/X86/combine-add-ssat.ll
M llvm/test/CodeGen/X86/combine-add-usat.ll
M llvm/test/CodeGen/X86/combine-sub-ssat.ll
M llvm/test/CodeGen/X86/combine-sub-usat.ll
M llvm/test/CodeGen/X86/load-combine.ll
M llvm/test/CodeGen/X86/pr33960.ll
M llvm/unittests/CodeGen/CMakeLists.txt
M llvm/unittests/CodeGen/SelectionDAGAddressAnalysisTest.cpp
A llvm/unittests/CodeGen/SelectionDAGNodeConstructionTest.cpp
M llvm/unittests/CodeGen/SelectionDAGPatternMatchTest.cpp
A llvm/unittests/CodeGen/SelectionDAGTestBase.h
Log Message:
-----------
[LLVM][SelectionDAG] Align poison/undef binop folds with IR. (#149334)
The "at construction" binop folds in SelectionDAG::getNode() has
different behaviour when compared to the equivalent LLVM IR. This PR
makes the behaviour consistent while also extending the coverage to
include signed/unsigned max/min operations.
Commit: 10d7352c7a9997f0d39d0ee26a786b08f904b5d6
https://github.com/llvm/llvm-project/commit/10d7352c7a9997f0d39d0ee26a786b08f904b5d6
Author: David Spickett <david.spickett at linaro.org>
Date: 2025-07-30 (Wed, 30 Jul 2025)
Changed paths:
M lldb/source/Plugins/Process/Utility/AuxVector.cpp
M lldb/source/Plugins/Process/Utility/AuxVector.h
Log Message:
-----------
[lldb][FreeBSD] Add Auxv numbers for HWCAP3 and HWCAP4 (#151152)
These entries serve the same purpose as the Linux HWCAPs but have been
assigned different numbers as FreeBSD had already used the Linux ones.
The numbers were assigned in:
https://github.com/freebsd/freebsd-src/commit/85007872d1227006adf2ce119fe30de856cbe12d
In theory we can read these for the purposes of register field
detection, even on earlier versions of FreeBSD. As the aux data is a
key-value structure, we simply won't find the new numbers on older
systems.
However, FreeBSD has not defined any feature bits for HWACP3 and 4. It
is likley that they will match the Linux feature bits, but I have no
proof of that yet.
For instance, FEAT_MTE_STORE_ONLY is indicated by a HWCAP3 feature bit
on Linux. FreeBSD does not support this feature at all yet.
So for now, these values exist for future use and are not used for
register field detection on FreeBSD.
Commit: 4a8ce6b704c32715bc16d6c33b8b0d91d2ab3ed1
https://github.com/llvm/llvm-project/commit/4a8ce6b704c32715bc16d6c33b8b0d91d2ab3ed1
Author: LLVM GN Syncbot <llvmgnsyncbot at gmail.com>
Date: 2025-07-30 (Wed, 30 Jul 2025)
Changed paths:
M llvm/utils/gn/secondary/llvm/unittests/CodeGen/BUILD.gn
Log Message:
-----------
[gn build] Port 13f38c97d597
Commit: 20293ebd3159b3964c4466e6ee04d3e9b721eac0
https://github.com/llvm/llvm-project/commit/20293ebd3159b3964c4466e6ee04d3e9b721eac0
Author: Paul Walker <paul.walker at arm.com>
Date: 2025-07-30 (Wed, 30 Jul 2025)
Changed paths:
M llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp
M llvm/test/CodeGen/AArch64/sme2-intrinsics-ld1.ll
M llvm/test/CodeGen/AArch64/sme2-intrinsics-ldnt1.ll
Log Message:
-----------
[LLVM][CodeGen][SME] Only emit strided loads in streaming mode. (#150445)
The selection code for aarch64_sve_ld[nt]1_pn_x{2,4} intrinsics gates
the use of strided load instructions behind the SME2 target feature.
However, the instructions are only available in streaming mode.
Commit: 8a09adc22adb18387e7c40db076af32b394db288
https://github.com/llvm/llvm-project/commit/8a09adc22adb18387e7c40db076af32b394db288
Author: Nikita Popov <npopov at redhat.com>
Date: 2025-07-30 (Wed, 30 Jul 2025)
Changed paths:
M llvm/lib/Transforms/InstCombine/InstructionCombining.cpp
M llvm/test/Transforms/InstCombine/canonicalize-gep-constglob.ll
M llvm/test/Transforms/InstCombine/gep-vector.ll
M llvm/test/Transforms/InstCombine/getelementptr.ll
M llvm/test/Transforms/InstCombine/icmp-gep.ll
M llvm/test/Transforms/InstCombine/loadstore-alignment.ll
M llvm/test/Transforms/InstCombine/pr58901.ll
M llvm/test/Transforms/InstCombine/ptrtoint-nullgep.ll
M llvm/test/Transforms/InstCombine/sub.ll
Log Message:
-----------
[InstCombine] Split GEPs with multiple variable indices (#137297)
Split GEPs that have more than one variable index into two. This is in
preparation for the ptradd migration, which will not support multi-index
GEPs.
This also enables the split off part to be CSEd and LICMed.
Commit: ef6eaa045aaa20c8c01d35c02b6200b3be5d5bb4
https://github.com/llvm/llvm-project/commit/ef6eaa045aaa20c8c01d35c02b6200b3be5d5bb4
Author: Fabian Ritter <fabian.ritter at amd.com>
Date: 2025-07-30 (Wed, 30 Jul 2025)
Changed paths:
M llvm/include/llvm/CodeGen/GlobalISel/GenericMachineInstrs.h
M llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h
M llvm/include/llvm/CodeGen/MachineInstr.h
M llvm/include/llvm/Target/GlobalISel/Combine.td
M llvm/lib/CodeGen/GlobalISel/MachineIRBuilder.cpp
M llvm/lib/CodeGen/MIRParser/MILexer.cpp
M llvm/lib/CodeGen/MIRParser/MILexer.h
M llvm/lib/CodeGen/MIRParser/MIParser.cpp
M llvm/lib/CodeGen/MIRPrinter.cpp
M llvm/lib/CodeGen/MachineInstr.cpp
M llvm/test/CodeGen/AArch64/GlobalISel/arm64-irtranslator-gep.ll
M llvm/test/CodeGen/AArch64/GlobalISel/arm64-irtranslator-switch.ll
M llvm/test/CodeGen/AArch64/GlobalISel/arm64-irtranslator.ll
M llvm/test/CodeGen/AArch64/GlobalISel/call-lowering-sret-demotion.ll
M llvm/test/CodeGen/AArch64/GlobalISel/call-translator-cse.ll
M llvm/test/CodeGen/AArch64/GlobalISel/call-translator-ios.ll
M llvm/test/CodeGen/AArch64/GlobalISel/call-translator.ll
M llvm/test/CodeGen/AArch64/GlobalISel/inline-memcpy-forced.mir
M llvm/test/CodeGen/AArch64/GlobalISel/inline-memcpy.mir
M llvm/test/CodeGen/AArch64/GlobalISel/inline-memmove.mir
M llvm/test/CodeGen/AArch64/GlobalISel/inline-memset.mir
M llvm/test/CodeGen/AArch64/GlobalISel/inline-small-memcpy.mir
M llvm/test/CodeGen/AArch64/GlobalISel/legalize-and.mir
M llvm/test/CodeGen/AArch64/GlobalISel/legalize-bswap.mir
M llvm/test/CodeGen/AArch64/GlobalISel/legalize-constant.mir
M llvm/test/CodeGen/AArch64/GlobalISel/legalize-extract-vector-elt.mir
M llvm/test/CodeGen/AArch64/GlobalISel/legalize-fpext.mir
M llvm/test/CodeGen/AArch64/GlobalISel/legalize-fptrunc.mir
M llvm/test/CodeGen/AArch64/GlobalISel/legalize-insert-vector-elt.mir
M llvm/test/CodeGen/AArch64/GlobalISel/legalize-load-store-vector.mir
M llvm/test/CodeGen/AArch64/GlobalISel/legalize-load-store.mir
M llvm/test/CodeGen/AArch64/GlobalISel/legalize-min-max.mir
M llvm/test/CodeGen/AArch64/GlobalISel/legalize-non-pow2-load-store.mir
M llvm/test/CodeGen/AArch64/GlobalISel/legalize-or.mir
M llvm/test/CodeGen/AArch64/GlobalISel/legalize-phi.mir
M llvm/test/CodeGen/AArch64/GlobalISel/legalize-shuffle-vector.mir
M llvm/test/CodeGen/AArch64/GlobalISel/legalize-vacopy.mir
M llvm/test/CodeGen/AArch64/GlobalISel/legalize-xor.mir
M llvm/test/CodeGen/AArch64/arm64-this-return.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/bug-legalization-artifact-combiner-dead-def.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/function-returns.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-amdgpu_kernel.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-call-abi-attribute-hints.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-call-implicit-args.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-call-non-fixed.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-call-return-values.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-call-sret.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-call.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-function-args.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-indirect-call.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-invariant.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-sibling-call.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-addrspacecast.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-extract-vector-elt.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-insert-vector-elt.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-constant-32bit.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-constant.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-flat.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-global.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-local.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-private.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-sextload-global.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-store-global.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-store.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-zextload-global.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.s.buffer.load.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-load.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-split-scalar-load-metadata.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-uniform-load-noclobber.mir
M llvm/test/CodeGen/ARM/GlobalISel/arm-irtranslator.ll
M llvm/test/CodeGen/ARM/GlobalISel/arm-legalize-load-store.mir
M llvm/test/CodeGen/M68k/GlobalISel/irtranslator-call.ll
M llvm/test/CodeGen/M68k/GlobalISel/legalize-load-store.mir
M llvm/test/CodeGen/Mips/GlobalISel/irtranslator/aggregate_struct_return.ll
M llvm/test/CodeGen/Mips/GlobalISel/irtranslator/sret_pointer.ll
M llvm/test/CodeGen/Mips/GlobalISel/irtranslator/var_arg.ll
M llvm/test/CodeGen/Mips/GlobalISel/mips-prelegalizer-combiner/inline-memcpy.mir
M llvm/test/CodeGen/Mips/GlobalISel/regbankselect/load.mir
M llvm/test/CodeGen/Mips/GlobalISel/regbankselect/long_ambiguous_chain_s32.mir
M llvm/test/CodeGen/Mips/GlobalISel/regbankselect/long_ambiguous_chain_s64.mir
M llvm/test/CodeGen/Mips/GlobalISel/regbankselect/store.mir
M llvm/test/CodeGen/RISCV/GlobalISel/irtranslator/calling-conv-ilp32-ilp32f-ilp32d-common.ll
M llvm/test/CodeGen/RISCV/GlobalISel/irtranslator/calling-conv-lp64-lp64f-lp64d-common.ll
M llvm/test/CodeGen/RISCV/GlobalISel/irtranslator/vararg.ll
M llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-icmp-rv32.mir
M llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-load-rv32.mir
M llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-load-rv64.mir
M llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-store-rv32.mir
M llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-store-rv64.mir
M llvm/test/CodeGen/X86/GlobalISel/legalize-memop-scalar-32.mir
M llvm/test/CodeGen/X86/GlobalISel/legalize-undef.mir
M llvm/test/CodeGen/X86/GlobalISel/regbankselect-x87.ll
M llvm/test/CodeGen/X86/GlobalISel/x86_64-irtranslator-struct-return.ll
M llvm/unittests/CodeGen/GlobalISel/LegalizerTest.cpp
M llvm/utils/update_mir_test_checks.py
Log Message:
-----------
[GISel] Introduce MIFlags::InBounds (#150900)
This flag applies to G_PTR_ADD instructions and indicates that the operation
implements an inbounds getelementptr operation, i.e., the pointer operand is in
bounds wrt. the allocated object it is based on, and the arithmetic does not
change that.
It is set when the IRTranslator lowers inbounds GEPs (currently only in some
cases, to be extended with a future PR), and in the
(build|materialize)ObjectPtrOffset functions.
Inbounds information is useful in ISel when we have instructions that perform
address computations whose intermediate steps must be in the same memory region
as the final result. A follow-up patch will start using it for AMDGPU's flat
memory instructions, where the immediate offset must not affect the memory
aperture of the address.
This is analogous to a concurrent effort in SDAG: #131862
(related: #140017, #141725).
For SWDEV-516125.
Commit: cf9be978a099e041129202f1a739666ed5ae648b
https://github.com/llvm/llvm-project/commit/cf9be978a099e041129202f1a739666ed5ae648b
Author: Donát Nagy <donat.nagy at ericsson.com>
Date: 2025-07-30 (Wed, 30 Jul 2025)
Changed paths:
M clang/lib/StaticAnalyzer/Checkers/BasicObjCFoundationChecks.cpp
Log Message:
-----------
[NFC][analyzer] Clean bug type use in BasicObjCFoundationChecks (#151141)
This commit eliminates some corrupted variants of the once-widespread
`mutable std::unique_ptr<BugType>` antipattern from the checker file
`BasicObjCFoundationChecks.cpp`.
Previous purges probably missed these because there are slight mutations
(e.g. using a subclass of `BugType` instead of `BugType`) and therefore
some natural search terms (e.g. `make_unique<BugType>`) didn't produce
matches in this file.
Commit: ffcee267f1633d22d83ef4b4ebfb70ca00c7cd14
https://github.com/llvm/llvm-project/commit/ffcee267f1633d22d83ef4b4ebfb70ca00c7cd14
Author: Michael Kruse <llvm-project at meinersbur.de>
Date: 2025-07-30 (Wed, 30 Jul 2025)
Changed paths:
M mlir/include/mlir/Target/LLVMIR/ModuleTranslation.h
M mlir/lib/Dialect/LLVMIR/IR/NVVMDialect.cpp
M mlir/lib/Target/LLVMIR/Dialect/NVVM/LLVMIRToNVVMTranslation.cpp
Log Message:
-----------
[MLIR] Avoid #include OMPIRBuilder.h (#151302)
`#include "llvm/Frontend/OpenMP/OMPIRBuilder.h"` can be replaced with
forward-declarations of `OpenMPIRBuilder` and `CanonicalLoopInfo`. This
also avoids a dependency to `omp_gen` of the LLVMFrontendOpenMP
component which is included indirectly in `OMPIRBuilder.h`.
Since its inclusion in #147069, additional indirect dependencies on
headers included by `OMPIRBuilder.h` were introduced as well. These are
now included directly.
Reported-by: fabrizio-indirli
See
https://github.com/llvm/llvm-project/pull/147069#issuecomment-3114034973
Commit: 638383cb7110469d652c75a58b42afc80e863574
https://github.com/llvm/llvm-project/commit/638383cb7110469d652c75a58b42afc80e863574
Author: Fraser Cormack <fraser at codeplay.com>
Date: 2025-07-30 (Wed, 30 Jul 2025)
Changed paths:
M llvm/lib/Target/SPIRV/SPIRVLegalizerInfo.cpp
M llvm/lib/Target/SPIRV/SPIRVLegalizerInfo.h
A llvm/test/CodeGen/SPIRV/llvm-intrinsics/is_fpclass.ll
Log Message:
-----------
[SPIRV] Support G_IS_FPCLASS (#148637)
This commit adds custom legalization for G_IS_FPCLASS, corresponding to
the @llvm.is.fpclass intrinsic.
The lowering strategy is essentially copied and adjusted from the
target-agnostic LegalizeHelper::lowerISFPCLASS legalization. The reason
we can't just use that directly is that the series of instruction it
expands to aren't logged in the SPIR-V backend's register/type
book-keeping, leading to issues later on in the compilation process.
As such the code introduced here was copied from the aforementioned
helper method, with some notable changes:
* Each new instruction's destination register must have a SPIR-V type
registered to it.
* Instead of a COPY from the floating-point type to integer, we issue a
SPIR-V OpBitcast directly. The backend doesn't currently appear to
handle bitcast-like COPYs.
Fixes #72862
Commit: 0d8abc2188f8a8c48dd40a9d0ad2fb0945611b44
https://github.com/llvm/llvm-project/commit/0d8abc2188f8a8c48dd40a9d0ad2fb0945611b44
Author: Mehdi Amini <joker.eph at gmail.com>
Date: 2025-07-30 (Wed, 30 Jul 2025)
Changed paths:
M mlir/lib/Conversion/NVGPUToNVVM/NVGPUToNVVM.cpp
M mlir/lib/Conversion/NVVMToLLVM/NVVMToLLVM.cpp
Log Message:
-----------
[MLIR] Migrate NVVM to the new LDBG debug macro (NFC) (#151162)
Commit: 4fdf07fd46f250804bc1ce5f9193a3ed990e308b
https://github.com/llvm/llvm-project/commit/4fdf07fd46f250804bc1ce5f9193a3ed990e308b
Author: Ricardo Jesus <rjj at nvidia.com>
Date: 2025-07-30 (Wed, 30 Jul 2025)
Changed paths:
M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
M llvm/test/CodeGen/AArch64/abds-neg.ll
M llvm/test/CodeGen/AArch64/abds.ll
M llvm/test/CodeGen/AArch64/abdu-neg.ll
M llvm/test/CodeGen/AArch64/abdu.ll
M llvm/test/CodeGen/AArch64/midpoint-int.ll
Log Message:
-----------
[AArch64] Use CNEG for absolute difference patterns. (#151177)
The current code generated for absolute difference patterns
(a > b ? a - b : b - a) typically consists of sequences of:
```
sub w8, w1, w0
subs w9, w0, w1
csel w0, w9, w8, hi
```
The first sub is redundant if the csel is replaced by a cneg:
```
subs w8, w0, w1
cneg w0, w8, ls
```
This is achieved by canonicalising
```
select_cc lhs, rhs, sub(lhs, rhs), sub(rhs, lhs), cc ->
select_cc lhs, rhs, sub(lhs, rhs), neg(sub(lhs, rhs)), cc
select_cc lhs, rhs, sub(rhs, lhs), sub(lhs, rhs), cc ->
select_cc lhs, rhs, neg(sub(lhs, rhs)), sub(lhs, rhs), cc
```
as the second forms can already be matched.
This helps with some of the patterns in #118413.
Commit: 4562b557a68895f0f3f5f70875eff28a42cc0f17
https://github.com/llvm/llvm-project/commit/4562b557a68895f0f3f5f70875eff28a42cc0f17
Author: Joseph Huber <huberjn at outlook.com>
Date: 2025-07-30 (Wed, 30 Jul 2025)
Changed paths:
M clang/lib/Driver/Driver.cpp
M clang/test/Driver/hip-dependent-options.hip
M clang/test/Driver/hip-phases.hip
Log Message:
-----------
[HIP] Handle `-fhip-emit-reloctable` in the new driver (#151237)
Summary:
Support for this was missing, here it pretty much overrides the normal
bundling behavior and also requires a few errors to be emitted.
Commit: b7bfbc0c4c7b20d6623a5b0b4a7fea8ae08a62da
https://github.com/llvm/llvm-project/commit/b7bfbc0c4c7b20d6623a5b0b4a7fea8ae08a62da
Author: Tobias Gysi <tobias.gysi at nextsilicon.com>
Date: 2025-07-30 (Wed, 30 Jul 2025)
Changed paths:
M mlir/include/mlir/Dialect/ArmSME/IR/ArmSMEIntrinsicOps.td
M mlir/include/mlir/Dialect/ArmSVE/IR/ArmSVE.td
M mlir/include/mlir/Dialect/LLVMIR/LLVMIntrinsicOps.td
M mlir/include/mlir/Dialect/LLVMIR/LLVMOpBase.td
M mlir/include/mlir/Dialect/LLVMIR/LLVMOps.td
M mlir/include/mlir/Dialect/LLVMIR/ROCDLOps.td
M mlir/include/mlir/Interfaces/CallInterfaces.td
M mlir/include/mlir/Target/LLVMIR/ModuleImport.h
M mlir/include/mlir/Target/LLVMIR/ModuleTranslation.h
M mlir/lib/Target/LLVMIR/Dialect/LLVMIR/LLVMToLLVMIRTranslation.cpp
M mlir/lib/Target/LLVMIR/LLVMImportInterface.cpp
M mlir/lib/Target/LLVMIR/ModuleImport.cpp
M mlir/lib/Target/LLVMIR/ModuleTranslation.cpp
M mlir/test/Target/LLVMIR/Import/intrinsic.ll
M mlir/test/Target/LLVMIR/llvmir-intrinsics.mlir
M utils/bazel/llvm-project-overlay/mlir/test/mlir-tblgen/BUILD.bazel
Log Message:
-----------
Reland "[mlir][llvm] Add intrinsic arg and result attribute support (… (#151125)
…… (#151099)
This reverts commit 2780b8f22058b35a8e70045858b87a1966df8df3 to reland
59013d44058ef423a117f95092150e16e16fdb09.
In addition to the original commit this one includes:
- This includes a bazel fix
- Use `let methods` instead of `list<InterfaceMethod> methods`
The original commit message was:
This patch extends the LLVM dialect's intrinsic infra to support
argument and result attributes. Initial support is added for the memory
intrinsics llvm.intr.memcpy, llvm.intr.memmove, and llvm.intr.memset.
Additionally, an ArgAndResultAttrsOpInterface is factored out of
CallOpInterface and CallableOpInterface, enabling operations to have
argument and result attributes without requiring them to be a call or a
callable operation.
Commit: 5c87374f2a33015d39b4e2634c2949851e463602
https://github.com/llvm/llvm-project/commit/5c87374f2a33015d39b4e2634c2949851e463602
Author: Chaitanya Koparkar <ckoparkar at gmail.com>
Date: 2025-07-30 (Wed, 30 Jul 2025)
Changed paths:
M mlir/docs/DefiningDialects/AttributesAndTypes.md
Log Message:
-----------
[mlir][docs] Use APIntParameter instead of APInt in AttributesAndTypes.md (#151315)
Fixes #151314.
Commit: 97fa9a1f5332dd05883fb67b37ce42c3c9d667be
https://github.com/llvm/llvm-project/commit/97fa9a1f5332dd05883fb67b37ce42c3c9d667be
Author: Mehdi Amini <joker.eph at gmail.com>
Date: 2025-07-30 (Wed, 30 Jul 2025)
Changed paths:
M mlir/include/mlir/Dialect/ArmSME/IR/ArmSMEIntrinsicOps.td
M mlir/include/mlir/Dialect/ArmSVE/IR/ArmSVE.td
M mlir/include/mlir/Dialect/LLVMIR/LLVMIntrinsicOps.td
M mlir/include/mlir/Dialect/LLVMIR/LLVMOpBase.td
M mlir/include/mlir/Dialect/LLVMIR/LLVMOps.td
M mlir/include/mlir/Dialect/LLVMIR/ROCDLOps.td
M mlir/include/mlir/Interfaces/CallInterfaces.td
M mlir/include/mlir/Target/LLVMIR/ModuleImport.h
M mlir/include/mlir/Target/LLVMIR/ModuleTranslation.h
M mlir/lib/Target/LLVMIR/Dialect/LLVMIR/LLVMToLLVMIRTranslation.cpp
M mlir/lib/Target/LLVMIR/LLVMImportInterface.cpp
M mlir/lib/Target/LLVMIR/ModuleImport.cpp
M mlir/lib/Target/LLVMIR/ModuleTranslation.cpp
M mlir/test/Target/LLVMIR/Import/intrinsic.ll
M mlir/test/Target/LLVMIR/llvmir-intrinsics.mlir
M utils/bazel/llvm-project-overlay/mlir/test/mlir-tblgen/BUILD.bazel
Log Message:
-----------
Revert "Reland "[mlir][llvm] Add intrinsic arg and result attribute support (…" (#151316)
Reverts llvm/llvm-project#151125
Broke the gcc-7 build:
include/mlir/Target/LLVMIR/ModuleTranslation.h:318:34: error: no type
named 'CallBase' in namespace 'llvm'
llvm::CallBase *call,
~~~~~~^
Commit: 58d70dc62b219cd89ba434c96928a0d9c1b23a60
https://github.com/llvm/llvm-project/commit/58d70dc62b219cd89ba434c96928a0d9c1b23a60
Author: Guy David <49722543+guy-david at users.noreply.github.com>
Date: 2025-07-30 (Wed, 30 Jul 2025)
Changed paths:
M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
M llvm/lib/Target/AArch64/AArch64InstrInfo.td
M llvm/test/CodeGen/AArch64/selectopt-const.ll
A llvm/test/CodeGen/AArch64/store-float-conversion.ll
M llvm/test/CodeGen/AArch64/tbl-loops.ll
Log Message:
-----------
[AArch64] Keep floating-point conversion in SIMD (#147707)
Stores can be issued faster if the result is kept in the SIMD/FP
registers.
The `HasOneUse` guards against creating two floating point conversions,
if for example there's some arithmetic done on the converted value as
well. Another approach would be to inspect the user instructions during
lowering, but I don't see that type of check in the lowering too often.
Commit: 1d6e68e63aa28783ad0de7d0b46238ce95849f2f
https://github.com/llvm/llvm-project/commit/1d6e68e63aa28783ad0de7d0b46238ce95849f2f
Author: Donát Nagy <donat.nagy at ericsson.com>
Date: 2025-07-30 (Wed, 30 Jul 2025)
Changed paths:
M clang/include/clang/StaticAnalyzer/Checkers/Checkers.td
M clang/lib/StaticAnalyzer/Checkers/NSErrorChecker.cpp
Log Message:
-----------
[analyzer] Conversion to CheckerFamily: NSOrCFErrorDerefChecker (#151171)
This commit converts the class `NSOrCFErrorDerefChecker` to the checker
family framework and simplifies some parts of the implementation (e.g.
removes two very trivial subclasses of `BugType`).
This commit is almost NFC, the only technically "functional" change is
that it removes the hidden modeling checker `NSOrCFErrorDerefChecker`
which was only relevant as an implementation detail of the old checker
registration procedure.
Commit: eca29aa0f17152f9801e08d14e3d0da6702262b5
https://github.com/llvm/llvm-project/commit/eca29aa0f17152f9801e08d14e3d0da6702262b5
Author: Donát Nagy <donat.nagy at ericsson.com>
Date: 2025-07-30 (Wed, 30 Jul 2025)
Changed paths:
M clang/include/clang/StaticAnalyzer/Checkers/Checkers.td
M clang/lib/StaticAnalyzer/Checkers/StackAddrEscapeChecker.cpp
M clang/test/Analysis/analyzer-enabled-checkers.c
M clang/test/Analysis/std-c-library-functions-arg-enabled-checkers.c
Log Message:
-----------
[analyzer] Conversion to CheckerFamily: StackAddrEscapeChecker (#151136)
This commit converts the class StackAddrEscapeChecker to the checker
family framework and slightly simplifies the implementation.
This commit is almost NFC, the only technically "functional" change is
that it removes the hidden modeling checker `core.StackAddrEscapeBase`
which was only relevant as an implementation detail of the old checker
registration procedure.
Commit: 9164d206b33d61c93f5fc4628797485f96d654ca
https://github.com/llvm/llvm-project/commit/9164d206b33d61c93f5fc4628797485f96d654ca
Author: Michael Kruse <llvm-project at meinersbur.de>
Date: 2025-07-30 (Wed, 30 Jul 2025)
Changed paths:
M mlir/include/mlir/Target/LLVMIR/ModuleTranslation.h
Log Message:
-----------
[MLIR] Missing declaration build fix
The sanizer bots are reporting a missing declaration:
```
In file included from /home/b/sanitizer-x86_64-linux-bootstrap-ubsan/build/llvm-project/mlir/lib/Dialect/LLVMIR/Transforms/InlinerInterfaceImpl.cpp:17:
In file included from /home/b/sanitizer-x86_64-linux-bootstrap-ubsan/build/llvm-project/mlir/include/mlir/Dialect/LLVMIR/NVVMDialect.h:26:
/home/b/sanitizer-x86_64-linux-bootstrap-ubsan/build/llvm-project/mlir/include/mlir/Target/LLVMIR/ModuleTranslation.h:318:34: error: no type named 'CallBase' in namespace 'llvm'
318 | llvm::CallBase *call,
| ~~~~~~^
1 error generated.
```
https://lab.llvm.org/buildbot/#/builders/94/builds/9340
https://lab.llvm.org/buildbot/#/builders/24/builds/11029
https://lab.llvm.org/buildbot/#/builders/169/builds/13454
https://lab.llvm.org/buildbot/#/builders/25/builds/10250
PR #151302 removed some indirect header #includes which had to be
includes explicitly. I do not know why this particular error only occurs
with the sanitizer buildbots.
Fix by adding a forward declaration.
Commit: fbdf4ec2a56075e5632ba2104a0b0a3cee0ae747
https://github.com/llvm/llvm-project/commit/fbdf4ec2a56075e5632ba2104a0b0a3cee0ae747
Author: Luke Hutton <luke.hutton at arm.com>
Date: 2025-07-30 (Wed, 30 Jul 2025)
Changed paths:
M mlir/lib/Dialect/Tosa/Transforms/TosaProfileCompliance.cpp
M mlir/test/Dialect/Tosa/invalid.mlir
M mlir/test/Dialect/Tosa/level_check.mlir
Log Message:
-----------
[mlir][tosa] Fix invalid data type combinations check (#150066)
Previously this check assumed that if an operator exists in profile
complimance (TosaProfileComplianceData.h.inc), an entry exists in both
the profiles and extensions section. However, this is not necessarily
the case.
This commit changes the check such that it doesn't assume the above. In
doing so, it allows more operators to be checked for invalid data type
combinations, which were otherwise skipped previously.
Commit: 3e5f1a66bde9d6c55955da73dfd054394d377b7e
https://github.com/llvm/llvm-project/commit/3e5f1a66bde9d6c55955da73dfd054394d377b7e
Author: Nikita Popov <npopov at redhat.com>
Date: 2025-07-30 (Wed, 30 Jul 2025)
Changed paths:
M llvm/test/Transforms/InstCombine/2010-11-21-SizeZeroTypeGEP.ll
Log Message:
-----------
[InstCombine] Generate test checks (NFC)
Commit: 730d05b0ebb73ada1f86ebea32496737d796b13c
https://github.com/llvm/llvm-project/commit/730d05b0ebb73ada1f86ebea32496737d796b13c
Author: Nikita Popov <npopov at redhat.com>
Date: 2025-07-30 (Wed, 30 Jul 2025)
Changed paths:
M llvm/test/Transforms/InstCombine/gepphigep.ll
Log Message:
-----------
[InstCombine] Avoid tmp var conflicts in test (NFC)
Commit: 807a82d40789a5e50174f979accca77c8b6841b5
https://github.com/llvm/llvm-project/commit/807a82d40789a5e50174f979accca77c8b6841b5
Author: Jay Foad <jay.foad at amd.com>
Date: 2025-07-30 (Wed, 30 Jul 2025)
Changed paths:
M llvm/test/TableGen/get-named-operand-idx.td
M llvm/utils/TableGen/InstrInfoEmitter.cpp
Log Message:
-----------
[TableGen] Implement getNamedOperandIdx with another table lookup. NFC. (#151116)
Use direct table lookup instead of a switch over all opcodes.
In my Release+Asserts build this reduced the code size for
AMDGPU::getNamedOperandIdx from 11422 to 80 bytes, and the total size of
all its tables (including the jump table for the switch) from 243564 to
155020 bytes.
Commit: 635e6d76530328b8412fbf985708dad26e3f8ea5
https://github.com/llvm/llvm-project/commit/635e6d76530328b8412fbf985708dad26e3f8ea5
Author: Aethezz <64500703+Aethezz at users.noreply.github.com>
Date: 2025-07-30 (Wed, 30 Jul 2025)
Changed paths:
M clang/lib/StaticAnalyzer/Checkers/CheckPlacementNew.cpp
M clang/test/Analysis/placement-new.cpp
Log Message:
-----------
[analyzer] Fix FP for cplusplus.placement new #149240 (#150161)
Fix false positive where warnings were asserted for placement new even
when no additional space is requested
The PlacementNewChecker incorrectly triggered warnings when the storage
provided matched or exceeded the allocated type size, causing false
positives. Now the warning triggers only when the provided storage is
strictly less than the required size.
Add test cases covering exact size, undersize, and oversize scenarios to
validate the fix.
Fixes #149240
Commit: 36961202fbf45968cc273fa78fe3479409f5a9c7
https://github.com/llvm/llvm-project/commit/36961202fbf45968cc273fa78fe3479409f5a9c7
Author: Nikita Popov <npopov at redhat.com>
Date: 2025-07-30 (Wed, 30 Jul 2025)
Changed paths:
A llvm/test/Transforms/InstCombine/vectorgep-crash.ll
R llvm/test/Transforms/InstSimplify/ConstProp/vectorgep-crash.ll
Log Message:
-----------
[InstSimplify] Regenerate test checks (NFC)
Change the function name so that UTC works properly. Also move the
test into the InstCombine directory, as that's the pass that's
actually being tested.
Commit: deced287ad1da9a61302e12e0406f8be36f3831b
https://github.com/llvm/llvm-project/commit/deced287ad1da9a61302e12e0406f8be36f3831b
Author: Tobias Gysi <tobias.gysi at nextsilicon.com>
Date: 2025-07-30 (Wed, 30 Jul 2025)
Changed paths:
M mlir/include/mlir/Dialect/ArmSME/IR/ArmSMEIntrinsicOps.td
M mlir/include/mlir/Dialect/ArmSVE/IR/ArmSVE.td
M mlir/include/mlir/Dialect/LLVMIR/LLVMIntrinsicOps.td
M mlir/include/mlir/Dialect/LLVMIR/LLVMOpBase.td
M mlir/include/mlir/Dialect/LLVMIR/LLVMOps.td
M mlir/include/mlir/Dialect/LLVMIR/ROCDLOps.td
M mlir/include/mlir/Interfaces/CallInterfaces.td
M mlir/include/mlir/Target/LLVMIR/ModuleImport.h
M mlir/include/mlir/Target/LLVMIR/ModuleTranslation.h
M mlir/lib/Target/LLVMIR/Dialect/LLVMIR/LLVMToLLVMIRTranslation.cpp
M mlir/lib/Target/LLVMIR/LLVMImportInterface.cpp
M mlir/lib/Target/LLVMIR/ModuleImport.cpp
M mlir/lib/Target/LLVMIR/ModuleTranslation.cpp
M mlir/test/Target/LLVMIR/Import/intrinsic.ll
M mlir/test/Target/LLVMIR/llvmir-intrinsics.mlir
Log Message:
-----------
Reapply "[mlir][llvm] Add intrinsic arg and result attribute support … (#151324)
…(… (#151099)
This reverts commit 2780b8f22058b35a8e70045858b87a1966df8df3 and relands
b7bfbc0c4c7b20d6623a5b0b4a7fea8ae08a62da.
Adds the following fixes compared to the original PR
(https://github.com/llvm/llvm-project/pull/150783):
- A bazel fix
- Use `let methods` instead of `list<InterfaceMethod> methods`
The missing forward declaration has been added in meantime:
https://github.com/llvm/llvm-project/commit/9164d206b33d61c93f5fc4628797485f96d654ca.
Commit: fcbbcffd2e6ea30097809ba0cd1e3b6003fa862f
https://github.com/llvm/llvm-project/commit/fcbbcffd2e6ea30097809ba0cd1e3b6003fa862f
Author: Martin Storsjö <martin at martin.st>
Date: 2025-07-30 (Wed, 30 Jul 2025)
Changed paths:
M llvm/lib/ObjCopy/COFF/COFFReader.cpp
A llvm/test/tools/llvm-objcopy/COFF/exe-bogus-assoc.test
Log Message:
-----------
[llvm-objcopy] [COFF] Ignore associative sections in executables (#151143)
COFF associative sections is a feature where relocatable object files
can have section snippets marked as related to another section snippet,
so they are kept or discarded in relation to that other section snippet.
When llvm-objcopy removes sections, it also removes sections that are
marked as associative to the removed section (as the associative
sections otherwise would end up orphaned).
In a linked executable module (EXE or DLL), section associativity is
meaningless - thus, we should ignore those fields from the input.
After linking, GNU ld keeps the SectionDefinition auxillary part of
symbols intact as it was in the source object file, which means that it
references section numbers in the source object files.
This fixes https://github.com/llvm/llvm-project/issues/53433.
Commit: 330b40e11fd20e9a29b9c24de17e4ba23afeedc6
https://github.com/llvm/llvm-project/commit/330b40e11fd20e9a29b9c24de17e4ba23afeedc6
Author: Serge Pavlov <sepavloff at gmail.com>
Date: 2025-07-30 (Wed, 30 Jul 2025)
Changed paths:
M clang/lib/Sema/AnalysisBasedWarnings.cpp
A clang/test/SemaCXX/noreturn-weverything.c
Log Message:
-----------
[Analysis] Prevent revisiting block when searching for noreturn vars (#150582)
When searching for noreturn variable initializations, do not visit CFG
blocks that are already visited, it prevents hanging the analysis.
It must fix https://github.com/llvm/llvm-project/issues/150336.
Commit: 17c1921b4a78b2ab3f455278c2a057d164863866
https://github.com/llvm/llvm-project/commit/17c1921b4a78b2ab3f455278c2a057d164863866
Author: Igor Wodiany <igor.wodiany at imgtec.com>
Date: 2025-07-30 (Wed, 30 Jul 2025)
Changed paths:
M mlir/include/mlir/Dialect/SPIRV/IR/SPIRVTypes.h
M mlir/lib/Dialect/SPIRV/IR/SPIRVDialect.cpp
M mlir/lib/Dialect/SPIRV/IR/SPIRVTypes.cpp
M mlir/lib/Target/SPIRV/Deserialization/Deserializer.cpp
M mlir/lib/Target/SPIRV/Deserialization/Deserializer.h
M mlir/lib/Target/SPIRV/Serialization/Serializer.cpp
M mlir/test/Dialect/SPIRV/IR/types.mlir
M mlir/test/Target/SPIRV/memory-ops.mlir
M mlir/test/Target/SPIRV/struct.mlir
M mlir/test/Target/SPIRV/undef.mlir
Log Message:
-----------
[mlir][spirv] Add support for structs decorations (#149793)
An alternative implementation could use `ArrayRef` of `NamedAttribute`s
or `NamedAttrList` to store structs decorations, as the deserializer
uses `NamedAttribute`s for decorations. However, using a custom struct
allows us to store the `spirv::Decoration`s directly rather than its
name in a `StringRef`/`StringAttr`.
Commit: bae8f1336db6a7f3288a7dcf253f2d484743b257
https://github.com/llvm/llvm-project/commit/bae8f1336db6a7f3288a7dcf253f2d484743b257
Author: Sander de Smalen <sander.desmalen at arm.com>
Date: 2025-07-30 (Wed, 30 Jul 2025)
Changed paths:
M llvm/lib/CodeGen/RegisterCoalescer.cpp
M llvm/test/CodeGen/AArch64/GlobalISel/arm64-pcsections.ll
M llvm/test/CodeGen/AArch64/implicit-def-subreg-to-reg-regression.ll
M llvm/test/CodeGen/AArch64/preserve_nonecc_varargs_darwin.ll
A llvm/test/CodeGen/AArch64/register-coalesce-implicit-def-subreg-to-reg.mir
M llvm/test/CodeGen/AArch64/register-coalesce-update-subranges-remat.mir
M llvm/test/CodeGen/PowerPC/aix-vec_insert_elt.ll
M llvm/test/CodeGen/PowerPC/build-vector-tests.ll
M llvm/test/CodeGen/PowerPC/canonical-merge-shuffles.ll
M llvm/test/CodeGen/PowerPC/combine-fneg.ll
M llvm/test/CodeGen/PowerPC/fp-strict-round.ll
M llvm/test/CodeGen/PowerPC/frem.ll
M llvm/test/CodeGen/PowerPC/froundeven-legalization.ll
M llvm/test/CodeGen/PowerPC/handle-f16-storage-type.ll
M llvm/test/CodeGen/PowerPC/ldexp.ll
M llvm/test/CodeGen/PowerPC/llvm.modf.ll
M llvm/test/CodeGen/PowerPC/vec_insert_elt.ll
M llvm/test/CodeGen/PowerPC/vector-constrained-fp-intrinsics.ll
A llvm/test/CodeGen/X86/coalescer-breaks-subreg-to-reg-liveness.ll
M llvm/test/CodeGen/X86/coalescer-implicit-def-regression-imp-operand-assert.mir
A llvm/test/CodeGen/X86/coalescing-subreg-to-reg-requires-subrange-update.mir
A llvm/test/CodeGen/X86/pr76416.ll
M llvm/test/CodeGen/X86/subreg-fail.mir
A llvm/test/CodeGen/X86/subreg-to-reg-coalescing.mir
Log Message:
-----------
Reland "RegisterCoalescer: Add implicit-def of super register when coalescing SUBREG_TO_REG" (#134408)
This tries to reland #123632 (previously reverted by commit
6b1db79887df19bc8e8c946108966aa6021c8b87)
This PR aims to fix coalescing of SUBREG_TO_REG when sub-register
liveness tracking is enabled and this is now the so-manieth
reincarnation of this effort :)
This change is needed in order to enable subreg liveness tracking for
AArch64, because without the implicit-def, Machine Copy Propagation
would remove a 'redundant' copy because it doesn't realise that the
top 32-bits of the register are zeroed, which subsequent instructions
rely on.
Changes compared to previous PR:
* Rather than updating all instructions that define the source register
(SrcReg) of the SUBREG_TO_REG, this new approach only updates
instructions
that define SrcReg when they dominate the SUBREG_TO_REG. The live-ranges
are updated accordingly.
Commit: 3d4f1fee48689465b5026f75414247307db7d34d
https://github.com/llvm/llvm-project/commit/3d4f1fee48689465b5026f75414247307db7d34d
Author: Davide Grohmann <davide.grohmann at arm.com>
Date: 2025-07-30 (Wed, 30 Jul 2025)
Changed paths:
M mlir/lib/Dialect/SPIRV/Transforms/UpdateVCEPass.cpp
M mlir/test/Dialect/SPIRV/Transforms/vce-deduction.mlir
Log Message:
-----------
[mlir][spirv] Fix UpdateVCEPass to deduce the correct set of capabilities (#151108)
When deducing capabilities implied capabilities are not considered,
which causes generation of incorrect SPIR-V modules. This commit fixes
that by pulling in the capability set for all the implied ones.
---------
Signed-off-by: Davide Grohmann <davide.grohmann at arm.com>
Commit: b47d9d033acd26e492bef9429ee9bce640be0901
https://github.com/llvm/llvm-project/commit/b47d9d033acd26e492bef9429ee9bce640be0901
Author: Steve Merritt <steve.merritt at intel.com>
Date: 2025-07-30 (Wed, 30 Jul 2025)
Changed paths:
M clang/lib/CodeGen/CGDebugInfo.cpp
M clang/test/CodeGenCXX/debug-info-gline-tables-only.cpp
Log Message:
-----------
[clang][DebugInfo] Don't emit VTable debug symbols for -gline-tables-only. (#151025)
The -gline-tables-only option emits minimal debug info for functions,
files and line numbers while omitting variables, parameters and most
type information. VTable debug symbols are emitted to facilitate a
debugger's ability to perform automatic type promotion on variables and
parameters. With variables and parameters being omitted, the VTable
symbols are unnecessary.
Commit: 3c62303ac3bfa115681509759a959b2f618d0266
https://github.com/llvm/llvm-project/commit/3c62303ac3bfa115681509759a959b2f618d0266
Author: Timm Baeder <tbaeder at redhat.com>
Date: 2025-07-30 (Wed, 30 Jul 2025)
Changed paths:
M clang/lib/AST/ByteCode/Compiler.h
M clang/lib/AST/ByteCode/Interp.h
Log Message:
-----------
[clang][bytecode] Clean up {Compiler,Interp}.h (#151335)
Remove else after return and remove some unused includes.
Commit: 7e419922a745f7c8d803564b1ff598ed80b1104b
https://github.com/llvm/llvm-project/commit/7e419922a745f7c8d803564b1ff598ed80b1104b
Author: Vitaly Buka <vitalybuka at google.com>
Date: 2025-07-30 (Wed, 30 Jul 2025)
Changed paths:
M bolt/lib/Core/Relocation.cpp
M clang-tools-extra/clangd/FindSymbols.cpp
M clang-tools-extra/clangd/unittests/FindSymbolsTests.cpp
M clang/include/clang/AST/Expr.h
M clang/include/clang/Basic/DiagnosticSemaKinds.td
A clang/include/clang/Driver/CudaInstallationDetector.h
A clang/include/clang/Driver/LazyDetector.h
A clang/include/clang/Driver/RocmInstallationDetector.h
A clang/include/clang/Driver/SyclInstallationDetector.h
M clang/include/clang/StaticAnalyzer/Checkers/Checkers.td
M clang/lib/AST/ByteCode/Compiler.h
M clang/lib/AST/ByteCode/Disasm.cpp
M clang/lib/AST/ByteCode/DynamicAllocator.cpp
M clang/lib/AST/ByteCode/Interp.h
M clang/lib/AST/ByteCode/InterpBlock.cpp
M clang/lib/AST/ByteCode/InterpState.cpp
M clang/lib/AST/ByteCode/Pointer.cpp
M clang/lib/AST/ByteCode/Pointer.h
M clang/lib/Basic/Targets/WebAssembly.cpp
M clang/lib/Basic/Targets/WebAssembly.h
M clang/lib/CodeGen/CGCoroutine.cpp
M clang/lib/CodeGen/CGDebugInfo.cpp
M clang/lib/Driver/Driver.cpp
M clang/lib/Driver/ToolChains/AMDGPU.h
M clang/lib/Driver/ToolChains/Clang.cpp
M clang/lib/Driver/ToolChains/CommonArgs.cpp
M clang/lib/Driver/ToolChains/Cuda.h
M clang/lib/Driver/ToolChains/Darwin.h
M clang/lib/Driver/ToolChains/Gnu.h
M clang/lib/Driver/ToolChains/HIPAMD.h
R clang/lib/Driver/ToolChains/LazyDetector.h
M clang/lib/Driver/ToolChains/MSVC.h
M clang/lib/Driver/ToolChains/MinGW.cpp
M clang/lib/Driver/ToolChains/MinGW.h
R clang/lib/Driver/ToolChains/ROCm.h
M clang/lib/Driver/ToolChains/SYCL.h
M clang/lib/Sema/AnalysisBasedWarnings.cpp
M clang/lib/Sema/SemaConcept.cpp
M clang/lib/Sema/SemaTemplate.cpp
M clang/lib/Sema/SemaTypeTraits.cpp
M clang/lib/StaticAnalyzer/Checkers/BasicObjCFoundationChecks.cpp
M clang/lib/StaticAnalyzer/Checkers/CheckPlacementNew.cpp
M clang/lib/StaticAnalyzer/Checkers/NSErrorChecker.cpp
M clang/lib/StaticAnalyzer/Checkers/StackAddrEscapeChecker.cpp
M clang/test/Analysis/analyzer-enabled-checkers.c
M clang/test/Analysis/placement-new.cpp
M clang/test/Analysis/std-c-library-functions-arg-enabled-checkers.c
M clang/test/CXX/drs/cwg18xx.cpp
M clang/test/CodeGen/AArch64/neon-scalar-copy.c
M clang/test/CodeGen/AArch64/neon-vget.c
M clang/test/CodeGen/AArch64/poly64.c
M clang/test/CodeGenCXX/debug-info-gline-tables-only.cpp
M clang/test/CodeGenCoroutines/coro-await.cpp
M clang/test/Driver/hip-dependent-options.hip
M clang/test/Driver/hip-phases.hip
M clang/test/Driver/mingw-msvcrt.c
M clang/test/Driver/wasm-features.c
M clang/test/Preprocessor/wasm-target-features.c
A clang/test/SemaCXX/noreturn-weverything.c
M clang/test/SemaCXX/overload-resolution-deferred-templates.cpp
M clang/test/SemaCXX/type-traits-unsatisfied-diags-std.cpp
M clang/test/SemaCXX/type-traits-unsatisfied-diags.cpp
M clang/test/SemaTemplate/concepts.cpp
M clang/utils/TableGen/NeonEmitter.cpp
M compiler-rt/test/asan/TestCases/Linux/long-object-path.cpp
M compiler-rt/test/fuzzer/afl-driver-stderr.test
M compiler-rt/test/sanitizer_common/TestCases/suffix-log-path_test.c
M compiler-rt/test/xray/TestCases/Posix/fdr-mode-inmemory.cpp
M compiler-rt/test/xray/TestCases/Posix/fdr-mode-multiple.cpp
M flang/lib/Lower/OpenMP/OpenMP.cpp
M flang/test/Lower/OpenMP/unroll-heuristic01.f90
M flang/test/Lower/OpenMP/unroll-heuristic02.f90
A flang/test/Lower/OpenMP/unroll-heuristic03.f90
M libc/shared/math.h
A libc/shared/math/atanf.h
M libc/src/__support/math/CMakeLists.txt
A libc/src/__support/math/atanf.h
M libc/src/math/generic/CMakeLists.txt
M libc/src/math/generic/atanf.cpp
M libc/test/shared/CMakeLists.txt
M libc/test/shared/shared_math_test.cpp
M libcxx/test/libcxx/utilities/expected/expected.expected/and_then.mandates.verify.cpp
M libcxx/test/libcxx/utilities/expected/expected.expected/or_else.mandates.verify.cpp
M libcxx/test/libcxx/utilities/expected/expected.expected/value.observers.verify.cpp
M libcxx/test/libcxx/utilities/expected/expected.void/and_then.mandates.verify.cpp
M libcxx/test/std/containers/sequences/array/array.creation/to_array.verify.cpp
M libcxx/test/std/containers/views/mdspan/mdspan/conversion.verify.cpp
M libcxx/test/std/utilities/function.objects/func.bind.partial/bind_back.verify.cpp
M libcxx/test/std/utilities/function.objects/func.bind_front/bind_front.verify.cpp
M lld/ELF/Arch/LoongArch.cpp
M lld/test/ELF/loongarch-relax-pc-hi20-lo12.s
M lldb/source/Plugins/Process/Utility/AuxVector.cpp
M lldb/source/Plugins/Process/Utility/AuxVector.h
M llvm/docs/LangRef.rst
M llvm/include/llvm/BinaryFormat/SFrame.h
M llvm/include/llvm/BinaryFormat/SFrameConstants.def
M llvm/include/llvm/CodeGen/GlobalISel/GenericMachineInstrs.h
M llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h
M llvm/include/llvm/CodeGen/MachineInstr.h
M llvm/include/llvm/IR/NVVMIntrinsicUtils.h
M llvm/include/llvm/Object/SFrameParser.h
M llvm/include/llvm/Passes/CodeGenPassBuilder.h
M llvm/include/llvm/Target/CGPassBuilderOption.h
M llvm/include/llvm/Target/GlobalISel/Combine.td
M llvm/lib/Analysis/ConstantFolding.cpp
M llvm/lib/Analysis/UniformityAnalysis.cpp
M llvm/lib/BinaryFormat/SFrame.cpp
M llvm/lib/CodeGen/GlobalISel/MachineIRBuilder.cpp
M llvm/lib/CodeGen/MIRParser/MILexer.cpp
M llvm/lib/CodeGen/MIRParser/MILexer.h
M llvm/lib/CodeGen/MIRParser/MIParser.cpp
M llvm/lib/CodeGen/MIRPrinter.cpp
M llvm/lib/CodeGen/MachineInstr.cpp
M llvm/lib/CodeGen/RegisterCoalescer.cpp
M llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
M llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
M llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
M llvm/lib/ObjCopy/COFF/COFFReader.cpp
M llvm/lib/Object/SFrameParser.cpp
M llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp
M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
M llvm/lib/Target/AArch64/AArch64InstrInfo.td
M llvm/lib/Target/AArch64/AArch64MIPeepholeOpt.cpp
M llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp
M llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
M llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeHelper.cpp
M llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
M llvm/lib/Target/AMDGPU/CMakeLists.txt
M llvm/lib/Target/AMDGPU/SIInsertWaitcnts.cpp
M llvm/lib/Target/AMDGPU/SIMemoryLegalizer.cpp
M llvm/lib/Target/AMDGPU/SOPInstructions.td
M llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp
M llvm/lib/Target/RISCV/RISCVCallingConv.td
M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
M llvm/lib/Target/RISCV/RISCVISelLowering.h
M llvm/lib/Target/RISCV/RISCVInterleavedAccess.cpp
M llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp
M llvm/lib/Target/RISCV/RISCVTargetTransformInfo.h
M llvm/lib/Target/SPIRV/SPIRVLegalizerInfo.cpp
M llvm/lib/Target/SPIRV/SPIRVLegalizerInfo.h
M llvm/lib/Target/WebAssembly/WebAssembly.td
M llvm/lib/Target/WebAssembly/WebAssemblyInstrInfo.td
M llvm/lib/Target/WebAssembly/WebAssemblySubtarget.h
M llvm/lib/Target/X86/CMakeLists.txt
M llvm/lib/Target/X86/X86ISelLowering.cpp
M llvm/lib/Transforms/InstCombine/InstructionCombining.cpp
M llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
M llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp
M llvm/lib/Transforms/Vectorize/VPlanTransforms.h
M llvm/lib/Transforms/Vectorize/VPlanVerifier.cpp
M llvm/test/Analysis/CostModel/RISCV/masked_ldst.ll
A llvm/test/Analysis/ScalarEvolution/zext-add.ll
M llvm/test/CodeGen/AArch64/GlobalISel/arm64-irtranslator-gep.ll
M llvm/test/CodeGen/AArch64/GlobalISel/arm64-irtranslator-switch.ll
M llvm/test/CodeGen/AArch64/GlobalISel/arm64-irtranslator.ll
M llvm/test/CodeGen/AArch64/GlobalISel/arm64-pcsections.ll
M llvm/test/CodeGen/AArch64/GlobalISel/call-lowering-sret-demotion.ll
M llvm/test/CodeGen/AArch64/GlobalISel/call-translator-cse.ll
M llvm/test/CodeGen/AArch64/GlobalISel/call-translator-ios.ll
M llvm/test/CodeGen/AArch64/GlobalISel/call-translator.ll
M llvm/test/CodeGen/AArch64/GlobalISel/inline-memcpy-forced.mir
M llvm/test/CodeGen/AArch64/GlobalISel/inline-memcpy.mir
M llvm/test/CodeGen/AArch64/GlobalISel/inline-memmove.mir
M llvm/test/CodeGen/AArch64/GlobalISel/inline-memset.mir
M llvm/test/CodeGen/AArch64/GlobalISel/inline-small-memcpy.mir
M llvm/test/CodeGen/AArch64/GlobalISel/legalize-and.mir
M llvm/test/CodeGen/AArch64/GlobalISel/legalize-bswap.mir
M llvm/test/CodeGen/AArch64/GlobalISel/legalize-constant.mir
M llvm/test/CodeGen/AArch64/GlobalISel/legalize-extract-vector-elt.mir
M llvm/test/CodeGen/AArch64/GlobalISel/legalize-fpext.mir
M llvm/test/CodeGen/AArch64/GlobalISel/legalize-fptrunc.mir
M llvm/test/CodeGen/AArch64/GlobalISel/legalize-insert-vector-elt.mir
M llvm/test/CodeGen/AArch64/GlobalISel/legalize-load-store-vector.mir
M llvm/test/CodeGen/AArch64/GlobalISel/legalize-load-store.mir
M llvm/test/CodeGen/AArch64/GlobalISel/legalize-min-max.mir
M llvm/test/CodeGen/AArch64/GlobalISel/legalize-non-pow2-load-store.mir
M llvm/test/CodeGen/AArch64/GlobalISel/legalize-or.mir
M llvm/test/CodeGen/AArch64/GlobalISel/legalize-phi.mir
M llvm/test/CodeGen/AArch64/GlobalISel/legalize-shuffle-vector.mir
M llvm/test/CodeGen/AArch64/GlobalISel/legalize-vacopy.mir
M llvm/test/CodeGen/AArch64/GlobalISel/legalize-xor.mir
M llvm/test/CodeGen/AArch64/aarch64-isel-csinc-type.ll
M llvm/test/CodeGen/AArch64/abds-neg.ll
M llvm/test/CodeGen/AArch64/abds.ll
M llvm/test/CodeGen/AArch64/abdu-neg.ll
M llvm/test/CodeGen/AArch64/abdu.ll
M llvm/test/CodeGen/AArch64/add-extract.ll
M llvm/test/CodeGen/AArch64/addsub.ll
M llvm/test/CodeGen/AArch64/arm64-this-return.ll
M llvm/test/CodeGen/AArch64/arm64-vmul.ll
M llvm/test/CodeGen/AArch64/combine-and-like.ll
M llvm/test/CodeGen/AArch64/implicit-def-subreg-to-reg-regression.ll
M llvm/test/CodeGen/AArch64/logical_shifted_reg.ll
M llvm/test/CodeGen/AArch64/midpoint-int.ll
M llvm/test/CodeGen/AArch64/neg-abs.ll
M llvm/test/CodeGen/AArch64/neg-selects.ll
M llvm/test/CodeGen/AArch64/neon-dot-product.ll
M llvm/test/CodeGen/AArch64/preserve_nonecc_varargs_darwin.ll
M llvm/test/CodeGen/AArch64/reassocmls.ll
A llvm/test/CodeGen/AArch64/register-coalesce-implicit-def-subreg-to-reg.mir
M llvm/test/CodeGen/AArch64/register-coalesce-update-subranges-remat.mir
M llvm/test/CodeGen/AArch64/selectopt-const.ll
M llvm/test/CodeGen/AArch64/sme2-intrinsics-ld1.ll
M llvm/test/CodeGen/AArch64/sme2-intrinsics-ldnt1.ll
A llvm/test/CodeGen/AArch64/store-float-conversion.ll
M llvm/test/CodeGen/AArch64/tbl-loops.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/bug-legalization-artifact-combiner-dead-def.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/function-returns.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-amdgpu_kernel.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-call-abi-attribute-hints.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-call-implicit-args.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-call-non-fixed.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-call-return-values.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-call-sret.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-call.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-function-args.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-indirect-call.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-invariant.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-sibling-call.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-addrspacecast.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-extract-vector-elt.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-insert-vector-elt.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-constant-32bit.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-constant.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-flat.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-global.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-local.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-private.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-sextload-global.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-store-global.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-store.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-zextload-global.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/memory-legalizer-atomic-fence.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.s.buffer.load.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-load.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-split-scalar-load-metadata.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-uniform-load-noclobber.mir
A llvm/test/CodeGen/AMDGPU/insert-waitcnts-fence-soft.mir
A llvm/test/CodeGen/AMDGPU/lds-dma-workgroup-release.ll
M llvm/test/CodeGen/AMDGPU/llc-pipeline-npm.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.mfma.xf32.gfx942.ll
A llvm/test/CodeGen/AMDGPU/merged-bfx-opt.ll
M llvm/test/CodeGen/AMDGPU/saddsat.ll
M llvm/test/CodeGen/AMDGPU/uaddsat.ll
M llvm/test/CodeGen/AMDGPU/vector-reduce-smax.ll
M llvm/test/CodeGen/AMDGPU/vector-reduce-smin.ll
M llvm/test/CodeGen/AMDGPU/vector-reduce-umax.ll
M llvm/test/CodeGen/AMDGPU/vector-reduce-umin.ll
M llvm/test/CodeGen/AMDGPU/workitem-intrinsic-opts.ll
M llvm/test/CodeGen/ARM/GlobalISel/arm-irtranslator.ll
M llvm/test/CodeGen/ARM/GlobalISel/arm-legalize-load-store.mir
M llvm/test/CodeGen/ARM/fcopysign.ll
M llvm/test/CodeGen/LoongArch/lasx/ir-instruction/insertelement.ll
M llvm/test/CodeGen/LoongArch/lsx/ir-instruction/insertelement.ll
M llvm/test/CodeGen/M68k/GlobalISel/irtranslator-call.ll
M llvm/test/CodeGen/M68k/GlobalISel/legalize-load-store.mir
M llvm/test/CodeGen/Mips/GlobalISel/irtranslator/aggregate_struct_return.ll
M llvm/test/CodeGen/Mips/GlobalISel/irtranslator/sret_pointer.ll
M llvm/test/CodeGen/Mips/GlobalISel/irtranslator/var_arg.ll
M llvm/test/CodeGen/Mips/GlobalISel/mips-prelegalizer-combiner/inline-memcpy.mir
M llvm/test/CodeGen/Mips/GlobalISel/regbankselect/load.mir
M llvm/test/CodeGen/Mips/GlobalISel/regbankselect/long_ambiguous_chain_s32.mir
M llvm/test/CodeGen/Mips/GlobalISel/regbankselect/long_ambiguous_chain_s64.mir
M llvm/test/CodeGen/Mips/GlobalISel/regbankselect/store.mir
M llvm/test/CodeGen/PowerPC/aix-vec_insert_elt.ll
M llvm/test/CodeGen/PowerPC/build-vector-tests.ll
M llvm/test/CodeGen/PowerPC/canonical-merge-shuffles.ll
M llvm/test/CodeGen/PowerPC/combine-fneg.ll
M llvm/test/CodeGen/PowerPC/fp-strict-round.ll
M llvm/test/CodeGen/PowerPC/frem.ll
M llvm/test/CodeGen/PowerPC/froundeven-legalization.ll
M llvm/test/CodeGen/PowerPC/handle-f16-storage-type.ll
M llvm/test/CodeGen/PowerPC/ldexp.ll
M llvm/test/CodeGen/PowerPC/llvm.modf.ll
M llvm/test/CodeGen/PowerPC/vec_insert_elt.ll
M llvm/test/CodeGen/PowerPC/vector-constrained-fp-intrinsics.ll
M llvm/test/CodeGen/RISCV/GlobalISel/irtranslator/calling-conv-ilp32-ilp32f-ilp32d-common.ll
M llvm/test/CodeGen/RISCV/GlobalISel/irtranslator/calling-conv-lp64-lp64f-lp64d-common.ll
M llvm/test/CodeGen/RISCV/GlobalISel/irtranslator/vararg.ll
M llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-icmp-rv32.mir
M llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-load-rv32.mir
M llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-load-rv64.mir
M llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-store-rv32.mir
M llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-store-rv64.mir
A llvm/test/CodeGen/RISCV/calling-conv-preserve-most.ll
A llvm/test/CodeGen/SPIRV/llvm-intrinsics/is_fpclass.ll
M llvm/test/CodeGen/WebAssembly/target-features-cpus.ll
M llvm/test/CodeGen/X86/GlobalISel/legalize-memop-scalar-32.mir
M llvm/test/CodeGen/X86/GlobalISel/legalize-undef.mir
M llvm/test/CodeGen/X86/GlobalISel/regbankselect-x87.ll
M llvm/test/CodeGen/X86/GlobalISel/x86_64-irtranslator-struct-return.ll
M llvm/test/CodeGen/X86/apx/cf.ll
A llvm/test/CodeGen/X86/coalescer-breaks-subreg-to-reg-liveness.ll
M llvm/test/CodeGen/X86/coalescer-implicit-def-regression-imp-operand-assert.mir
A llvm/test/CodeGen/X86/coalescing-subreg-to-reg-requires-subrange-update.mir
M llvm/test/CodeGen/X86/combine-add-ssat.ll
M llvm/test/CodeGen/X86/combine-add-usat.ll
M llvm/test/CodeGen/X86/combine-sub-ssat.ll
M llvm/test/CodeGen/X86/combine-sub-usat.ll
M llvm/test/CodeGen/X86/load-combine.ll
M llvm/test/CodeGen/X86/pr33960.ll
A llvm/test/CodeGen/X86/pr76416.ll
M llvm/test/CodeGen/X86/subreg-fail.mir
A llvm/test/CodeGen/X86/subreg-to-reg-coalescing.mir
M llvm/test/TableGen/get-named-operand-idx.td
M llvm/test/Transforms/GVN/PRE/load-metadata.ll
M llvm/test/Transforms/GVN/PRE/load-pre-across-backedge.ll
M llvm/test/Transforms/GVN/PRE/load-pre-nonlocal.ll
M llvm/test/Transforms/GVN/PRE/lpre-call-wrap.ll
M llvm/test/Transforms/GVN/PRE/rle-addrspace-cast.ll
M llvm/test/Transforms/GVN/PRE/rle-semidominated.ll
M llvm/test/Transforms/InstCombine/2010-11-21-SizeZeroTypeGEP.ll
M llvm/test/Transforms/InstCombine/canonicalize-gep-constglob.ll
M llvm/test/Transforms/InstCombine/gep-vector.ll
M llvm/test/Transforms/InstCombine/gepphigep.ll
M llvm/test/Transforms/InstCombine/getelementptr.ll
M llvm/test/Transforms/InstCombine/icmp-gep.ll
M llvm/test/Transforms/InstCombine/loadstore-alignment.ll
M llvm/test/Transforms/InstCombine/pr58901.ll
M llvm/test/Transforms/InstCombine/ptrtoint-nullgep.ll
M llvm/test/Transforms/InstCombine/sub.ll
A llvm/test/Transforms/InstCombine/vectorgep-crash.ll
R llvm/test/Transforms/InstSimplify/ConstProp/vectorgep-crash.ll
M llvm/test/Transforms/LoopVectorize/RISCV/evl-compatible-loops.ll
M llvm/test/Transforms/LoopVectorize/RISCV/inloop-reduction.ll
M llvm/test/Transforms/LoopVectorize/RISCV/interleaved-masked-access.ll
M llvm/test/Transforms/LoopVectorize/RISCV/pr88802.ll
M llvm/test/Transforms/LoopVectorize/RISCV/scalable-tailfold.ll
M llvm/test/Transforms/LoopVectorize/RISCV/tail-folding-bin-unary-ops-args.ll
M llvm/test/Transforms/LoopVectorize/RISCV/tail-folding-call-intrinsics.ll
M llvm/test/Transforms/LoopVectorize/RISCV/tail-folding-cast-intrinsics.ll
M llvm/test/Transforms/LoopVectorize/RISCV/tail-folding-cond-reduction.ll
M llvm/test/Transforms/LoopVectorize/RISCV/tail-folding-div.ll
M llvm/test/Transforms/LoopVectorize/RISCV/tail-folding-fixed-order-recurrence.ll
M llvm/test/Transforms/LoopVectorize/RISCV/tail-folding-gather-scatter.ll
M llvm/test/Transforms/LoopVectorize/RISCV/tail-folding-inloop-reduction.ll
M llvm/test/Transforms/LoopVectorize/RISCV/tail-folding-interleave.ll
M llvm/test/Transforms/LoopVectorize/RISCV/tail-folding-intermediate-store.ll
M llvm/test/Transforms/LoopVectorize/RISCV/tail-folding-iv32.ll
M llvm/test/Transforms/LoopVectorize/RISCV/tail-folding-known-no-overflow.ll
M llvm/test/Transforms/LoopVectorize/RISCV/tail-folding-masked-loadstore.ll
M llvm/test/Transforms/LoopVectorize/RISCV/tail-folding-ordered-reduction.ll
M llvm/test/Transforms/LoopVectorize/RISCV/tail-folding-reduction.ll
M llvm/test/Transforms/LoopVectorize/RISCV/tail-folding-reverse-load-store.ll
M llvm/test/Transforms/LoopVectorize/RISCV/tail-folding-safe-dep-distance.ll
M llvm/test/Transforms/LoopVectorize/RISCV/tail-folding-uniform-store.ll
M llvm/test/Transforms/LoopVectorize/RISCV/truncate-to-minimal-bitwidth-cost.ll
M llvm/test/Transforms/LoopVectorize/RISCV/truncate-to-minimal-bitwidth-evl-crash.ll
M llvm/test/Transforms/LoopVectorize/RISCV/type-info-cache-evl-crash.ll
M llvm/test/Transforms/LoopVectorize/RISCV/uniform-load-store.ll
A llvm/test/Transforms/LoopVectorize/RISCV/vector-loop-backedge-elimination-with-evl.ll
M llvm/test/Transforms/LoopVectorize/RISCV/vectorize-vp-intrinsics.ll
A llvm/test/tools/llvm-objcopy/COFF/exe-bogus-assoc.test
A llvm/test/tools/llvm-readobj/ELF/sframe-fde.test
M llvm/test/tools/llvm-readobj/ELF/sframe-header.test
M llvm/tools/llvm-readobj/ELFDumper.cpp
M llvm/unittests/CodeGen/CMakeLists.txt
M llvm/unittests/CodeGen/GlobalISel/LegalizerTest.cpp
M llvm/unittests/CodeGen/SelectionDAGAddressAnalysisTest.cpp
A llvm/unittests/CodeGen/SelectionDAGNodeConstructionTest.cpp
M llvm/unittests/CodeGen/SelectionDAGPatternMatchTest.cpp
A llvm/unittests/CodeGen/SelectionDAGTestBase.h
M llvm/utils/TableGen/InstrInfoEmitter.cpp
M llvm/utils/UpdateTestChecks/asm.py
M llvm/utils/gn/secondary/llvm/unittests/CodeGen/BUILD.gn
M llvm/utils/update_mir_test_checks.py
M mlir/docs/DefiningDialects/AttributesAndTypes.md
M mlir/include/mlir/Dialect/ArmSME/IR/ArmSMEIntrinsicOps.td
M mlir/include/mlir/Dialect/ArmSVE/IR/ArmSVE.td
M mlir/include/mlir/Dialect/LLVMIR/LLVMIntrinsicOps.td
M mlir/include/mlir/Dialect/LLVMIR/LLVMOpBase.td
M mlir/include/mlir/Dialect/LLVMIR/LLVMOps.td
M mlir/include/mlir/Dialect/LLVMIR/ROCDLOps.td
M mlir/include/mlir/Dialect/SPIRV/IR/SPIRVTypes.h
M mlir/include/mlir/Interfaces/CallInterfaces.td
M mlir/include/mlir/Target/LLVMIR/ModuleImport.h
M mlir/include/mlir/Target/LLVMIR/ModuleTranslation.h
M mlir/lib/Conversion/NVGPUToNVVM/NVGPUToNVVM.cpp
M mlir/lib/Conversion/NVVMToLLVM/NVVMToLLVM.cpp
M mlir/lib/Dialect/LLVMIR/IR/NVVMDialect.cpp
M mlir/lib/Dialect/SPIRV/IR/SPIRVDialect.cpp
M mlir/lib/Dialect/SPIRV/IR/SPIRVTypes.cpp
M mlir/lib/Dialect/SPIRV/Transforms/UpdateVCEPass.cpp
M mlir/lib/Dialect/Tosa/Transforms/TosaProfileCompliance.cpp
M mlir/lib/Target/LLVMIR/Dialect/LLVMIR/LLVMToLLVMIRTranslation.cpp
M mlir/lib/Target/LLVMIR/Dialect/NVVM/LLVMIRToNVVMTranslation.cpp
M mlir/lib/Target/LLVMIR/LLVMImportInterface.cpp
M mlir/lib/Target/LLVMIR/ModuleImport.cpp
M mlir/lib/Target/LLVMIR/ModuleTranslation.cpp
M mlir/lib/Target/SPIRV/Deserialization/Deserializer.cpp
M mlir/lib/Target/SPIRV/Deserialization/Deserializer.h
M mlir/lib/Target/SPIRV/Serialization/Serializer.cpp
M mlir/test/Dialect/SPIRV/IR/types.mlir
M mlir/test/Dialect/SPIRV/Transforms/vce-deduction.mlir
M mlir/test/Dialect/Tosa/invalid.mlir
M mlir/test/Dialect/Tosa/level_check.mlir
M mlir/test/Target/LLVMIR/Import/intrinsic.ll
M mlir/test/Target/LLVMIR/llvmir-intrinsics.mlir
M mlir/test/Target/SPIRV/memory-ops.mlir
M mlir/test/Target/SPIRV/struct.mlir
M mlir/test/Target/SPIRV/undef.mlir
M offload/tools/offload-tblgen/CMakeLists.txt
M utils/bazel/llvm-project-overlay/libc/BUILD.bazel
Log Message:
-----------
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Created using spr 1.3.6
Compare: https://github.com/llvm/llvm-project/compare/cd628134732c...7e419922a745
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