[all-commits] [llvm/llvm-project] bae8f1: Reland "RegisterCoalescer: Add implicit-def of sup...

[Sander de Smalen via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: bae8f1336db6a7f3288a7dcf253f2d484743b257
      https://github.com/llvm/llvm-project/commit/bae8f1336db6a7f3288a7dcf253f2d484743b257
  Author: Sander de Smalen <sander.desmalen at arm.com>
  Date:   2025-07-30 (Wed, 30 Jul 2025)

  Changed paths:
    M llvm/lib/CodeGen/RegisterCoalescer.cpp
    M llvm/test/CodeGen/AArch64/GlobalISel/arm64-pcsections.ll
    M llvm/test/CodeGen/AArch64/implicit-def-subreg-to-reg-regression.ll
    M llvm/test/CodeGen/AArch64/preserve_nonecc_varargs_darwin.ll
    A llvm/test/CodeGen/AArch64/register-coalesce-implicit-def-subreg-to-reg.mir
    M llvm/test/CodeGen/AArch64/register-coalesce-update-subranges-remat.mir
    M llvm/test/CodeGen/PowerPC/aix-vec_insert_elt.ll
    M llvm/test/CodeGen/PowerPC/build-vector-tests.ll
    M llvm/test/CodeGen/PowerPC/canonical-merge-shuffles.ll
    M llvm/test/CodeGen/PowerPC/combine-fneg.ll
    M llvm/test/CodeGen/PowerPC/fp-strict-round.ll
    M llvm/test/CodeGen/PowerPC/frem.ll
    M llvm/test/CodeGen/PowerPC/froundeven-legalization.ll
    M llvm/test/CodeGen/PowerPC/handle-f16-storage-type.ll
    M llvm/test/CodeGen/PowerPC/ldexp.ll
    M llvm/test/CodeGen/PowerPC/llvm.modf.ll
    M llvm/test/CodeGen/PowerPC/vec_insert_elt.ll
    M llvm/test/CodeGen/PowerPC/vector-constrained-fp-intrinsics.ll
    A llvm/test/CodeGen/X86/coalescer-breaks-subreg-to-reg-liveness.ll
    M llvm/test/CodeGen/X86/coalescer-implicit-def-regression-imp-operand-assert.mir
    A llvm/test/CodeGen/X86/coalescing-subreg-to-reg-requires-subrange-update.mir
    A llvm/test/CodeGen/X86/pr76416.ll
    M llvm/test/CodeGen/X86/subreg-fail.mir
    A llvm/test/CodeGen/X86/subreg-to-reg-coalescing.mir

  Log Message:
  -----------
  Reland "RegisterCoalescer: Add implicit-def of super register when coalescing SUBREG_TO_REG" (#134408)

This tries to reland #123632 (previously reverted by commit
6b1db79887df19bc8e8c946108966aa6021c8b87)

This PR aims to fix coalescing of SUBREG_TO_REG when sub-register
liveness tracking is enabled and this is now the so-manieth
reincarnation of this effort :)

This change is needed in order to enable subreg liveness tracking for 
AArch64, because without the implicit-def, Machine Copy Propagation
would remove a 'redundant' copy because it doesn't realise that the 
top 32-bits of the register are zeroed, which subsequent instructions
rely on. 

Changes compared to previous PR: 

* Rather than updating all instructions that define the source register
(SrcReg) of the SUBREG_TO_REG, this new approach only updates
instructions
that define SrcReg when they dominate the SUBREG_TO_REG. The live-ranges
  are updated accordingly.



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