[all-commits] [llvm/llvm-project] cc8c94: [VPlan] Convert EVL loops to variable-length stepp...

[Shih-Po Hung via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: cc8c941e17558ba427de06e72c8ad96d7b17ced1
      https://github.com/llvm/llvm-project/commit/cc8c941e17558ba427de06e72c8ad96d7b17ced1
  Author: Shih-Po Hung <shihpo.hung at sifive.com>
  Date:   2025-07-30 (Wed, 30 Jul 2025)

  Changed paths:
    M llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
    M llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp
    M llvm/lib/Transforms/Vectorize/VPlanTransforms.h
    M llvm/lib/Transforms/Vectorize/VPlanVerifier.cpp
    M llvm/test/Transforms/LoopVectorize/RISCV/evl-compatible-loops.ll
    M llvm/test/Transforms/LoopVectorize/RISCV/inloop-reduction.ll
    M llvm/test/Transforms/LoopVectorize/RISCV/interleaved-masked-access.ll
    M llvm/test/Transforms/LoopVectorize/RISCV/pr88802.ll
    M llvm/test/Transforms/LoopVectorize/RISCV/scalable-tailfold.ll
    M llvm/test/Transforms/LoopVectorize/RISCV/tail-folding-bin-unary-ops-args.ll
    M llvm/test/Transforms/LoopVectorize/RISCV/tail-folding-call-intrinsics.ll
    M llvm/test/Transforms/LoopVectorize/RISCV/tail-folding-cast-intrinsics.ll
    M llvm/test/Transforms/LoopVectorize/RISCV/tail-folding-cond-reduction.ll
    M llvm/test/Transforms/LoopVectorize/RISCV/tail-folding-div.ll
    M llvm/test/Transforms/LoopVectorize/RISCV/tail-folding-fixed-order-recurrence.ll
    M llvm/test/Transforms/LoopVectorize/RISCV/tail-folding-gather-scatter.ll
    M llvm/test/Transforms/LoopVectorize/RISCV/tail-folding-inloop-reduction.ll
    M llvm/test/Transforms/LoopVectorize/RISCV/tail-folding-interleave.ll
    M llvm/test/Transforms/LoopVectorize/RISCV/tail-folding-intermediate-store.ll
    M llvm/test/Transforms/LoopVectorize/RISCV/tail-folding-iv32.ll
    M llvm/test/Transforms/LoopVectorize/RISCV/tail-folding-known-no-overflow.ll
    M llvm/test/Transforms/LoopVectorize/RISCV/tail-folding-masked-loadstore.ll
    M llvm/test/Transforms/LoopVectorize/RISCV/tail-folding-ordered-reduction.ll
    M llvm/test/Transforms/LoopVectorize/RISCV/tail-folding-reduction.ll
    M llvm/test/Transforms/LoopVectorize/RISCV/tail-folding-reverse-load-store.ll
    M llvm/test/Transforms/LoopVectorize/RISCV/tail-folding-safe-dep-distance.ll
    M llvm/test/Transforms/LoopVectorize/RISCV/tail-folding-uniform-store.ll
    M llvm/test/Transforms/LoopVectorize/RISCV/truncate-to-minimal-bitwidth-cost.ll
    M llvm/test/Transforms/LoopVectorize/RISCV/truncate-to-minimal-bitwidth-evl-crash.ll
    M llvm/test/Transforms/LoopVectorize/RISCV/type-info-cache-evl-crash.ll
    M llvm/test/Transforms/LoopVectorize/RISCV/uniform-load-store.ll
    A llvm/test/Transforms/LoopVectorize/RISCV/vector-loop-backedge-elimination-with-evl.ll
    M llvm/test/Transforms/LoopVectorize/RISCV/vectorize-vp-intrinsics.ll

  Log Message:
  -----------
  [VPlan] Convert EVL loops to variable-length stepping after dissolution (#147222)

Loop regions require fixed-length steps and rounded-up trip counts, but
after dissolution creates explicit control flow, EVL loops can leverage
variable-length stepping with original trip counts.

This patch adds a post-dissolution transform pass to convert EVL loops
from fixed-length to variable-length stepping .



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