[all-commits] [llvm/llvm-project] 75116f: [GISel] Introduce MIFlags::InBounds

Fabian Ritter via All-commits all-commits at lists.llvm.org
Tue Jul 29 23:33:19 PDT 2025 

  Branch: refs/heads/users/ritter-x2a/07-24-_gisel_introduce_miflags_inbounds
  Home:   https://github.com/llvm/llvm-project
  Commit: 75116fa835d7aa2b57ebe59c8bc909f0e3d0bf8c
      https://github.com/llvm/llvm-project/commit/75116fa835d7aa2b57ebe59c8bc909f0e3d0bf8c
  Author: Fabian Ritter <fabian.ritter at amd.com>
  Date:   2025-07-30 (Wed, 30 Jul 2025)

  Changed paths:
    M llvm/include/llvm/CodeGen/GlobalISel/GenericMachineInstrs.h
    M llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h
    M llvm/include/llvm/CodeGen/MachineInstr.h
    M llvm/lib/CodeGen/GlobalISel/MachineIRBuilder.cpp
    M llvm/lib/CodeGen/MIRParser/MILexer.cpp
    M llvm/lib/CodeGen/MIRParser/MILexer.h
    M llvm/lib/CodeGen/MIRParser/MIParser.cpp
    M llvm/lib/CodeGen/MIRPrinter.cpp
    M llvm/lib/CodeGen/MachineInstr.cpp
    M llvm/test/CodeGen/AArch64/GlobalISel/arm64-irtranslator-gep.ll
    M llvm/test/CodeGen/AArch64/GlobalISel/arm64-irtranslator-switch.ll
    M llvm/test/CodeGen/AArch64/GlobalISel/arm64-irtranslator.ll
    M llvm/test/CodeGen/AArch64/GlobalISel/call-lowering-sret-demotion.ll
    M llvm/test/CodeGen/AArch64/GlobalISel/call-translator-cse.ll
    M llvm/test/CodeGen/AArch64/GlobalISel/call-translator-ios.ll
    M llvm/test/CodeGen/AArch64/GlobalISel/call-translator.ll
    M llvm/test/CodeGen/AArch64/GlobalISel/inline-memcpy-forced.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/inline-memcpy.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/inline-memmove.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/inline-memset.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/inline-small-memcpy.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/legalize-and.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/legalize-bswap.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/legalize-constant.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/legalize-extract-vector-elt.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/legalize-fpext.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/legalize-fptrunc.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/legalize-insert-vector-elt.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/legalize-load-store-vector.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/legalize-load-store.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/legalize-min-max.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/legalize-non-pow2-load-store.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/legalize-or.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/legalize-phi.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/legalize-shuffle-vector.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/legalize-vacopy.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/legalize-xor.mir
    M llvm/test/CodeGen/AArch64/arm64-this-return.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/bug-legalization-artifact-combiner-dead-def.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/function-returns.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-amdgpu_kernel.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-call-abi-attribute-hints.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-call-implicit-args.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-call-non-fixed.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-call-return-values.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-call-sret.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-call.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-function-args.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-indirect-call.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-invariant.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-sibling-call.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-addrspacecast.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-extract-vector-elt.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-insert-vector-elt.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-constant-32bit.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-constant.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-flat.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-global.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-local.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-private.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-sextload-global.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-store-global.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-store.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-zextload-global.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.s.buffer.load.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-load.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-split-scalar-load-metadata.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-uniform-load-noclobber.mir
    M llvm/test/CodeGen/ARM/GlobalISel/arm-irtranslator.ll
    M llvm/test/CodeGen/ARM/GlobalISel/arm-legalize-load-store.mir
    M llvm/test/CodeGen/Mips/GlobalISel/irtranslator/aggregate_struct_return.ll
    M llvm/test/CodeGen/Mips/GlobalISel/irtranslator/sret_pointer.ll
    M llvm/test/CodeGen/Mips/GlobalISel/irtranslator/var_arg.ll
    M llvm/test/CodeGen/Mips/GlobalISel/mips-prelegalizer-combiner/inline-memcpy.mir
    M llvm/test/CodeGen/Mips/GlobalISel/regbankselect/load.mir
    M llvm/test/CodeGen/Mips/GlobalISel/regbankselect/long_ambiguous_chain_s32.mir
    M llvm/test/CodeGen/Mips/GlobalISel/regbankselect/long_ambiguous_chain_s64.mir
    M llvm/test/CodeGen/Mips/GlobalISel/regbankselect/store.mir
    M llvm/test/CodeGen/RISCV/GlobalISel/irtranslator/calling-conv-ilp32-ilp32f-ilp32d-common.ll
    M llvm/test/CodeGen/RISCV/GlobalISel/irtranslator/calling-conv-lp64-lp64f-lp64d-common.ll
    M llvm/test/CodeGen/RISCV/GlobalISel/irtranslator/vararg.ll
    M llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-icmp-rv32.mir
    M llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-load-rv32.mir
    M llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-load-rv64.mir
    M llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-store-rv32.mir
    M llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-store-rv64.mir
    M llvm/test/CodeGen/X86/GlobalISel/legalize-memop-scalar-32.mir
    M llvm/test/CodeGen/X86/GlobalISel/legalize-undef.mir
    M llvm/test/CodeGen/X86/GlobalISel/regbankselect-x87.ll
    M llvm/test/CodeGen/X86/GlobalISel/x86_64-irtranslator-struct-return.ll
    M llvm/unittests/CodeGen/GlobalISel/LegalizerTest.cpp
    M llvm/utils/update_mir_test_checks.py

  Log Message:
  -----------
  [GISel] Introduce MIFlags::InBounds

This flag applies to G_PTR_ADD instructions and indicates that the operation
implements an inbounds getelementptr operation, i.e., the pointer operand is in
bounds wrt. the allocated object it is based on, and the arithmetic does not
change that.

It is set when the IRTranslator lowers inbounds GEPs (currently only in some
cases, to be extended with a future PR), and in the
(build|materialize)ObjectPtrOffset functions.

Inbounds information is useful in ISel when we have instructions that perform
address computations whose intermediate steps must be in the same memory region
as the final result. A follow-up patch will start using it for AMDGPU's flat
memory instructions, where the immediate offset must not affect the memory
aperture of the address.

This is analogous to a concurrent effort in SDAG: #131862
(related: #140017, #141725).

For SWDEV-516125.


  Commit: 0d132092c12a5947af8e2277f16483ba6e082a6b
      https://github.com/llvm/llvm-project/commit/0d132092c12a5947af8e2277f16483ba6e082a6b
  Author: Fabian Ritter <fabian.ritter at amd.com>
  Date:   2025-07-30 (Wed, 30 Jul 2025)

  Changed paths:
    M llvm/include/llvm/Target/GlobalISel/Combine.td

  Log Message:
  -----------
  Add InBounds MIFlagEnum to GlobalISel/Combine.td


Compare: https://github.com/llvm/llvm-project/compare/f397bf380f24...0d132092c12a

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