[all-commits] [llvm/llvm-project] db322b: [lldb] Fix libcxx configuration in dotest.py (#151...

Tue Jul 29 21:01:11 PDT 2025

  Branch: refs/heads/users/vitalybuka/spr/ltonfc-switch-lto-api-from-output-parameter-to-return-value
  Home:   https://github.com/llvm/llvm-project
  Commit: db322be91bdee2419eba30a850785098f321a814
      https://github.com/llvm/llvm-project/commit/db322be91bdee2419eba30a850785098f321a814
  Author: Jonas Devlieghere <jonas at devlieghere.com>
  Date:   2025-07-29 (Tue, 29 Jul 2025)

  Changed paths:
    M lldb/packages/Python/lldbsuite/test/dotest.py

  Log Message:
  -----------
  [lldb] Fix libcxx configuration in dotest.py (#151258)

We emit a warning when running the test suite remotely that says the
libcxx arguments will be ignored, but because they're set outside the
conditional block, we're not actually do this. Fix the logic by moving
the configuration in the conditional else-block.

  Commit: fe25445ded152df6cba2efcf053924f3f9f0e3c7
      https://github.com/llvm/llvm-project/commit/fe25445ded152df6cba2efcf053924f3f9f0e3c7
  Author: Hood Chatham <roberthoodchatham at gmail.com>
  Date:   2025-07-29 (Tue, 29 Jul 2025)

  Changed paths:
    M clang/lib/Basic/Targets/WebAssembly.cpp
    M clang/lib/Basic/Targets/WebAssembly.h
    M clang/test/Driver/wasm-features.c
    M clang/test/Preprocessor/wasm-target-features.c
    M llvm/lib/Target/WebAssembly/WebAssembly.td
    M llvm/lib/Target/WebAssembly/WebAssemblyInstrInfo.td
    M llvm/lib/Target/WebAssembly/WebAssemblySubtarget.h
    M llvm/test/CodeGen/WebAssembly/target-features-cpus.ll

  Log Message:
  -----------
  [WebAssembly] Add gc target feature to addBleedingEdgeFeatures (#151107)

See suggestion here:
https://github.com/llvm/llvm-project/pull/150201#discussion_r2237982637

  Commit: 1132562bf3760a929dd53c372cad29fe939e7a7a
      https://github.com/llvm/llvm-project/commit/1132562bf3760a929dd53c372cad29fe939e7a7a
  Author: Morris Hafner <mmha at users.noreply.github.com>
  Date:   2025-07-30 (Wed, 30 Jul 2025)

  Changed paths:
    M clang/lib/CIR/CodeGen/CIRGenModule.cpp
    A clang/test/CIR/CodeGen/cxx-conversion-operators.cpp

  Log Message:
  -----------
  [CIR] Add support for C++ conversion operators (#151066)

This fairly simple addition enables codegen for C++ conversion operators

  Commit: 025b4388f028eabdcebd7c0588a54dc5450e1156
      https://github.com/llvm/llvm-project/commit/025b4388f028eabdcebd7c0588a54dc5450e1156
  Author: Jim Lin <jim at andestech.com>
  Date:   2025-07-30 (Wed, 30 Jul 2025)

  Changed paths:
    M llvm/test/MC/RISCV/rvv/zvfbfwma.s

  Log Message:
  -----------
  [RISCV] Remove scalar half FP load/store/move mc tests for Zvfbfwma. NFC.

Zvfbfwma doesn't include scalar half FP load/store/move instructions.

  Commit: f011c99ceb90fbc7b5b0d22652444d4292ef3ee3
      https://github.com/llvm/llvm-project/commit/f011c99ceb90fbc7b5b0d22652444d4292ef3ee3
  Author: Jim Lin <jim at andestech.com>
  Date:   2025-07-30 (Wed, 30 Jul 2025)

  Changed paths:
    M llvm/test/MC/RISCV/rvv/fadd.s
    M llvm/test/MC/RISCV/rvv/fcompare.s
    M llvm/test/MC/RISCV/rvv/fdiv.s
    M llvm/test/MC/RISCV/rvv/fmacc.s
    M llvm/test/MC/RISCV/rvv/fminmax.s
    M llvm/test/MC/RISCV/rvv/fmul.s
    M llvm/test/MC/RISCV/rvv/fmv.s
    M llvm/test/MC/RISCV/rvv/fothers.s
    M llvm/test/MC/RISCV/rvv/freduction.s
    M llvm/test/MC/RISCV/rvv/fsub.s

  Log Message:
  -----------
  [RISCV] Simplify RUN lines in the mc tests for RVV floating-point instructions. NFC.

Replace v with zve32f, as zve32f is sufficient. Remove f extension
since zve32f alrealy implies f.

  Commit: 05bfcd8ae3f1764145b0d7f491f059bcf8537da3
      https://github.com/llvm/llvm-project/commit/05bfcd8ae3f1764145b0d7f491f059bcf8537da3
  Author: Aiden Grossman <aidengrossman at google.com>
  Date:   2025-07-29 (Tue, 29 Jul 2025)

  Changed paths:
    M compiler-rt/test/asan/TestCases/Linux/long-object-path.cpp
    M compiler-rt/test/fuzzer/afl-driver-stderr.test
    M compiler-rt/test/sanitizer_common/TestCases/suffix-log-path_test.c
    M compiler-rt/test/xray/TestCases/Posix/fdr-mode-inmemory.cpp
    M compiler-rt/test/xray/TestCases/Posix/fdr-mode-multiple.cpp

  Log Message:
  -----------
  [compiler-rt] Remove %T from tests (#151265)

%T has been deprecated for about seven years and use is to be avoided
given it doesn't actually create a unique test directory per test, which
can lead to races. Remove it from compiler-rt so we can hopefully remove
it from within llvm-lit.

This patch just touches the tests. There are still uses in some
substitutions defined in compiler-rt/test/lit.common.cfg.py that I want
to leave for a separate patch because it is quite a bit more thorny.

  Commit: 3dfd939a162181cf6c5f1e684abf3763fb2ab3e8
      https://github.com/llvm/llvm-project/commit/3dfd939a162181cf6c5f1e684abf3763fb2ab3e8
  Author: Stanislav Mekhanoshin <Stanislav.Mekhanoshin at amd.com>
  Date:   2025-07-29 (Tue, 29 Jul 2025)

  Changed paths:
    M llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
    M llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp
    M llvm/lib/Target/AMDGPU/GCNSubtarget.h
    M llvm/lib/Target/AMDGPU/SIISelLowering.cpp
    M llvm/lib/Target/AMDGPU/VOP3Instructions.td
    A llvm/test/CodeGen/AMDGPU/GlobalISel/minmaxabs-i64.ll
    M llvm/test/CodeGen/AMDGPU/flat-saddr-atomics.ll
    M llvm/test/CodeGen/AMDGPU/max.ll
    M llvm/test/CodeGen/AMDGPU/min.ll
    M llvm/test/MC/AMDGPU/gfx1250_asm_vop3-fake16.s
    M llvm/test/MC/AMDGPU/gfx1250_asm_vop3.s
    M llvm/test/MC/AMDGPU/gfx1250_asm_vop3_err.s
    M llvm/test/MC/Disassembler/AMDGPU/gfx1250_dasm_vop3.txt

  Log Message:
  -----------
  [AMDGPU] gfx1250 V_{MIN|MAX}_{I|U}64 opcodes (#151256)

  Commit: ee1ecf32451ee87705666cfb919879123d388220
      https://github.com/llvm/llvm-project/commit/ee1ecf32451ee87705666cfb919879123d388220
  Author: wenzhi-cui <40185576+wenzhi-cui at users.noreply.github.com>
  Date:   2025-07-29 (Tue, 29 Jul 2025)

  Changed paths:
    M utils/bazel/llvm-project-overlay/mlir/BUILD.bazel

  Log Message:
  -----------
  Update BUILD.bazel to add RegisterAllPasses/Dialects/Extensions (#151233)

  Commit: 8f09b03aebb71c154f3bbe725c29e3f47d37c26e
      https://github.com/llvm/llvm-project/commit/8f09b03aebb71c154f3bbe725c29e3f47d37c26e
  Author: Chuanqi Xu <yedeng.yd at linux.alibaba.com>
  Date:   2025-07-30 (Wed, 30 Jul 2025)

  Changed paths:
    M clang/lib/Sema/SemaModule.cpp

  Log Message:
  -----------
  [NFC] [Sema] [Modules] Use DynamicRecursiveASTVisitor to reduce generted code size (#151074)

It is better to use DynamicRecursiveASTVisitor than RecursiveASTVisitor
as it can reduce the generated size. And also avoid using a template
type to present callbacks to avoid generating more code too.

  Commit: 9b23e2bf8d69909d959434da5ef392aefcd0b694
      https://github.com/llvm/llvm-project/commit/9b23e2bf8d69909d959434da5ef392aefcd0b694
  Author: Luke Lau <luke at igalia.com>
  Date:   2025-07-30 (Wed, 30 Jul 2025)

  Changed paths:
    M llvm/test/CodeGen/RISCV/rvv/vl-opt-op-info.mir
    M llvm/test/CodeGen/RISCV/rvv/vl-opt.mir

  Log Message:
  -----------
  [RISCV] Add copies to physical registers in VL optimizer tests. NFC (#151170)

In an upcoming patch to support recurrences in the RISCVVLOptimizer, we
need to perform an optimistic dataflow analysis where we assume
instructions have a DemandedVL of zero until a user is encountered.

Because of this if there's no "root" instruction, nothing will be
demanded and all the VLs will be set to zero.

This prepares for this by adding a copy to a physical register in the
MIR tests so that the behaviour is preserved, and matches whats
generated lowering from regular LLVM IR.

  Commit: b663e563cce2bcf6cf7e15799f0ab1cfc56a8361
      https://github.com/llvm/llvm-project/commit/b663e563cce2bcf6cf7e15799f0ab1cfc56a8361
  Author: Luke Lau <luke at igalia.com>
  Date:   2025-07-30 (Wed, 30 Jul 2025)

  Changed paths:
    M llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp
    M llvm/lib/Transforms/Vectorize/VPlanVerifier.cpp
    M llvm/test/Transforms/LoopVectorize/RISCV/pr88802.ll
    M llvm/test/Transforms/LoopVectorize/RISCV/tail-folding-cond-reduction.ll
    M llvm/test/Transforms/LoopVectorize/RISCV/uniform-load-store.ll

  Log Message:
  -----------
  [VPlan] Fix header masks in EVL tail folding (#150202)

With EVL tail folding, the EVL may not always be VF on the
second-to-last iteration.

Recipes that have been converted to VP intrinsics via optimizeMaskToEVL
account for this, but recipes that are left behind will still use the
old header mask which may end up having a different vector length.

This is effectively the same as #95368, and fixes this by converting
header masks from icmp ule wide-canonical-iv, backedge-trip-count ->
icmp ult step-vector, evl. Without it, recipes that fall through
optimizeMaskToEVL may use the wrong vector length, e.g. in #150074 and
#149981.

We really need to split off optimizeMaskToEVL into
VPlanTransforms::optimize and move transformRecipestoEVLRecipes into
tryToBuildVPlanWithVPRecipes, so we don't mix up what is needed for
correctness and what is needed to optimize away the mask computations.
We should be able to still generate a correct albeit suboptimal VPlan
without running optimizeMaskToEVL. I've added a TODO for this, which I
think we can do after #148274

Fixes #150197

  Commit: e10b182a5fb020f6b69ea95d00fd8590bba7559b
      https://github.com/llvm/llvm-project/commit/e10b182a5fb020f6b69ea95d00fd8590bba7559b
  Author: Ziqing Luo <ziqing at udel.edu>
  Date:   2025-07-30 (Wed, 30 Jul 2025)

  Changed paths:
    M clang/lib/Analysis/UnsafeBufferUsage.cpp
    M clang/test/SemaCXX/warn-unsafe-buffer-usage-libc-functions.cpp

  Log Message:
  -----------
  [-Wunsafe-buffer-usage] Support safe patterns of "%.*s" in printf functions (#145862)

The character buffer passed to a "%.*s" specifier may be safely bound if
the precision is properly specified, even if the buffer does not
guarantee null-termination.
For example,
```
void f(std::span<char> span) {
  printf("%.*s", (int)span.size(), span.data());  // "span.data()" does not guarantee null-termination but is safely bound by "span.size()", so this call is safe
}
```
rdar://154072130

  Commit: 57b34376b108c8418b3f6dff55eb5e91d23ae7dd
      https://github.com/llvm/llvm-project/commit/57b34376b108c8418b3f6dff55eb5e91d23ae7dd
  Author: Vitaly Buka <vitalybuka at google.com>
  Date:   2025-07-29 (Tue, 29 Jul 2025)

  Changed paths:
    M clang/lib/Analysis/UnsafeBufferUsage.cpp
    M clang/lib/Basic/Targets/WebAssembly.cpp
    M clang/lib/Basic/Targets/WebAssembly.h
    M clang/lib/CIR/CodeGen/CIRGenModule.cpp
    M clang/lib/Sema/SemaModule.cpp
    A clang/test/CIR/CodeGen/cxx-conversion-operators.cpp
    M clang/test/Driver/wasm-features.c
    M clang/test/Preprocessor/wasm-target-features.c
    M clang/test/SemaCXX/warn-unsafe-buffer-usage-libc-functions.cpp
    M compiler-rt/test/asan/TestCases/Linux/long-object-path.cpp
    M compiler-rt/test/fuzzer/afl-driver-stderr.test
    M compiler-rt/test/sanitizer_common/TestCases/suffix-log-path_test.c
    M compiler-rt/test/xray/TestCases/Posix/fdr-mode-inmemory.cpp
    M compiler-rt/test/xray/TestCases/Posix/fdr-mode-multiple.cpp
    M lldb/packages/Python/lldbsuite/test/dotest.py
    M llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
    M llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp
    M llvm/lib/Target/AMDGPU/GCNSubtarget.h
    M llvm/lib/Target/AMDGPU/SIISelLowering.cpp
    M llvm/lib/Target/AMDGPU/VOP3Instructions.td
    M llvm/lib/Target/WebAssembly/WebAssembly.td
    M llvm/lib/Target/WebAssembly/WebAssemblyInstrInfo.td
    M llvm/lib/Target/WebAssembly/WebAssemblySubtarget.h
    M llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp
    M llvm/lib/Transforms/Vectorize/VPlanVerifier.cpp
    A llvm/test/CodeGen/AMDGPU/GlobalISel/minmaxabs-i64.ll
    M llvm/test/CodeGen/AMDGPU/flat-saddr-atomics.ll
    M llvm/test/CodeGen/AMDGPU/max.ll
    M llvm/test/CodeGen/AMDGPU/min.ll
    M llvm/test/CodeGen/RISCV/rvv/vl-opt-op-info.mir
    M llvm/test/CodeGen/RISCV/rvv/vl-opt.mir
    M llvm/test/CodeGen/WebAssembly/target-features-cpus.ll
    M llvm/test/MC/AMDGPU/gfx1250_asm_vop3-fake16.s
    M llvm/test/MC/AMDGPU/gfx1250_asm_vop3.s
    M llvm/test/MC/AMDGPU/gfx1250_asm_vop3_err.s
    M llvm/test/MC/Disassembler/AMDGPU/gfx1250_dasm_vop3.txt
    M llvm/test/MC/RISCV/rvv/fadd.s
    M llvm/test/MC/RISCV/rvv/fcompare.s
    M llvm/test/MC/RISCV/rvv/fdiv.s
    M llvm/test/MC/RISCV/rvv/fmacc.s
    M llvm/test/MC/RISCV/rvv/fminmax.s
    M llvm/test/MC/RISCV/rvv/fmul.s
    M llvm/test/MC/RISCV/rvv/fmv.s
    M llvm/test/MC/RISCV/rvv/fothers.s
    M llvm/test/MC/RISCV/rvv/freduction.s
    M llvm/test/MC/RISCV/rvv/fsub.s
    M llvm/test/MC/RISCV/rvv/zvfbfwma.s
    M llvm/test/Transforms/LoopVectorize/RISCV/pr88802.ll
    M llvm/test/Transforms/LoopVectorize/RISCV/tail-folding-cond-reduction.ll
    M llvm/test/Transforms/LoopVectorize/RISCV/uniform-load-store.ll
    M utils/bazel/llvm-project-overlay/mlir/BUILD.bazel

  Log Message:
  -----------
  rebase

Created using spr 1.3.6

Compare: https://github.com/llvm/llvm-project/compare/f283a0eb848d...57b34376b108

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