[all-commits] [llvm/llvm-project] 8f09b0: [NFC] [Sema] [Modules] Use DynamicRecursiveASTVisi...

[Matt Arsenault via All-commits]

  Branch: refs/heads/users/arsenm/amdgpu/test-vgpr-cd-selection-mfma-xf32
  Home:   https://github.com/llvm/llvm-project
  Commit: 8f09b03aebb71c154f3bbe725c29e3f47d37c26e
      https://github.com/llvm/llvm-project/commit/8f09b03aebb71c154f3bbe725c29e3f47d37c26e
  Author: Chuanqi Xu <yedeng.yd at linux.alibaba.com>
  Date:   2025-07-30 (Wed, 30 Jul 2025)

  Changed paths:
    M clang/lib/Sema/SemaModule.cpp

  Log Message:
  -----------
  [NFC] [Sema] [Modules] Use DynamicRecursiveASTVisitor to reduce generted code size (#151074)

It is better to use DynamicRecursiveASTVisitor than RecursiveASTVisitor
as it can reduce the generated size. And also avoid using a template
type to present callbacks to avoid generating more code too.


  Commit: 9b23e2bf8d69909d959434da5ef392aefcd0b694
      https://github.com/llvm/llvm-project/commit/9b23e2bf8d69909d959434da5ef392aefcd0b694
  Author: Luke Lau <luke at igalia.com>
  Date:   2025-07-30 (Wed, 30 Jul 2025)

  Changed paths:
    M llvm/test/CodeGen/RISCV/rvv/vl-opt-op-info.mir
    M llvm/test/CodeGen/RISCV/rvv/vl-opt.mir

  Log Message:
  -----------
  [RISCV] Add copies to physical registers in VL optimizer tests. NFC (#151170)

In an upcoming patch to support recurrences in the RISCVVLOptimizer, we
need to perform an optimistic dataflow analysis where we assume
instructions have a DemandedVL of zero until a user is encountered.

Because of this if there's no "root" instruction, nothing will be
demanded and all the VLs will be set to zero.

This prepares for this by adding a copy to a physical register in the
MIR tests so that the behaviour is preserved, and matches whats
generated lowering from regular LLVM IR.


  Commit: b663e563cce2bcf6cf7e15799f0ab1cfc56a8361
      https://github.com/llvm/llvm-project/commit/b663e563cce2bcf6cf7e15799f0ab1cfc56a8361
  Author: Luke Lau <luke at igalia.com>
  Date:   2025-07-30 (Wed, 30 Jul 2025)

  Changed paths:
    M llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp
    M llvm/lib/Transforms/Vectorize/VPlanVerifier.cpp
    M llvm/test/Transforms/LoopVectorize/RISCV/pr88802.ll
    M llvm/test/Transforms/LoopVectorize/RISCV/tail-folding-cond-reduction.ll
    M llvm/test/Transforms/LoopVectorize/RISCV/uniform-load-store.ll

  Log Message:
  -----------
  [VPlan] Fix header masks in EVL tail folding (#150202)

With EVL tail folding, the EVL may not always be VF on the
second-to-last iteration.

Recipes that have been converted to VP intrinsics via optimizeMaskToEVL
account for this, but recipes that are left behind will still use the
old header mask which may end up having a different vector length.

This is effectively the same as #95368, and fixes this by converting
header masks from icmp ule wide-canonical-iv, backedge-trip-count ->
icmp ult step-vector, evl. Without it, recipes that fall through
optimizeMaskToEVL may use the wrong vector length, e.g. in #150074 and
#149981.

We really need to split off optimizeMaskToEVL into
VPlanTransforms::optimize and move transformRecipestoEVLRecipes into
tryToBuildVPlanWithVPRecipes, so we don't mix up what is needed for
correctness and what is needed to optimize away the mask computations.
We should be able to still generate a correct albeit suboptimal VPlan
without running optimizeMaskToEVL. I've added a TODO for this, which I
think we can do after #148274

Fixes #150197


  Commit: e66dfaed60c688646d01beaf206a1200e51ebe28
      https://github.com/llvm/llvm-project/commit/e66dfaed60c688646d01beaf206a1200e51ebe28
  Author: Matt Arsenault <Matthew.Arsenault at amd.com>
  Date:   2025-07-30 (Wed, 30 Jul 2025)

  Changed paths:
    M clang/lib/Sema/SemaModule.cpp
    M llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp
    M llvm/lib/Transforms/Vectorize/VPlanVerifier.cpp
    M llvm/test/CodeGen/RISCV/rvv/vl-opt-op-info.mir
    M llvm/test/CodeGen/RISCV/rvv/vl-opt.mir
    M llvm/test/Transforms/LoopVectorize/RISCV/pr88802.ll
    M llvm/test/Transforms/LoopVectorize/RISCV/tail-folding-cond-reduction.ll
    M llvm/test/Transforms/LoopVectorize/RISCV/uniform-load-store.ll

  Log Message:
  -----------
  Merge branch 'main' into users/arsenm/amdgpu/test-vgpr-cd-selection-mfma-xf32


Compare: https://github.com/llvm/llvm-project/compare/f57cbb53552c...e66dfaed60c6

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