[all-commits] [llvm/llvm-project] ce2383: [RISCV] Combine a vsse from a vsseg with one activ...

[Philip Reames via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: ce2383050867dbdefedec7c4fae4de86d318eadd
      https://github.com/llvm/llvm-project/commit/ce2383050867dbdefedec7c4fae4de86d318eadd
  Author: Philip Reames <preames at rivosinc.com>
  Date:   2025-07-29 (Tue, 29 Jul 2025)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
    M llvm/lib/Target/RISCV/RISCVInterleavedAccess.cpp
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-interleaved-access.ll
    M llvm/test/CodeGen/RISCV/rvv/vector-interleave-store.ll

  Log Message:
  -----------
  [RISCV] Combine a vsse from a vsseg with one active segment (#151198)

This is a rewrite of the current strided store optimization to be a DAG
combine. This allows it to kick in slightly more broadly, in particular
for the scalable lowering paths.



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