[all-commits] [llvm/llvm-project] 2a3f72: [AMDGPU][CodeGen][True16] Correct size calculation...

[Brox Chen via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 2a3f72ee6e435382dd5bc46f2961c3698ac20eec
      https://github.com/llvm/llvm-project/commit/2a3f72ee6e435382dd5bc46f2961c3698ac20eec
  Author: Brox Chen <guochen2 at amd.com>
  Date:   2025-07-29 (Tue, 29 Jul 2025)

  Changed paths:
    M llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
    A llvm/test/CodeGen/AMDGPU/branch-relaxation-inst-size-gfx11.ll

  Log Message:
  -----------
  [AMDGPU][CodeGen][True16] Correct size calculation for d16 insts (#151042)

D16 pesudo instructions are introduced in true16 mode to represet a D16
load/store. In MC lowering, the pesudo instructions are lowered to the
corresponding D16 Lo/Hi MC Inst respecting the register allocation.

However, the pesudo instruction has size 0 and cause an issue in the
Inst size estimation. Use D16 Lo when calculating inst size



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