[all-commits] [llvm/llvm-project] 73245b: [RISCV] Rewrite deinterleave load as vlse optimiza...

[Philip Reames via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 73245b06b3da19ef70e04cf0f0a0d0df1ba82a57
      https://github.com/llvm/llvm-project/commit/73245b06b3da19ef70e04cf0f0a0d0df1ba82a57
  Author: Philip Reames <preames at rivosinc.com>
  Date:   2025-07-29 (Tue, 29 Jul 2025)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
    M llvm/lib/Target/RISCV/RISCVInterleavedAccess.cpp
    M llvm/test/CodeGen/RISCV/rvv/pr141907.ll
    M llvm/test/CodeGen/RISCV/rvv/vector-deinterleave-load.ll
    M llvm/test/CodeGen/RISCV/rvv/vector-deinterleave.ll
    M llvm/test/CodeGen/RISCV/rvv/vp-vector-interleaved-access.ll

  Log Message:
  -----------
  [RISCV] Rewrite deinterleave load as vlse optimization as DAG combine (#150049)

This reworks an existing optimization on the fixed vector (shuffle
based) deinterleave lowering into a DAG combine. This has the effect of
making it kick in much more widely - in particular on the deinterleave
intrinsic (i.e. scalable) path, deinterleaveN (without load) lowering,
but also the intrinsic lowering paths.



To unsubscribe from these emails, change your notification settings at https://github.com/llvm/llvm-project/settings/notifications