[all-commits] [llvm/llvm-project] 7c14c5: [github/CODEOWNERS] Add yozhu as BOLT reviewer

Mon Jul 28 22:06:29 PDT 2025

  Branch: refs/heads/users/MaskRay/spr/mcfragment-use-trailing-data-for-fixed-size-part
  Home:   https://github.com/llvm/llvm-project
  Commit: 7c14c5380a510d8df20be8c681821c1ed558e39c
      https://github.com/llvm/llvm-project/commit/7c14c5380a510d8df20be8c681821c1ed558e39c
  Author: Maksim Panchenko <maks at fb.com>
  Date:   2025-07-28 (Mon, 28 Jul 2025)

  Changed paths:
    M .github/CODEOWNERS

  Log Message:
  -----------
  [github/CODEOWNERS] Add yozhu as BOLT reviewer

  Commit: b39160ddfb625bd57f9113471b15cda748151a10
      https://github.com/llvm/llvm-project/commit/b39160ddfb625bd57f9113471b15cda748151a10
  Author: Yanzuo Liu <zwuis at outlook.com>
  Date:   2025-07-29 (Tue, 29 Jul 2025)

  Changed paths:
    M clang/docs/ReleaseNotes.rst
    M clang/lib/Sema/SemaStmtAttr.cpp
    M clang/lib/Sema/SemaTemplateInstantiate.cpp
    M clang/test/Parser/cxx23-assume.cpp
    M clang/test/SemaCXX/cxx23-assume.cpp

  Log Message:
  -----------
  [Clang][Sema] Expression in assumption attribute should be full expression (#150814)

Add missing `ActOnFinishFullExpr` to `BuildCXXAssumeExpr`. We did it
during template instantiation but forgot non-template case.

  Commit: ce86ff105b506aa0f150f676f59ee43abc00a213
      https://github.com/llvm/llvm-project/commit/ce86ff105b506aa0f150f676f59ee43abc00a213
  Author: paperchalice <liujunchang97 at outlook.com>
  Date:   2025-07-29 (Tue, 29 Jul 2025)

  Changed paths:
    M llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp
    M llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
    M llvm/test/CodeGen/AMDGPU/GlobalISel/combine-fma-add-mul-post-legalize.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/combine-fma-add-mul-pre-legalize.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/combine-fma-add-mul.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/combine-fma-unmerge-values.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fptrunc.mir
    M llvm/test/CodeGen/AMDGPU/fptrunc.f16.ll
    M llvm/test/CodeGen/AMDGPU/fptrunc.ll

  Log Message:
  -----------
  [GlobalISel] Remove `UnsafeFPMath` references (#146319)

This is the GlobalISel part to remove `UnsafeFPMath` flag in CodeGen
pipeline.

  Commit: 19ba224fb8a925d095d84836bc9896bf564dfd99
      https://github.com/llvm/llvm-project/commit/19ba224fb8a925d095d84836bc9896bf564dfd99
  Author: Daniil Kovalev <dkovalev at accesssoftek.com>
  Date:   2025-07-29 (Tue, 29 Jul 2025)

  Changed paths:
    M compiler-rt/lib/builtins/crtbegin.c

  Log Message:
  -----------
  [PAC][compiler-rt] Fix init/fini array signing schema (#150691)

When `ptrauth_calls` is present but `ptrauth_init_fini` is not, compiler
emits raw unsigned pointers in `.init_array`/`.fini_array` sections.
Previously, `__do_init`/`__do_fini` pointers, which are explicitly added
to the sections, were implicitly signed (due to the presense of
`ptrauth_calls`), while all the other pointers in the sections were
implicitly added by the compiler and thus non-signed.. As a result, the
sections contained a mix of unsigned function pointers and function
pointers signed with default signing schema.

This patch introduces use of inline assembly for this particular case,
so we can manually specify that we do not want to sign the pointers.

Note that we cannot use `__builtin_ptrauth_strip` for this purpose since
its result is not a constant expression.

  Commit: dbcbdc4da0a9f4627562c305492b4464afe5b467
      https://github.com/llvm/llvm-project/commit/dbcbdc4da0a9f4627562c305492b4464afe5b467
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2025-07-28 (Mon, 28 Jul 2025)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVInstrInfoP.td

  Log Message:
  -----------
  [RISCV] Add IsSignExtendingOpW to P-ext CLS, CLSW, and ABSW instructions. (#151037)

This matches other W instructions. CLS is included since it can only
return 0-64 which has bits [63:31] as zero. This is similar to CLZ.

This doesn't do anything yet since we don't have CodeGen support for P.

  Commit: b103311c1d75bb00845e0160fce76d75fe2377d3
      https://github.com/llvm/llvm-project/commit/b103311c1d75bb00845e0160fce76d75fe2377d3
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2025-07-28 (Mon, 28 Jul 2025)

  Changed paths:
    M llvm/test/TableGen/CompressInstEmitter/suboperands.td
    M llvm/utils/TableGen/CompressInstEmitter.cpp

  Log Message:
  -----------
  [TableGen] Check destination instruction predicates in CompressInstEmitter. (#151061)

In addition to checking the predicate from the CompressPat, also check
the destination instruction. This prevents creating bad instructions if
CompressPat isn't a proper subset of the destination instruction. This
prevents mistakes that we can't catch at compile time.

We are able to verify RegisterClass hierarchy at compile time so don't
have to check the destination register class.

I've added comments for the operand names to make auditing easier.

  Commit: 769b0e6f5c28a09ed5dd7eba2e82457a0064a9e2
      https://github.com/llvm/llvm-project/commit/769b0e6f5c28a09ed5dd7eba2e82457a0064a9e2
  Author: Fangrui Song <i at maskray.me>
  Date:   2025-07-28 (Mon, 28 Jul 2025)

  Changed paths:
    M llvm/lib/MC/MCXCOFFStreamer.cpp
    M llvm/lib/Target/PowerPC/MCTargetDesc/PPCAsmBackend.cpp
    M llvm/lib/Target/PowerPC/MCTargetDesc/PPCFixupKinds.h
    M llvm/lib/Target/PowerPC/MCTargetDesc/PPCXCOFFObjectWriter.cpp

  Log Message:
  -----------
  XCOFF: Simplify R_REF and remove a MCFragment::addFixup use

Simplify the code added by https://reviews.llvm.org/D144356

  Commit: adcad6adc981f83b42551160386d7d01367057b2
      https://github.com/llvm/llvm-project/commit/adcad6adc981f83b42551160386d7d01367057b2
  Author: paperchalice <liujunchang97 at outlook.com>
  Date:   2025-07-29 (Tue, 29 Jul 2025)

  Changed paths:
    M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
    M llvm/lib/Target/AArch64/AArch64ISelLowering.h
    M llvm/lib/Target/AArch64/AArch64InstrInfo.cpp
    M llvm/test/CodeGen/AArch64/aarch64-combine-fmul-fsub.mir
    M llvm/test/CodeGen/AArch64/arm64-fml-combines.ll
    M llvm/test/CodeGen/AArch64/fcsel-zero.ll
    M llvm/test/CodeGen/AArch64/machine-combiner-reassociate.mir
    M llvm/test/CodeGen/AArch64/machine-combiner.ll
    M llvm/test/CodeGen/AArch64/machine-combiner.mir
    M llvm/test/CodeGen/AArch64/sched-past-vector-ldst.ll
    M llvm/test/CodeGen/AArch64/sqrt-fastmath.ll

  Log Message:
  -----------
  [AArch64] Remove `UnsafeFPMath` (#150876)

We should always use fast math flags, remove these global flags
incrementally.
See also
https://discourse.llvm.org/t/rfc-honor-pragmas-with-ffp-contract-fast/80797

  Commit: 96a9e8c9fa4ed8e53c5a13669e9dea16a566c48a
      https://github.com/llvm/llvm-project/commit/96a9e8c9fa4ed8e53c5a13669e9dea16a566c48a
  Author: Fangrui Song <i at maskray.me>
  Date:   2025-07-28 (Mon, 28 Jul 2025)

  Changed paths:
    M llvm/lib/Target/ARM/MCTargetDesc/ARMELFStreamer.cpp

  Log Message:
  -----------
  ARM: Migrate away from MCFragment::addFixup

  Commit: 66fbb6e147e7f37aee52d71f7f6c99c22f699d87
      https://github.com/llvm/llvm-project/commit/66fbb6e147e7f37aee52d71f7f6c99c22f699d87
  Author: Fangrui Song <i at maskray.me>
  Date:   2025-07-28 (Mon, 28 Jul 2025)

  Changed paths:
    M .github/CODEOWNERS
    M clang/docs/ReleaseNotes.rst
    M clang/lib/Sema/SemaStmtAttr.cpp
    M clang/lib/Sema/SemaTemplateInstantiate.cpp
    M clang/test/Parser/cxx23-assume.cpp
    M clang/test/SemaCXX/cxx23-assume.cpp
    M compiler-rt/lib/builtins/crtbegin.c
    M llvm/include/llvm/MC/MCObjectStreamer.h
    M llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp
    M llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
    M llvm/lib/MC/MCWinCOFFStreamer.cpp
    M llvm/lib/MC/MCXCOFFStreamer.cpp
    M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
    M llvm/lib/Target/AArch64/AArch64ISelLowering.h
    M llvm/lib/Target/AArch64/AArch64InstrInfo.cpp
    M llvm/lib/Target/ARM/MCTargetDesc/ARMELFStreamer.cpp
    M llvm/lib/Target/Mips/MCTargetDesc/MipsTargetStreamer.cpp
    M llvm/lib/Target/PowerPC/MCTargetDesc/PPCAsmBackend.cpp
    M llvm/lib/Target/PowerPC/MCTargetDesc/PPCFixupKinds.h
    M llvm/lib/Target/PowerPC/MCTargetDesc/PPCXCOFFObjectWriter.cpp
    M llvm/lib/Target/RISCV/RISCVInstrInfoP.td
    M llvm/test/CodeGen/AArch64/aarch64-combine-fmul-fsub.mir
    M llvm/test/CodeGen/AArch64/arm64-fml-combines.ll
    M llvm/test/CodeGen/AArch64/fcsel-zero.ll
    M llvm/test/CodeGen/AArch64/machine-combiner-reassociate.mir
    M llvm/test/CodeGen/AArch64/machine-combiner.ll
    M llvm/test/CodeGen/AArch64/machine-combiner.mir
    M llvm/test/CodeGen/AArch64/sched-past-vector-ldst.ll
    M llvm/test/CodeGen/AArch64/sqrt-fastmath.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/combine-fma-add-mul-post-legalize.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/combine-fma-add-mul-pre-legalize.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/combine-fma-add-mul.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/combine-fma-unmerge-values.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fptrunc.mir
    M llvm/test/CodeGen/AMDGPU/fptrunc.f16.ll
    M llvm/test/CodeGen/AMDGPU/fptrunc.ll
    M llvm/test/TableGen/CompressInstEmitter/suboperands.td
    M llvm/utils/TableGen/CompressInstEmitter.cpp

  Log Message:
  -----------
  add ensureHeadroom

Created using spr 1.3.5-bogner

Compare: https://github.com/llvm/llvm-project/compare/28e6f7e0fc0c...66fbb6e147e7

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