[all-commits] [llvm/llvm-project] 0d8606: [RISCV] Pass sign-extended value to isInt check in...

[Sudharsan Veeravalli via All-commits]

  Branch: refs/heads/release/21.x
  Home:   https://github.com/llvm/llvm-project
  Commit: 0d8606fc858c1fc85593c6a412ea548045ef890b
      https://github.com/llvm/llvm-project/commit/0d8606fc858c1fc85593c6a412ea548045ef890b
  Author: Sudharsan Veeravalli <quic_svs at quicinc.com>
  Date:   2025-07-28 (Mon, 28 Jul 2025)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
    M llvm/test/CodeGen/RISCV/xqciac.ll

  Log Message:
  -----------
  [RISCV] Pass sign-extended value to isInt check in expandMul (#150211)

In the `isInt` check that was added in #147661 we were passing the
zero-extended `uint64_t` value instead of the sign-extended one.

(cherry picked from commit d3937e2d12648caa49fd80f9520a391fde2f7ba5)



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