[all-commits] [llvm/llvm-project] 6118a2: [AMDGPU] Allocate AVRegClass last (#146606)

[Jeffrey Byrnes via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 6118a254ff9acb4b54a6bdb952c088a792b679af
      https://github.com/llvm/llvm-project/commit/6118a254ff9acb4b54a6bdb952c088a792b679af
  Author: Jeffrey Byrnes <jeffrey.byrnes at amd.com>
  Date:   2025-07-25 (Fri, 25 Jul 2025)

  Changed paths:
    M llvm/lib/Target/AMDGPU/SIRegisterInfo.td
    M llvm/test/CodeGen/AMDGPU/GlobalISel/fp64-atomics-gfx90a.ll
    M llvm/test/CodeGen/AMDGPU/bad-agpr-vgpr-regalloc-priority.mir
    M llvm/test/CodeGen/AMDGPU/bf16.ll
    M llvm/test/CodeGen/AMDGPU/build_vector.ll
    M llvm/test/CodeGen/AMDGPU/fix-crash-valu-hazard.ll
    M llvm/test/CodeGen/AMDGPU/fp64-atomics-gfx90a.ll
    M llvm/test/CodeGen/AMDGPU/infer-addrspace-flat-atomic.ll
    M llvm/test/CodeGen/AMDGPU/inflated-reg-class-snippet-copy-use-after-free.mir
    M llvm/test/CodeGen/AMDGPU/insert_vector_elt.v2bf16.ll
    A llvm/test/CodeGen/AMDGPU/large-avgpr-assign-last.mir
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.iglp.AFLCustomIRMutator.opt.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.dim.gfx90a.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.mfma.gfx90a.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.mfma.gfx942.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.mfma.gfx950.bf16.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.mfma.gfx950.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.mfma.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.mfma.scale.f32.16x16x128.f8f6f4.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.mfma.scale.f32.32x32x64.f8f6f4.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.mfma.xf32.gfx942.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.smfmac.gfx950.ll
    M llvm/test/CodeGen/AMDGPU/packed-fp32.ll
    M llvm/test/CodeGen/AMDGPU/partial-regcopy-and-spill-missed-at-regalloc.ll
    M llvm/test/CodeGen/AMDGPU/ptradd-sdag-optimizations.ll
    M llvm/test/CodeGen/AMDGPU/regalloc-illegal-eviction-assert.ll
    M llvm/test/CodeGen/AMDGPU/scalar_to_vector.v8i16.ll
    M llvm/test/CodeGen/AMDGPU/shufflevector-physreg-copy.ll
    M llvm/test/CodeGen/AMDGPU/spill-agpr.ll
    M llvm/test/CodeGen/AMDGPU/tuple-allocation-failure.ll
    M llvm/test/CodeGen/AMDGPU/undef-handling-crash-in-ra.ll
    M llvm/test/CodeGen/AMDGPU/vector_shuffle.packed.ll
    M llvm/test/CodeGen/AMDGPU/vni8-across-blocks.ll

  Log Message:
  -----------
  [AMDGPU] Allocate AVRegClass last (#146606)

This changes the RC priorities such that AVRegClass is the least
prioritized. These registers are less constrained than the VRegClass and
ARegClass as they can be either agpr or vgpr. Thus, assigning them last
removes unnecessary constraints from VRegClass and ARegClass
assignments, and allows the RA to make smarter decisions about whether
to use vgpr / agpr for AVRegClass.

We only have 5 bits for RC priorities, and we still want to prioritize
larger RCs over smaller ones. Since this new prioritization uses the 5th
bit for AVRegClass vs ARegClass / VRegClass, we only have 4 bits to
encode the size priorities. Previously, each RC with a distinct size,
had a distinct priority. However, this PR groups together multiple sizes
to the same priority. Currently, this will have no effect on
prioritization in practice because we only have one actually defined RC
per group per vector register type.

For example, a register class with 15 or 16 32bit registers will have
the same size priority (14). However, we only have VReg_512 (VReg_480
doesn't exist), so only one actual RC in VRegClass has this priority.
Similarly, we give register class with 17-32+ 32 bit registers a size
priority of 15, but we only have VReg_1024.

The effect of this PR is to prioritize first the vector register type
(VReg & Areg have top priority, then AVReg), with the size of the
register class having second priority.

Passes PSDB.

---------

Co-authored-by: Matt Arsenault <Matthew.Arsenault at amd.com>



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