[all-commits] [llvm/llvm-project] bd91e8: [TableGen] Strengthen check for what operands can ...

[Craig Topper via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: bd91e8a5bd115be1350d4ad3a7100303511b1d15
      https://github.com/llvm/llvm-project/commit/bd91e8a5bd115be1350d4ad3a7100303511b1d15
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2025-07-24 (Thu, 24 Jul 2025)

  Changed paths:
    M llvm/utils/TableGen/CompressInstEmitter.cpp

  Log Message:
  -----------
  [TableGen] Strengthen check for what operands can be an immediate in CompressInstEmitter. (#150568)

Registers can be represented by RegisterOperand, not just RegisterClass.
Instead of trying to block certain classes, only allow Operand.



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