[all-commits] [llvm/llvm-project] 895222: [RISC-V] Update SpacemiT-X60 Vector Integer latenc...

[Mikhail R. Gadelha via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 8952225d88a5ce58a65c8b8695c610f4499d7181
      https://github.com/llvm/llvm-project/commit/8952225d88a5ce58a65c8b8695c610f4499d7181
  Author: Mikhail R. Gadelha <mikhail at igalia.com>
  Date:   2025-07-24 (Thu, 24 Jul 2025)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVSchedSpacemitX60.td
    M llvm/test/tools/llvm-mca/RISCV/SpacemitX60/rvv-arithmetic.s
    M llvm/test/tools/llvm-mca/RISCV/SpacemitX60/rvv-bitwise.s
    M llvm/test/tools/llvm-mca/RISCV/SpacemitX60/rvv-comparison.s
    M llvm/test/tools/llvm-mca/RISCV/SpacemitX60/rvv-conversion.s
    M llvm/test/tools/llvm-mca/RISCV/SpacemitX60/rvv-fma.s
    M llvm/test/tools/llvm-mca/RISCV/SpacemitX60/rvv-minmax.s
    M llvm/test/tools/llvm-mca/RISCV/SpacemitX60/rvv-mul-div.s
    M llvm/test/tools/llvm-mca/RISCV/SpacemitX60/rvv-permutation.s

  Log Message:
  -----------
  [RISC-V] Update SpacemiT-X60 Vector Integer latencies (#149207)

This PR adds hardware-measured latencies for all instructions defined in
Section 11 of the RVV specification: "Vector Integer Arithmetic
Instructions" to the SpacemiT-X60 scheduling model.

The code in this PR was extracted from PR #144564, so it's smaller to
review. I made a few adjustments here and there, and the code is almost
identical; the only change was to add ReleaseAtCycles to all
instructions modified in this patch, except for the vmul, vdiv, and vrem
ones.



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