[all-commits] [llvm/llvm-project] eb0d8f: [libunwind] Fix return type of `DwarfFDECache::fin...
Han-Chung Wang via All-commits
all-commits at lists.llvm.org
Thu Jul 24 10:11:35 PDT 2025
Branch: refs/heads/users/hanhanW/restrict-pack-unpack-folding-patterns
Home: https://github.com/llvm/llvm-project
Commit: eb0d8f9272f7c734cdaf31bc33a18e1619e021e4
https://github.com/llvm/llvm-project/commit/eb0d8f9272f7c734cdaf31bc33a18e1619e021e4
Author: Alex Rønne Petersen <alex at alexrp.com>
Date: 2025-07-23 (Wed, 23 Jul 2025)
Changed paths:
M libunwind/src/UnwindCursor.hpp
Log Message:
-----------
[libunwind] Fix return type of `DwarfFDECache::findFDE()` in definition (#146308)
Needed to resolve this compilation error on some systems:
lib/libunwind/src/UnwindCursor.hpp:153:38: error: return type of
out-of-line definition of 'libunwind::DwarfFDECache::findFDE' differs
from that in the declaration
typename A::pint_t DwarfFDECache<A>::findFDE(pint_t mh, pint_t pc) {
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~^
lib/libunwind/src/libunwind.cpp:31:10: note: in file included from
lib/libunwind/src/libunwind.cpp:31:
#include "UnwindCursor.hpp"
^
lib/libunwind/src/UnwindCursor.hpp:100:17: note: previous declaration is
here
static pint_t findFDE(pint_t mh, pint_t pc);
~~~~~~~^
Commit: a0973de745837d9144b058479cd798c9de5b430f
https://github.com/llvm/llvm-project/commit/a0973de745837d9144b058479cd798c9de5b430f
Author: Stanislav Mekhanoshin <Stanislav.Mekhanoshin at amd.com>
Date: 2025-07-22 (Tue, 22 Jul 2025)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp
M llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.h
M llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
M llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.h
M llvm/lib/Target/AMDGPU/GCNSubtarget.h
M llvm/test/CodeGen/AMDGPU/branch-relaxation-gfx1250.ll
M llvm/test/CodeGen/AMDGPU/flat-saddr-load.ll
M llvm/test/CodeGen/AMDGPU/global-load-xcnt.ll
A llvm/test/CodeGen/AMDGPU/scale-offset-flat.ll
A llvm/test/CodeGen/AMDGPU/scale-offset-global.ll
Log Message:
-----------
[AMDGPU] Select scale_offset for global instructions on gfx1250 (#150107)
Also switches immediate offset to signed for the subtarget.
Commit: 5eecbc018bfdf6f262647de739f35230596a1b8f
https://github.com/llvm/llvm-project/commit/5eecbc018bfdf6f262647de739f35230596a1b8f
Author: Slava "nerfur" Voronzoff <nerfur at gmail.com>
Date: 2025-07-22 (Tue, 22 Jul 2025)
Changed paths:
M clang/lib/Basic/Targets.cpp
M clang/lib/Basic/Targets/OSTargets.h
M clang/lib/Driver/ToolChains/OpenBSD.cpp
M clang/test/Driver/openbsd.c
Log Message:
-----------
Adding Loongarch64 to OpenBSD parts (#149737)
Adding Loongarch64 to OpenBSD parts
Commit: efbe98db0029a97109ec0b4db51f46af1ce8e581
https://github.com/llvm/llvm-project/commit/efbe98db0029a97109ec0b4db51f46af1ce8e581
Author: Andrew Rogers <andrurogerz at gmail.com>
Date: 2025-07-22 (Tue, 22 Jul 2025)
Changed paths:
M llvm/include/llvm/Demangle/DemangleConfig.h
Log Message:
-----------
[llvm] simplify and clean-up DemangleConfig.h (#149163)
## Purpose
Simplify `DEMANGLE_` macro definitions in
`llvm/Demangle/DemangleConfig.h` for clarity/maintainability.
## Overview
* Alias `DEMANGLE_DUMP_METHOD`, `DEMANGLE_FALLTHROUGH`, and
`DEMANGLE_UNREACHABLE` macros to their `LLVM_` counterparts defined in
`llvm/Support/Compiler.h`
* Remove several `DEMANGLE_`-prefixed macros that were only used within
`DemangleConfig.h`
## Background
* It should be safe for the `Demangle` component library to depend on
`Support`, so there is no need for it to maintain copies of macros
defined in `llvm/Support/Compiler.h`.
* Since the canonical copy `llvm/Demangle/ItaniumDemangle.h` lives under
`libcxxabi`, it cannot directly reference the `LLVM_`-prefixed macros so
we define `DEMANGLE_`-prefixed aliases.
## Validation
* Built llvm-project on Windows with `clang-cl` and MSVC `cl`.
* Built llvm-project on Linux with `clang` and `gcc`.
Commit: 2e2a8992f992b185483bb1b120b30eacb30700ca
https://github.com/llvm/llvm-project/commit/2e2a8992f992b185483bb1b120b30eacb30700ca
Author: Philip Reames <preames at rivosinc.com>
Date: 2025-07-22 (Tue, 22 Jul 2025)
Changed paths:
M llvm/lib/CodeGen/InterleavedAccessPass.cpp
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-interleaved-access.ll
Log Message:
-----------
[IA] Remove resriction on constant masks for shuffle lowering (#150098)
The point of this change is simply to show that the constant check was
not required for correctness. The mixed intrinsic and shuffle tests are
added purely to exercise the code. An upcoming change will add support
for shuffle matching in getMask to support non-constant fixed vector
cases.
Commit: c6e560a25bcc3050ff3a02677c8bc1a6f673b36f
https://github.com/llvm/llvm-project/commit/c6e560a25bcc3050ff3a02677c8bc1a6f673b36f
Author: Stanislav Mekhanoshin <Stanislav.Mekhanoshin at amd.com>
Date: 2025-07-22 (Tue, 22 Jul 2025)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp
M llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.h
M llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
M llvm/lib/Target/AMDGPU/FLATInstructions.td
M llvm/test/CodeGen/AMDGPU/GlobalISel/flat-scratch.ll
M llvm/test/CodeGen/AMDGPU/flat-scratch-svs.ll
A llvm/test/CodeGen/AMDGPU/scale-offset-scratch.ll
Log Message:
-----------
[AMDGPU] Select scale_offset for scratch instructions on gfx1250 (#150111)
Commit: 5ecb58058d4578dd96e41fd038cf9d985a77d7aa
https://github.com/llvm/llvm-project/commit/5ecb58058d4578dd96e41fd038cf9d985a77d7aa
Author: Vladimir Vereschaka <vvereschaka at accesssoftek.com>
Date: 2025-07-22 (Tue, 22 Jul 2025)
Changed paths:
M llvm/test/CodeGen/NVPTX/pr126337.ll
Log Message:
-----------
[NVPTX] Fix NVPTX builder test failures.
Fixed broken 'pr126337.ll' NVPTX related test (by #149393)
Commit: b13bca7387a7aad6eaf3fa1c55bd06fe091f65ed
https://github.com/llvm/llvm-project/commit/b13bca7387a7aad6eaf3fa1c55bd06fe091f65ed
Author: Heejin Ahn <aheejin at gmail.com>
Date: 2025-07-22 (Tue, 22 Jul 2025)
Changed paths:
M llvm/lib/Target/WebAssembly/WebAssemblyExplicitLocals.cpp
A llvm/test/CodeGen/WebAssembly/removed-terminator.ll
Log Message:
-----------
[WebAssembly] Unstackify registers with no uses in ExplicitLocals (#149626)
There are cases we end up removing some intructions that use stackified
registers after RegStackify. For example,
```wasm
bb.0:
%0 = ... ;; %0 is stackified
br_if %bb.1, %0
bb.1:
```
In this code, br_if will be removed in CFGSort, so we should unstackify
%0 so that it can be correctly dropped in ExplicitLocals.
Rather than handling this in case-by-case basis, this PR just
unstackifies all stackifies register with no uses in the beginning of
ExplicitLocals, so that they can be correctly dropped.
Fixes #149097.
Commit: 10812eb7c9e9822078a109a98132b829c771c1a8
https://github.com/llvm/llvm-project/commit/10812eb7c9e9822078a109a98132b829c771c1a8
Author: Alex MacLean <amaclean at nvidia.com>
Date: 2025-07-22 (Tue, 22 Jul 2025)
Changed paths:
M llvm/lib/Target/NVPTX/NVPTXISelLowering.cpp
Log Message:
-----------
[NVPTX] Assert PRMT operands are of correct type (NFC) (#150104)
Commit: 681c2ee4dfbf10b3ef74afd1a2c72f844771e602
https://github.com/llvm/llvm-project/commit/681c2ee4dfbf10b3ef74afd1a2c72f844771e602
Author: Justin King <jcking at google.com>
Date: 2025-07-22 (Tue, 22 Jul 2025)
Changed paths:
M compiler-rt/lib/asan/asan_allocator.cpp
M compiler-rt/lib/asan/asan_allocator.h
M compiler-rt/lib/asan/asan_mac.cpp
M compiler-rt/lib/asan/asan_malloc_linux.cpp
M compiler-rt/lib/asan/asan_malloc_mac.cpp
M compiler-rt/lib/asan/asan_malloc_win.cpp
M compiler-rt/lib/asan/asan_new_delete.cpp
M compiler-rt/lib/asan/tests/asan_noinst_test.cpp
Log Message:
-----------
asan: refactor interceptor allocation/deallocation functions (#145087)
Do some refactoring to allocation/deallocation interceptors. Expose
explicit per-alloc_type functions and stop accepting explicit AllocType.
This ensures we do not accidentally mix.
NOTE: This change rejects attempts to call `operator new(<some_size>,
static_cast<std::align_val_t>(0))`.
For https://github.com/llvm/llvm-project/issues/144435
Signed-off-by: Justin King <jcking at google.com>
Commit: 5edb845fcaafd56110670fb2f6eeac22cbb0afff
https://github.com/llvm/llvm-project/commit/5edb845fcaafd56110670fb2f6eeac22cbb0afff
Author: sribee8 <sriya.pratipati at gmail.com>
Date: 2025-07-22 (Tue, 22 Jul 2025)
Changed paths:
M libc/src/__support/wchar/mbrtowc.cpp
M libc/src/wchar/mbtowc.cpp
M libc/test/src/wchar/mbrtowc_test.cpp
Log Message:
-----------
[libc] Fixed mbtowc functions (#150118)
mbrtowc was not handling null destination correctly
---------
Co-authored-by: Sriya Pratipati <sriyap at google.com>
Commit: dbd9eae95a5ad113d4559c07839306bf68f1925c
https://github.com/llvm/llvm-project/commit/dbd9eae95a5ad113d4559c07839306bf68f1925c
Author: Philip Reames <preames at rivosinc.com>
Date: 2025-07-22 (Tue, 22 Jul 2025)
Changed paths:
M llvm/include/llvm/CodeGen/TargetLowering.h
M llvm/lib/CodeGen/InterleavedAccessPass.cpp
M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
M llvm/lib/Target/AArch64/AArch64ISelLowering.h
M llvm/lib/Target/ARM/ARMISelLowering.cpp
M llvm/lib/Target/ARM/ARMISelLowering.h
M llvm/lib/Target/RISCV/RISCVISelLowering.h
M llvm/lib/Target/RISCV/RISCVInterleavedAccess.cpp
M llvm/lib/Target/X86/X86ISelLowering.h
M llvm/lib/Target/X86/X86InterleavedAccess.cpp
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-interleaved-access.ll
Log Message:
-----------
[IA] Support vp.store in lowerinterleavedStore (#149605)
Follow up to 28417e64, and the whole line of work started with 4b81dc7.
This change merges the handling for VPStore - currently in
lowerInterleavedVPStore - into the existing dedicated routine used in
the shuffle lowering path. This removes the last use of the dedicated
lowerInterleavedVPStore and thus we can remove it.
This contains two changes which are functional.
First, like in 28417e64, merging support for vp.store exposes the
strided store optimization for code using vp.store.
Second, it seems the strided store case had a significant missed
optimization. We were performing the strided store at the full unit
strided store type width (i.e. LMUL) rather than reducing it to match
the input width. This became obvious when I tried to use the mask
created by the helper routine as it caused a type incompatibility.
Normally, I'd try not to include an optimization in an API rework, but
structuring the code to both be correct for vp.store and not optimize
the existing case turned out be more involved than seemed worthwhile. I
could pull this part out as a pre-change, but its a bit awkward on it's
own as it turns out to be somewhat of a half step on the possible
optimization; the full optimization is complex with the old code
structure.
---------
Co-authored-by: Craig Topper <craig.topper at sifive.com>
Commit: 2cb1ecb94bb4e7f89494e59d25707fd9787ff98a
https://github.com/llvm/llvm-project/commit/2cb1ecb94bb4e7f89494e59d25707fd9787ff98a
Author: Jonas Devlieghere <jonas at devlieghere.com>
Date: 2025-07-22 (Tue, 22 Jul 2025)
Changed paths:
M lldb/include/lldb/Core/dwarf.h
M lldb/source/Expression/DWARFExpression.cpp
M lldb/source/Plugins/SymbolFile/CTF/SymbolFileCTF.cpp
M lldb/source/Plugins/SymbolFile/DWARF/AppleDWARFIndex.cpp
M lldb/source/Plugins/SymbolFile/DWARF/DWARFASTParser.cpp
M lldb/source/Plugins/SymbolFile/DWARF/DWARFASTParserClang.cpp
M lldb/source/Plugins/SymbolFile/DWARF/DWARFAttribute.cpp
M lldb/source/Plugins/SymbolFile/DWARF/DWARFDIE.cpp
M lldb/source/Plugins/SymbolFile/DWARF/DWARFDebugInfo.cpp
M lldb/source/Plugins/SymbolFile/DWARF/DWARFDebugInfoEntry.cpp
M lldb/source/Plugins/SymbolFile/DWARF/DWARFDebugMacro.cpp
M lldb/source/Plugins/SymbolFile/DWARF/DWARFDeclContext.cpp
M lldb/source/Plugins/SymbolFile/DWARF/DWARFFormValue.cpp
M lldb/source/Plugins/SymbolFile/DWARF/DWARFUnit.cpp
M lldb/source/Plugins/SymbolFile/DWARF/DebugNamesDWARFIndex.cpp
M lldb/source/Plugins/SymbolFile/DWARF/ManualDWARFIndex.cpp
M lldb/source/Plugins/SymbolFile/DWARF/SymbolFileDWARF.cpp
M lldb/source/Plugins/SymbolFile/DWARF/UniqueDWARFASTType.cpp
M lldb/source/Plugins/SymbolFile/PDB/PDBLocationToDWARFExpression.cpp
M lldb/source/Plugins/TypeSystem/Clang/TypeSystemClang.cpp
M lldb/source/Symbol/DWARFCallFrameInfo.cpp
M lldb/source/Symbol/PostfixExpression.cpp
M lldb/unittests/Expression/DWARFExpressionTest.cpp
M lldb/unittests/Symbol/TestTypeSystemClang.cpp
M lldb/unittests/SymbolFile/DWARF/DWARF64UnitTest.cpp
M lldb/unittests/SymbolFile/DWARF/DWARFASTParserClangTests.cpp
M lldb/unittests/SymbolFile/DWARF/DWARFDIETest.cpp
M lldb/unittests/SymbolFile/DWARF/DWARFDebugNamesIndexTest.cpp
M lldb/unittests/SymbolFile/DWARF/SymbolFileDWARFTests.cpp
Log Message:
-----------
[lldb] Eliminate namespace lldb_private::dwarf (NFC) (#150073)
Eliminate the `lldb_private::dwarf` namespace, in favor of using
`llvm::dwarf` directly. The latter is shorter, and this avoids ambiguity
in the ABI plugins that define a `dwarf` namespace inside an anonymous
namespace.
Commit: 796f5512442782c7d37b8008740b3afcac1feb8b
https://github.com/llvm/llvm-project/commit/796f5512442782c7d37b8008740b3afcac1feb8b
Author: Aiden Grossman <aidengrossman at google.com>
Date: 2025-07-22 (Tue, 22 Jul 2025)
Changed paths:
M .github/workflows/premerge.yaml
Log Message:
-----------
[CI] Enable Windows Caching Through Sccache GCS (#150114)
Same as 921287e126465d6850954855ded640f0f78d72fd but for Windows.
Commit: eb554128acef5f814d02d357f10e4666e32a699b
https://github.com/llvm/llvm-project/commit/eb554128acef5f814d02d357f10e4666e32a699b
Author: Krzysztof Drewniak <Krzysztof.Drewniak at amd.com>
Date: 2025-07-22 (Tue, 22 Jul 2025)
Changed paths:
M mlir/lib/Dialect/Arith/Transforms/ExpandOps.cpp
Log Message:
-----------
[mlir][Arith] Prevent IR modification for non-matching pattern (#150103)
The F4E2M1 truncation emulation was expanding or truncating operations
to F32 even when the pattern did not apply, causing non-convergent
rewrites when operating on doubles.
Also, fix a pair of whitespace issues that snuck in.
Commit: c267928700778f01870094009fe6afdce79635a6
https://github.com/llvm/llvm-project/commit/c267928700778f01870094009fe6afdce79635a6
Author: Philip Reames <preames at rivosinc.com>
Date: 2025-07-22 (Tue, 22 Jul 2025)
Changed paths:
M llvm/lib/Target/RISCV/RISCVInterleavedAccess.cpp
Log Message:
-----------
[RISCV][IA] Use getIntNTy routines on builder to simplify code [nfc]
Addressing a suggestion from #149605 consistently throughout file.
Commit: 5ca40fa101df2b75e10c0c260192b653120a9b1d
https://github.com/llvm/llvm-project/commit/5ca40fa101df2b75e10c0c260192b653120a9b1d
Author: yonghong-song <yhs at fb.com>
Date: 2025-07-22 (Tue, 22 Jul 2025)
Changed paths:
M llvm/lib/Target/BPF/BPF.h
Log Message:
-----------
[BPF] Fix build warnings due to a static var in header file (#150128)
Simon Pilgrim ([1]) and Anton reported that the following warning will
appear when building clang compiler:
```
In file included from .../llvm-project/llvm/lib/Target/BPF/BPFASpaceCastSimplifyPass.cpp:9: .../llvm-project/llvm/lib/Target/BPF/BPF.h:25:20: warning: ‘llvm::BPF_TRAP’ defined but not used [-Wunused-variable]
25 | static const char *BPF_TRAP = "__bpf_trap";
| ^~~~~~~~
...
In file included from .../llvm-project/llvm/lib/Target/BPF/MCTargetDesc/BPFInstPrinter.cpp:14:
.../llvm-project/llvm/lib/Target/BPF/BPF.h:25:20: warning: ‘llvm::BPF_TRAP’ defined but not used [-Wunused-variable]
25 | static const char *BPF_TRAP = "__bpf_trap";
| ^~~~~~~~
...
```
Instead of using static const variable, use macro to silence warnings.
[1] https://github.com/llvm/llvm-project/pull/131731
Commit: b2c38f153efe96e4a1497baed9fd25faa1e058c1
https://github.com/llvm/llvm-project/commit/b2c38f153efe96e4a1497baed9fd25faa1e058c1
Author: Craig Topper <craig.topper at sifive.com>
Date: 2025-07-22 (Tue, 22 Jul 2025)
Changed paths:
M llvm/lib/Target/RISCV/RISCVInstrInfoP.td
M llvm/test/MC/RISCV/rv32p-valid.s
M llvm/test/MC/RISCV/rv64p-valid.s
Log Message:
-----------
[RISCV] Correct the immediate swizzling for P-ext plui.h/w. (#149945)
If I'm reading the spec correctly, plui.h/w encode the immediate
differently from pli.h/w. pli.h/w appear to rotate the immediate
left by 1 before encoding while plui.h/w rotates the immediate right
by 1 before encoding.
Since I was splitting the classes, I made the name closer to the
instruction names since the immediate width was ambiguous. I've
added an _i suffix to make it similar to base and Zb* class names.
Commit: fbeb801a718a13ca895ed3db23c6265e93bb9185
https://github.com/llvm/llvm-project/commit/fbeb801a718a13ca895ed3db23c6265e93bb9185
Author: Shilei Tian <i at tianshilei.me>
Date: 2025-07-22 (Tue, 22 Jul 2025)
Changed paths:
M llvm/lib/Target/AMDGPU/VOP3Instructions.td
M llvm/test/CodeGen/AMDGPU/bf16-conversions.ll
M llvm/test/MC/AMDGPU/gfx1250_asm_vop3-fake16.s
M llvm/test/MC/AMDGPU/gfx1250_asm_vop3.s
A llvm/test/MC/AMDGPU/gfx1250_asm_vop3_dpp16-fake16.s
A llvm/test/MC/AMDGPU/gfx1250_asm_vop3_dpp16.s
A llvm/test/MC/AMDGPU/gfx1250_asm_vop3_dpp8-fake16.s
A llvm/test/MC/AMDGPU/gfx1250_asm_vop3_dpp8.s
M llvm/test/MC/Disassembler/AMDGPU/gfx1250_dasm_vop3.txt
A llvm/test/MC/Disassembler/AMDGPU/gfx1250_dasm_vop3_dpp16.txt
A llvm/test/MC/Disassembler/AMDGPU/gfx1250_dasm_vop3_dpp8.txt
Log Message:
-----------
[AMDGPU] Add support for `v_cvt_pk_bf16_f32` on gfx1250 (#150053)
Co-authored-by: Mekhanoshin, Stanislav <Stanislav.Mekhanoshin at amd.com>
Commit: 7fc65569c1d461682504a4552d872bb75b868b4f
https://github.com/llvm/llvm-project/commit/7fc65569c1d461682504a4552d872bb75b868b4f
Author: Shilei Tian <i at tianshilei.me>
Date: 2025-07-22 (Tue, 22 Jul 2025)
Changed paths:
M llvm/lib/Target/AMDGPU/SIISelLowering.cpp
A llvm/test/CodeGen/AMDGPU/fcanonicalize-elimination.bf16.ll
Log Message:
-----------
[AMDGPU] Mark `amdgcn_tanh` as canonicalized (#150059)
Co-authored-by: Mekhanoshin, Stanislav <Stanislav.Mekhanoshin at amd.com>
Commit: c3c72c1de9aece0b98a6f1c62d3883dde1a50fcd
https://github.com/llvm/llvm-project/commit/c3c72c1de9aece0b98a6f1c62d3883dde1a50fcd
Author: Deric C. <cheung.deric at gmail.com>
Date: 2025-07-22 (Tue, 22 Jul 2025)
Changed paths:
M llvm/lib/Target/DirectX/DXILShaderFlags.cpp
M llvm/lib/Target/DirectX/DXILWriter/DXILWriterPass.cpp
A llvm/test/CodeGen/DirectX/ShaderFlags/lifetimes-noint64op.ll
M llvm/test/CodeGen/DirectX/legalize-lifetimes-valver-1.6.ll
A llvm/test/tools/dxil-dis/lifetimes.ll
Log Message:
-----------
[DirectX] Legalize `llvm.lifetime.*` intrinsics in EmbedDXILPass (#150100)
Fixes #147395
This PR:
- Excludes lifetime intrinsics from the Int64Ops shader flags analysis
to match DXC behavior and pass DXIL validation.
- Performs legalization of `llvm.lifetime.*` intrinsics in the
EmbedDXILPass just before invoking the DXILBitcodeWriter.
- After invoking the DXILBitcodeWriter, all lifetime intrinsics and
associated bitcasts are removed from the module to keep the Module
Verifier happy. This is fine since lifetime intrinsics are not needed by
any passes after the EmbedDXILPass.
Commit: d1ca9847575ae94049c4877812cca96b7f3058f0
https://github.com/llvm/llvm-project/commit/d1ca9847575ae94049c4877812cca96b7f3058f0
Author: Valentin Clement (バレンタイン クレメン) <clementval at gmail.com>
Date: 2025-07-23 (Wed, 23 Jul 2025)
Changed paths:
M flang-rt/unittests/Runtime/CUDA/AllocatorCUF.cpp
Log Message:
-----------
[flang][cuda] Fix unittest (#150136)
Commit: 482ec90428017f986edc67644484555a367a624c
https://github.com/llvm/llvm-project/commit/482ec90428017f986edc67644484555a367a624c
Author: aankit-ca <aankit at codeaurora.org>
Date: 2025-07-22 (Tue, 22 Jul 2025)
Changed paths:
M llvm/lib/Target/Hexagon/HexagonInstrFormats.td
R llvm/lib/Target/Hexagon/HexagonInstrFormatsV60.td
M llvm/lib/Target/Hexagon/HexagonInstrFormatsV65.td
R llvm/lib/Target/Hexagon/HexagonIntrinsicsV5.td
R llvm/lib/Target/Hexagon/HexagonIntrinsicsV60.td
R llvm/lib/Target/Hexagon/HexagonMapAsm2IntrinV62.gen.td
Log Message:
-----------
[Hexagon] Remove unused td files (#150109)
Fixes https://github.com/llvm/llvm-project/issues/150094
Commit: dbc41dd5d827a3e13625a66fd2bfa83a8a4dfe83
https://github.com/llvm/llvm-project/commit/dbc41dd5d827a3e13625a66fd2bfa83a8a4dfe83
Author: Volodymyr Sapsai <vsapsai at apple.com>
Date: 2025-07-22 (Tue, 22 Jul 2025)
Changed paths:
M clang/docs/ReleaseNotes.rst
Log Message:
-----------
[clang][deps] Add a release note for fixing crashes in `clang-scan-deps`. (#149857)
Commit: bbbe69f5f3983e919ebceb5f702b248aff495a3a
https://github.com/llvm/llvm-project/commit/bbbe69f5f3983e919ebceb5f702b248aff495a3a
Author: Connector Switch <c8ef at outlook.com>
Date: 2025-07-23 (Wed, 23 Jul 2025)
Changed paths:
M flang/include/flang/Optimizer/Builder/IntrinsicCall.h
M flang/lib/Evaluate/intrinsics.cpp
M flang/lib/Optimizer/Builder/IntrinsicCall.cpp
A flang/test/Lower/Intrinsics/sinpi.f90
Log Message:
-----------
[flang] Implement `sinpi` (#149525)
Commit: 7dc9b433673e28f671894bd22c65f406ba9bea6f
https://github.com/llvm/llvm-project/commit/7dc9b433673e28f671894bd22c65f406ba9bea6f
Author: sivadeilra <arlie.davis at microsoft.com>
Date: 2025-07-22 (Tue, 22 Jul 2025)
Changed paths:
M clang/test/CodeGenCXX/microsoft-abi-eh-disabled.cpp
M clang/test/CodeGenCXX/microsoft-abi-eh-ip2state.cpp
Log Message:
-----------
Fix CI on non-Windows platforms, for #144745 (#150145)
Commit: e0dd22fab19df2c9370fc2e90bcf57eb0cf25bed
https://github.com/llvm/llvm-project/commit/e0dd22fab19df2c9370fc2e90bcf57eb0cf25bed
Author: Wenju He <wenju.he at intel.com>
Date: 2025-07-23 (Wed, 23 Jul 2025)
Changed paths:
M clang/docs/LanguageExtensions.rst
M clang/docs/ReleaseNotes.rst
M clang/include/clang/Basic/Builtins.td
M clang/lib/CodeGen/CGBuiltin.cpp
M clang/lib/Sema/SemaChecking.cpp
A clang/test/CodeGen/builtin-maximumnum-minimumnum.c
M clang/test/Sema/builtins-elementwise-math.c
Log Message:
-----------
[Clang] Add elementwise maximumnum/minimumnum builtin functions (#149775)
Addresses https://github.com/llvm/llvm-project/issues/112164. minimumnum
and maximumnum intrinsics were added in 5bf81e53dbea.
The new built-ins can be used for implementing OpenCL math function fmax
and fmin in #128506.
Commit: 726502d668d12d917411d48d0b2210f8592b23a9
https://github.com/llvm/llvm-project/commit/726502d668d12d917411d48d0b2210f8592b23a9
Author: Daniel Sanders <daniel_l_sanders at apple.com>
Date: 2025-07-22 (Tue, 22 Jul 2025)
Changed paths:
M lldb/include/lldb/lldb-enumerations.h
M lldb/source/Plugins/SymbolFile/DWARF/SymbolFileDWARF.cpp
M lldb/source/Target/Language.cpp
Log Message:
-----------
[lldb] Fix UB cast when encountering DW_LANG_* >= eNumLanguageTypes (#150132)
LanguageType has two kinds of enumerators in it. The first is
DWARF-assigned enumerators which must be consecutive and match DW_LANG
values. The second is the vendor-assigned enumerators which must be
unique and must follow on from the DWARF-assigned values (i.e. the first
one is currently eLanguageTypeMojo + 1) even if that collides with
DWARF-assigned values that lldb is not yet aware of
Only the DWARF-assigned enumerators may be static_cast from DW_LANG
since their values match. The vendor-assigned enumerators must be
explicitly converted since their values do not match. This needs to
handle new languages added to DWARF and not yet implemented in lldb.
This fixes a crash when encountering a DW_LANG value >=
eNumLanguageTypes and wrong behaviour when encountering DW_LANG values
that have not yet been added to LanguageType but happen to coincide with
a vendor-assigned enumerator due to the consecutive values requirement
described above.
Another way to fix the crash is to add the language to LanguageType (and
fill any preceeding gaps in the number space) so that the DW_LANG being
encountered is correctly handled but this just moves the problem to a
new subset of DW_LANG values.
Also fix an unnecessary static-cast from LanguageType to LanguageType.
Commit: 8c26858f1a8bc5796c493f4f720552edbcb09fb4
https://github.com/llvm/llvm-project/commit/8c26858f1a8bc5796c493f4f720552edbcb09fb4
Author: Doug Gregor <dgregor at apple.com>
Date: 2025-07-22 (Tue, 22 Jul 2025)
Changed paths:
M clang/lib/Sema/SemaDecl.cpp
M clang/test/APINotes/Inputs/Headers/SwiftImportAs.apinotes
M clang/test/APINotes/Inputs/Headers/SwiftImportAs.h
M clang/test/APINotes/swift-import-as.cpp
Log Message:
-----------
[API Notes] Attach API notes to forward declarations of tags (#149951)
Forward declarations can still have useful API notes applied to them.
When the use of the tag is not a definition, apply the API notes
immediately.
Fixes rdar://156288588.
Commit: 471e59b858b1d2ee844cb527522e60ed03a1a1dc
https://github.com/llvm/llvm-project/commit/471e59b858b1d2ee844cb527522e60ed03a1a1dc
Author: Prabhu Rajasekaran <prabhukr at google.com>
Date: 2025-07-22 (Tue, 22 Jul 2025)
Changed paths:
M clang/lib/Basic/TargetInfo.cpp
M clang/test/Layout/ms-no-unique-address.cpp
M clang/test/SemaCXX/cxx2a-ms-no-unique-address.cpp
Log Message:
-----------
[clang] Set correct CXXABI for UEFI (#150115)
The target triple x86_64-uefi must be assumed to have Microsft ABI by
default.
Fixes: https://github.com/llvm/llvm-project/issues/150113
Commit: 8f410b491e55f3b91587da926a7a6fee99722df3
https://github.com/llvm/llvm-project/commit/8f410b491e55f3b91587da926a7a6fee99722df3
Author: Leandro Lacerda <leandrolcampos at yahoo.com.br>
Date: 2025-07-22 (Tue, 22 Jul 2025)
Changed paths:
M libc/shared/sign.h
Log Message:
-----------
[libc] Fix incorrect macro usage in shared/sign.h (#150140)
This patch corrects the `using`-declaration in `libc/shared/sign.h`.
The previous change (#150083) incorrectly used the `LIBC_NAMESPACE_DECL`
macro. This is corrected to use `LIBC_NAMESPACE`.
Commit: 8c4fa11dd871ba747867d2e707d643664868837e
https://github.com/llvm/llvm-project/commit/8c4fa11dd871ba747867d2e707d643664868837e
Author: Zack Johnson <zacklj89 at gmail.com>
Date: 2025-07-22 (Tue, 22 Jul 2025)
Changed paths:
M compiler-rt/lib/builtins/CMakeLists.txt
Log Message:
-----------
[compiler-rt][MSVC] Update check to include clang-cl (#150108)
Follow up to #149823 to include `clang-cl` for AArch64 builtins sources.
Commit: efffa42f593739ea7d80a5be301b6f235e44f35a
https://github.com/llvm/llvm-project/commit/efffa42f593739ea7d80a5be301b6f235e44f35a
Author: Joseph Huber <huberjn at outlook.com>
Date: 2025-07-22 (Tue, 22 Jul 2025)
Changed paths:
M clang/lib/Driver/Driver.cpp
Log Message:
-----------
[Clang] Add generated offloading Xarch args to synthesized args (#150142)
Summary:
The synthesized args contains a list of unique pointers, so this should
clean this generated argument up once created.
Commit: a69cddef43f64d5307c0d5f2f01e5176ac05729a
https://github.com/llvm/llvm-project/commit/a69cddef43f64d5307c0d5f2f01e5176ac05729a
Author: Craig Topper <craig.topper at sifive.com>
Date: 2025-07-22 (Tue, 22 Jul 2025)
Changed paths:
M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
M llvm/lib/Target/RISCV/RISCVSelectionDAGInfo.cpp
Log Message:
-----------
[RISCV] Add TUPLE_INSERT and TUPLE_EXTRACT to verifyTargetNode. (#150148)
Verify that the index is an i32 target constant which is what we get
from intrinsic lowering. All other inserts and extracts should be the
same.
Commit: 11fba3591692e339aa2d683c7bcc9eef66b78b88
https://github.com/llvm/llvm-project/commit/11fba3591692e339aa2d683c7bcc9eef66b78b88
Author: Alex MacLean <amaclean at nvidia.com>
Date: 2025-07-22 (Tue, 22 Jul 2025)
Changed paths:
M llvm/lib/Target/NVPTX/NVPTXISelLowering.cpp
M llvm/lib/Target/NVPTX/NVPTXISelLowering.h
M llvm/test/CodeGen/NVPTX/LoadStoreVectorizer.ll
M llvm/test/CodeGen/NVPTX/extractelement.ll
M llvm/test/CodeGen/NVPTX/i8x4-instructions.ll
Log Message:
-----------
[NVPTX] Add SimplifyDemandedBitsForTargetNode for PRMT (#149395)
Commit: 92858528c2db534e4101b7ac6cd263ac7884764d
https://github.com/llvm/llvm-project/commit/92858528c2db534e4101b7ac6cd263ac7884764d
Author: Alan Zhao <ayzhao at google.com>
Date: 2025-07-22 (Tue, 22 Jul 2025)
Changed paths:
M clang/include/clang/Basic/CodeGenOptions.def
M clang/include/clang/Driver/Options.td
M clang/lib/Frontend/CompilerInvocation.cpp
M clang/test/Misc/time-passes.c
M clang/tools/driver/cc1_main.cpp
Log Message:
-----------
[clang][timers][stats] Add a flag to enable timers in the stats file (#149946)
As reported in #138173, enabling `-ftime-report` adds pass timing info
to the stats file if `-stats-file` is specified. This was determined to
be WAI. However, if one intentionally wants to put timer information in
the stats file, using `-ftime-report` may lead to a lot of logspam (that
can't be removed by directing stderr to `/dev/null` as that would also
redirect compiler errors). To address this, this PR adds a flag
`-stats-file-timers` that adds timer data to the stats file without
outputting to stderr.
Commit: 324773e238026c5d4f501213678a89bf411e1509
https://github.com/llvm/llvm-project/commit/324773e238026c5d4f501213678a89bf411e1509
Author: Elvis Wang <elvis.wang at sifive.com>
Date: 2025-07-23 (Wed, 23 Jul 2025)
Changed paths:
M llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
M llvm/test/Analysis/CostModel/RISCV/cast-sat.ll
Log Message:
-----------
[RISCV][TTI] Implement vector costs for `llvm.fpto{u|s}i.sat()`. (#143655)
This patch implement vector costs for `llvm.fptoui.sat()` in RISCV TTI.
Commit: eb0c863c447bf2ad4d35cfde39925a655c060fa5
https://github.com/llvm/llvm-project/commit/eb0c863c447bf2ad4d35cfde39925a655c060fa5
Author: Jordan Rupprecht <rupprecht at google.com>
Date: 2025-07-22 (Tue, 22 Jul 2025)
Changed paths:
M utils/bazel/llvm-project-overlay/libc/BUILD.bazel
Log Message:
-----------
[bazel] Port #147408 (#150154)
Add deps for 45d0750dac528ea7e1fcfda34cc9faca3c5454e6
Commit: 01b47eb86c991f88d3117f494ebd1826fd3ab41e
https://github.com/llvm/llvm-project/commit/01b47eb86c991f88d3117f494ebd1826fd3ab41e
Author: Timm Baeder <tbaeder at redhat.com>
Date: 2025-07-23 (Wed, 23 Jul 2025)
Changed paths:
M clang/lib/AST/ByteCode/Compiler.cpp
M clang/test/AST/ByteCode/unions.cpp
Log Message:
-----------
[clang][bytecode] Only implicitly start lifetime of trivially-default-constructible union members (#149835)
See
https://github.com/llvm/llvm-project/commit/faee39baa87e43f4b746dd77e479268391163658
Commit: 8937b61f21fcd60ab1b19db6e755053364584d18
https://github.com/llvm/llvm-project/commit/8937b61f21fcd60ab1b19db6e755053364584d18
Author: Longsheng Mou <longshengmou at gmail.com>
Date: 2025-07-23 (Wed, 23 Jul 2025)
Changed paths:
M mlir/lib/Dialect/Vector/IR/VectorOps.cpp
M mlir/test/Dialect/Vector/canonicalize.mlir
Log Message:
-----------
[mlir][vector] Fix cast incompatible type bug in `ShuffleOp::fold` (#150037)
This PR uses `dyn_cast` instead of `cast` to avoid a crash when the
constant attribute is not a `DenseElementsAttr`. Fixes #149325.
Commit: 0eafc737248f1232309cef6824a5a95d0747626e
https://github.com/llvm/llvm-project/commit/0eafc737248f1232309cef6824a5a95d0747626e
Author: Andrew Rogers <andrurogerz at gmail.com>
Date: 2025-07-22 (Tue, 22 Jul 2025)
Changed paths:
M llvm/include/llvm/Demangle/DemangleConfig.h
Log Message:
-----------
Revert "[llvm] simplify and clean-up DemangleConfig.h" (#150160)
Reverts llvm/llvm-project#149163 because it introduced a layering
violation.
Support depends on Demangle:
[llvm-project/llvm/lib/Support/Unix/Signals.inc](https://github.com/llvm/llvm-project/blob/324773e238026c5d4f501213678a89bf411e1509/llvm/lib/Support/Unix/Signals.inc#L38)
Line 38 in
[324773e](https://github.com/llvm/llvm-project/commit/324773e238026c5d4f501213678a89bf411e1509)
Commit: 23eef9a7c40f15fcf3cd393e7dc18f48c516bf7e
https://github.com/llvm/llvm-project/commit/23eef9a7c40f15fcf3cd393e7dc18f48c516bf7e
Author: Timm Baeder <tbaeder at redhat.com>
Date: 2025-07-23 (Wed, 23 Jul 2025)
Changed paths:
M clang/lib/AST/ByteCode/Compiler.cpp
M clang/lib/AST/ByteCode/Compiler.h
M clang/lib/AST/ByteCode/Interp.h
M clang/lib/AST/ByteCode/Opcodes.td
M clang/test/AST/ByteCode/unions.cpp
Log Message:
-----------
[clang][bytecode] Activate primitive fields before initializing them (#149963)
The initializer itself might need the field to be active.
Commit: c9714d20350f5895f292794eb82bce4231b9472b
https://github.com/llvm/llvm-project/commit/c9714d20350f5895f292794eb82bce4231b9472b
Author: Craig Topper <craig.topper at sifive.com>
Date: 2025-07-22 (Tue, 22 Jul 2025)
Changed paths:
M llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
M llvm/test/CodeGen/RISCV/xqcisls.ll
M llvm/test/CodeGen/RISCV/xtheadmemidx.ll
Log Message:
-----------
[RISCV] Add profitability checks to SelectAddrRegRegScale. (#150135)
-Only fold if the ADD can be folded into all uses.
-Don't reassociate an ADDI if the shl+add can be a shxadd or similar
instruction.
-Only reassociate a single ADDI. If there are 2 addis it's the same
number of instructions as shl+add. If there are more than 2 that it
would increase instructions over folding the addis into the
loads/stores.
Commit: d8ea88f99a8093c018fa0680900682a562ac93a0
https://github.com/llvm/llvm-project/commit/d8ea88f99a8093c018fa0680900682a562ac93a0
Author: Kazu Hirata <kazu at google.com>
Date: 2025-07-22 (Tue, 22 Jul 2025)
Changed paths:
M llvm/docs/LangRef.rst
Log Message:
-----------
[llvm] Proofread LangRef.rst (#150042)
Commit: 2edc730a687be160965e4b9026a55905f7dfeebe
https://github.com/llvm/llvm-project/commit/2edc730a687be160965e4b9026a55905f7dfeebe
Author: Sameer Sahasrabuddhe <sameer.sahasrabuddhe at amd.com>
Date: 2025-07-23 (Wed, 23 Jul 2025)
Changed paths:
M llvm/test/CodeGen/AMDGPU/memory-legalizer-atomic-insert-end.mir
M llvm/test/CodeGen/AMDGPU/memory-legalizer-multiple-mem-operands-atomics.mir
Log Message:
-----------
[AMDGPU] auto update some tests to prepare for future changes
Commit: 5050a1507116735b5e7b6a6c7f7fcee49a8aa714
https://github.com/llvm/llvm-project/commit/5050a1507116735b5e7b6a6c7f7fcee49a8aa714
Author: Craig Topper <craig.topper at sifive.com>
Date: 2025-07-22 (Tue, 22 Jul 2025)
Changed paths:
M llvm/lib/Target/RISCV/RISCVInstrInfoP.td
Log Message:
-----------
[RISCV] Remove extra spaces from RISCVInstrInfoP.td. NFC
Commit: 7ad1d5bd34754fb909d7b58014372baddf94bfc7
https://github.com/llvm/llvm-project/commit/7ad1d5bd34754fb909d7b58014372baddf94bfc7
Author: Frank Schlimbach <frank.schlimbach at intel.com>
Date: 2025-07-23 (Wed, 23 Jul 2025)
Changed paths:
M mlir/include/mlir/Dialect/Mesh/IR/MeshOps.h
M mlir/include/mlir/Dialect/Mesh/IR/MeshOps.td
M mlir/lib/Dialect/Linalg/Transforms/MeshShardingInterfaceImpl.cpp
M mlir/lib/Dialect/Mesh/IR/MeshOps.cpp
M mlir/lib/Dialect/Mesh/Interfaces/ShardingInterface.cpp
M mlir/lib/Dialect/Mesh/Transforms/Spmdization.cpp
M mlir/test/Dialect/Linalg/mesh-spmdization.mlir
M mlir/test/Dialect/Mesh/forward-sharding-propagation.mlir
M mlir/test/Dialect/Mesh/invalid.mlir
M mlir/test/Dialect/Mesh/ops.mlir
M mlir/test/Dialect/Mesh/resharding-spmdization.mlir
M mlir/test/Dialect/Mesh/sharding-propagation.mlir
M mlir/test/Dialect/Mesh/spmdization.mlir
Log Message:
-----------
[mlir][mesh] removing partial/reduction axes from mesh.sharding (#149805)
[mlir][mesh] Removing partial axes from sharding annotations (discourse 87053)
Commit: 0b3579bedcb2ac608b1a68bf967386c4600554ea
https://github.com/llvm/llvm-project/commit/0b3579bedcb2ac608b1a68bf967386c4600554ea
Author: Fangrui Song <i at maskray.me>
Date: 2025-07-22 (Tue, 22 Jul 2025)
Changed paths:
M llvm/lib/MC/MCMachOStreamer.cpp
Log Message:
-----------
MCMachOStreamer: Call MCObjectStreamer::changeSection
We don't want to emit linker-local label `ltmpN` for addrsig and
cg_profile sections. Make the intention clear to prepare for the pending
refactoring that moves emitLabel from switchSection to changeSection.
Commit: 0f235695709d2505651a55ec7f3c8b7fba2b2dbb
https://github.com/llvm/llvm-project/commit/0f235695709d2505651a55ec7f3c8b7fba2b2dbb
Author: Rainer Orth <ro at gcc.gnu.org>
Date: 2025-07-23 (Wed, 23 Jul 2025)
Changed paths:
M clang/lib/Driver/ToolChains/Arch/Sparc.cpp
M clang/test/Driver/sparc-target-features.c
Log Message:
-----------
[Driver] Default to -mcpu=ultrasparc3 on Solaris/SPARC (#149990)
Prompted by PR #149652, this patch changes the Solaris/SPARC default to
-mcpu, matching both the Oracle Studio 12.6 compilers and GCC 16:
[[PATCH] Default to -mcpu=ultrasparc3 on
Solaris/SPARC](https://gcc.gnu.org/pipermail/gcc-patches/2025-July/690191.html).
This is equivalent to enabling the `vis2` feature.
Tested on `sparcv9-sun-solaris2.11` and `sparc64-unknown-linux-gnu`.
Commit: d385e9d86bce21679ac04b1c6abde0182f1d9e03
https://github.com/llvm/llvm-project/commit/d385e9d86bce21679ac04b1c6abde0182f1d9e03
Author: Changpeng Fang <changpeng.fang at amd.com>
Date: 2025-07-23 (Wed, 23 Jul 2025)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPU.td
M llvm/lib/Target/AMDGPU/GCNSubtarget.h
M llvm/lib/Target/AMDGPU/VOP3PInstructions.td
A llvm/test/CodeGen/AMDGPU/add-max.ll
M llvm/test/CodeGen/AMDGPU/max3.ll
M llvm/test/CodeGen/AMDGPU/min3.ll
A llvm/test/MC/AMDGPU/gfx1250_asm_vop3p.s
M llvm/test/MC/AMDGPU/gfx1250_err.s
A llvm/test/MC/Disassembler/AMDGPU/gfx1250_dasm_vop3p.txt
Log Message:
-----------
AMDGPU: Support V_PK_ADD_{MIN|MAX}_{I|U}16 and V_{MIN|MAX}3_{I|U}16 on gfx1250 (#150155)
Co-authored-by: Stanislav Mekhanoshin <Stanislav.Mekhanoshin at amd.com>
Commit: 073460a2a35c7f0d9aa643e3043fccd62f094c9e
https://github.com/llvm/llvm-project/commit/073460a2a35c7f0d9aa643e3043fccd62f094c9e
Author: Jakub Chlanda <jakub at codeplay.com>
Date: 2025-07-23 (Wed, 23 Jul 2025)
Changed paths:
M clang/include/clang/Driver/ToolChain.h
M clang/lib/Driver/ToolChain.cpp
M clang/lib/Driver/ToolChains/AMDGPU.cpp
M clang/lib/Driver/ToolChains/AMDGPU.h
M clang/lib/Driver/ToolChains/AMDGPUOpenMP.cpp
M clang/lib/Driver/ToolChains/AMDGPUOpenMP.h
M clang/lib/Driver/ToolChains/HIPAMD.cpp
M clang/lib/Driver/ToolChains/HIPAMD.h
M clang/lib/Driver/ToolChains/HIPSPV.cpp
M clang/lib/Driver/ToolChains/HIPSPV.h
M clang/lib/Driver/ToolChains/ROCm.h
Log Message:
-----------
[HIP][Clang][Driver] Move BC preference logic into ROCm detection (#149294)
This patch provides a single point for handling the logic behind
choosing common bitcode libraries. The intention is that the users of
ROCm installation detector will not have to rewrite options handling
code each time the bitcode libraries are queried. This is not too
distant from detectors for other architecture that encapsulate the
similar decision making process, providing cleaner interface. The only
flag left in `getCommonBitcodeLibs` (main point of entry) is
`NeedsASanRT`, this is deliberate, as in order to calculate it we need
to consult `ToolChain`.
Commit: 1e24b53534ed4043562ae32bb16c55b7820a3aed
https://github.com/llvm/llvm-project/commit/1e24b53534ed4043562ae32bb16c55b7820a3aed
Author: Nikita Popov <npopov at redhat.com>
Date: 2025-07-23 (Wed, 23 Jul 2025)
Changed paths:
M llvm/lib/Transforms/InstCombine/InstCombineAddSub.cpp
M llvm/lib/Transforms/InstCombine/InstCombineCompares.cpp
M llvm/lib/Transforms/InstCombine/InstCombineInternal.h
M llvm/test/Transforms/InstCombine/icmp-gep.ll
M llvm/test/Transforms/InstCombine/sub-gep.ll
Log Message:
-----------
[InstCombine] Add limit for expansion of gep chains (#147065)
When converting gep subtraction / comparison to offset subtraction /
comparison, avoid expanding very long multi-use gep chains.
Commit: b59aaf7da7a7121bf0263243fcec6a5fd6db1a2b
https://github.com/llvm/llvm-project/commit/b59aaf7da7a7121bf0263243fcec6a5fd6db1a2b
Author: Nikita Popov <npopov at redhat.com>
Date: 2025-07-23 (Wed, 23 Jul 2025)
Changed paths:
M llvm/include/llvm/Transforms/Utils/MemoryTaggingSupport.h
M llvm/lib/Analysis/StackLifetime.cpp
M llvm/lib/Target/AArch64/AArch64StackTagging.cpp
M llvm/lib/Transforms/Instrumentation/AddressSanitizer.cpp
M llvm/lib/Transforms/Instrumentation/HWAddressSanitizer.cpp
M llvm/lib/Transforms/Instrumentation/MemorySanitizer.cpp
M llvm/lib/Transforms/Scalar/TailRecursionElimination.cpp
M llvm/lib/Transforms/Utils/MemoryTaggingSupport.cpp
Log Message:
-----------
[Sanitizers] Remove handling for lifetimes on non-alloca insts (NFC) (#149994)
After #149310 the pointer argument of lifetime.start/lifetime.end is
guaranteed to be an alloca, so we don't need to go through
findAllocaForValue() anymore, and don't have to have special handling
for the case where it fails.
Commit: 0cfea5b73cadfcf408f3549ff209fba4f56f9138
https://github.com/llvm/llvm-project/commit/0cfea5b73cadfcf408f3549ff209fba4f56f9138
Author: Nikita Popov <npopov at redhat.com>
Date: 2025-07-23 (Wed, 23 Jul 2025)
Changed paths:
M llvm/lib/Bitcode/Reader/BitcodeReader.cpp
Log Message:
-----------
[BitcodeReader] Avoid quadratic complexity in intrinsic upgrade (#150032)
When materializing a function, we'd upgrade all calls to all upgraded
intrinsics. However, this would operate on all calls to the intrinsic
(including previously materialized ones), which leads to quadratic
complexity.
Instead, only upgrade the calls that are in the materialized function.
This fixes a compile-time regression introduced by #149310.
Commit: b7889a65a8e54f2d9c7f578a515a7bf970044bfe
https://github.com/llvm/llvm-project/commit/b7889a65a8e54f2d9c7f578a515a7bf970044bfe
Author: Michael Buch <michaelbuch12 at gmail.com>
Date: 2025-07-23 (Wed, 23 Jul 2025)
Changed paths:
M lldb/source/Plugins/TypeSystem/Clang/TypeSystemClang.cpp
M lldb/source/Symbol/CompilerType.cpp
M lldb/source/ValueObject/ValueObject.cpp
A lldb/test/API/python_api/sbtype_basic_type/Makefile
A lldb/test/API/python_api/sbtype_basic_type/TestSBTypeBasicType.py
A lldb/test/API/python_api/sbtype_basic_type/main.cpp
Log Message:
-----------
[lldb][SBType] GetBasicType to unwrap canonical type (#149112)
`SBType::GetBasicType` fails on typedefs to primitive types. The docs
for `GetBasicType` state:
```
Returns the BasicType value that is most appropriate to this type
```
But, e.g., for `uint64_t` this would currently return
`eBasicTypeInvalid`.
`TypeSystemClang::GetBasicTypeEnumeration` (which is what
`SBType::GetBasicType` uses) doesn't see through typedefs. Inside LLDB
we almost always call `GetBasicTypeEnumeration` on the canonical type.
In the cases we don't I suspect those were just subtle bugs. This patch
gets the canonical type inside of `GetBasicTypeEnumeration` instead.
rdar://155829208
Commit: 7e878aaf23dd559fa491a0bf6168f15f939c5965
https://github.com/llvm/llvm-project/commit/7e878aaf23dd559fa491a0bf6168f15f939c5965
Author: Nikita Popov <npopov at redhat.com>
Date: 2025-07-23 (Wed, 23 Jul 2025)
Changed paths:
M llvm/include/llvm/IR/PatternMatch.h
M llvm/lib/Transforms/InstCombine/InstCombineAddSub.cpp
M llvm/lib/Transforms/InstCombine/InstCombineAndOrXor.cpp
Log Message:
-----------
[PatternMatch] Add support for capture-and-match (NFC) (#149825)
When using PatternMatch, there is a common problem where we want to both
match something against a pattern, but also capture the
value/instruction for various reasons (e.g. to access flags).
Currently the two ways to do that is to either capture using
m_Value/m_Instruction and do a separate match on the result, or to use
the somewhat awkward `m_CombineAnd(m_XYZ, m_Value(V))` pattern.
This PR introduces to add a variant of `m_Value`/`m_Instruction` which
does both a capture and a match. `m_Value(V, m_XYZ)` is basically
equivalent to `m_CombineAnd(m_XYZ, m_Value(V))`.
I've ported two InstCombine files to this pattern as a sample.
Commit: b17f4d3366cd3a6a276b825342c270a839b849db
https://github.com/llvm/llvm-project/commit/b17f4d3366cd3a6a276b825342c270a839b849db
Author: Nikita Popov <npopov at redhat.com>
Date: 2025-07-23 (Wed, 23 Jul 2025)
Changed paths:
M llvm/lib/Transforms/AggressiveInstCombine/AggressiveInstCombine.cpp
M llvm/test/Transforms/AggressiveInstCombine/X86/store-merge.ll
Log Message:
-----------
[AggressiveInstCombine] Use AA during store merge (#149992)
This is a small extension of #147540, resolving one of the FIXMEs.
Instead of bailing out on any instruction that may read/write memory,
use AA to check whether it can alias the stored parts. Do this using a
crude check based on the underlying object only.
This pattern occurs rarely in practice, but at the same time it also doesn't
seem to add any compile-time cost, so it's probably worth handling.
Commit: c3a9e69737c0577cacddff1a2b4cfd2209fb3706
https://github.com/llvm/llvm-project/commit/c3a9e69737c0577cacddff1a2b4cfd2209fb3706
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2025-07-23 (Wed, 23 Jul 2025)
Changed paths:
A llvm/test/CodeGen/RISCV/pr148084.ll
Log Message:
-----------
[RISCV] Add test coverage for #148084
Commit: 0586067cf07bef0f04fd1dc7135a9b773ebaa07a
https://github.com/llvm/llvm-project/commit/0586067cf07bef0f04fd1dc7135a9b773ebaa07a
Author: Michael Kruse <llvm-project at meinersbur.de>
Date: 2025-07-23 (Wed, 23 Jul 2025)
Changed paths:
M flang/lib/Semantics/canonicalize-omp.cpp
Log Message:
-----------
[Flang] Build fix without precompiled headers
The header semantics.h is added implitly in the precompiled headers, but
the build was failing when precompiled headers are disabled (e.g.
using CMAKE_DISABLE_PRECOMPILE_HEADERS=ON):
```
../_src/flang/lib/Semantics/canonicalize-omp.cpp: In constructor ‘Fortran::semantics::CanonicalizationOfOmp::CanonicalizationOfOmp(Fortran::semantics::SemanticsContext&)’:
../_src/flang/lib/Semantics/canonicalize-omp.cpp:31:38: error: invalid use of incomplete type ‘class Fortran::semantics::SemanticsContext’
31 | : context_{context}, messages_{context.messages()} {}
| ^~~~~~~
In file included from ../_src/flang/lib/Semantics/canonicalize-omp.cpp:9:
../_src/flang/lib/Semantics/canonicalize-omp.h:17:7: note: forward declaration of ‘class Fortran::semantics::SemanticsContext’
17 | class SemanticsContext;
| ^~~~~~~~~~~~~~~~
compilation terminated due to -fmax-errors=1.
```
Commit: 39b9891fc9adb23a1894b2aeea1f5577892a40fe
https://github.com/llvm/llvm-project/commit/39b9891fc9adb23a1894b2aeea1f5577892a40fe
Author: Luke Lau <luke at igalia.com>
Date: 2025-07-23 (Wed, 23 Jul 2025)
Changed paths:
M llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
M llvm/lib/Target/RISCV/RISCVInstrInfoXAndes.td
M llvm/lib/Target/RISCV/RISCVInstrInfoXRivos.td
M llvm/lib/Target/RISCV/RISCVInstrInfoXSf.td
M llvm/lib/Target/RISCV/RISCVInstrInfoZvk.td
Log Message:
-----------
[RISCV] Make RISCVVPseudo extend Pseudo. NFC (#149785)
This PR makes RISCVVPseudo extend Pseudo so that we don't forget to
define a record for RISCVVPseudo.
Commit: 6c50e2b2dda185816b3a4d65cef6771dad5113d8
https://github.com/llvm/llvm-project/commit/6c50e2b2dda185816b3a4d65cef6771dad5113d8
Author: Florian Hahn <flo at fhahn.com>
Date: 2025-07-23 (Wed, 23 Jul 2025)
Changed paths:
M llvm/lib/Analysis/ScalarEvolution.cpp
M llvm/test/Analysis/LoopAccessAnalysis/different-strides-safe-dep-due-to-backedge-taken-count.ll
M llvm/test/Analysis/LoopAccessAnalysis/positive-dependence-distance-different-access-sizes.ll
Log Message:
-----------
[SCEV] Don't require NUW at first add when checking A+C1 < (A+C2)<nuw> (#149795)
Relax the NUW requirements for isKnownPredicateViaNoOverflow, if the
second operand (Y) is an ADD. The code only simplifies the condition if
C1 < C2, so if the second ADD is NUW, it doesn't matter whether the
first operand also has the NUW flag, as it cannot wrap if C1 < C2.
https://alive2.llvm.org/ce/z/b3dM7N
PR: https://github.com/llvm/llvm-project/pull/149795
Commit: b1aece90f32c0bb0685e1e79d6dc8e1a147bde37
https://github.com/llvm/llvm-project/commit/b1aece90f32c0bb0685e1e79d6dc8e1a147bde37
Author: Ralf Jung <post at ralfj.de>
Date: 2025-07-23 (Wed, 23 Jul 2025)
Changed paths:
M llvm/docs/LangRef.rst
Log Message:
-----------
LangRef: allocated objects can grow (#141338)
This enables the (reasonably common) pattern of using `mmap` to reserve
but not actually map a wide range of pages, and then only adding in more
pages as memory is actually needed. Effectively, that region of memory
is one big allocated object for LLVM, but crucially, that allocated
object *changes its size*.
Having an allocated object grow seems entirely compatible with what LLVM
optimizations assume, *except* that when LLVM sees an `alloca` or
similar instruction, it will assume that a pointer that has been
`getelementptr inbounds` by more than the size of the allocated object
cannot alias that `alloca`. But for allocated objects that are created
e.g. by `mmap`, where LLVM does not know their size, this cannot happen
anyway.
The other main point to be concerned about is having a `getelementptr
inbounds` that is moved up across an operation that grows an allocated
object: this should be legal as `getelementptr` is freely reorderable.
We achieve that by saying that for allocated objects that change their
size, "inbounds" means "inbounds of their maximal size", not "inbounds
of their current size".
It would be nice to also allow shrinking allocations (e.g. by
`munmap`ing pages at the end), but that is more tricky. Consider an
example like this:
- load 4 bytes from `ptr`
- call some function
- load 1 byte from `ptr`
Right now, LLVM could argue that since `ptr` clearly has not been
deallocated, there must be at least 4 bytes of dereferenceable memory
behind `ptr` after the call. If allocations can shrink, this kind of
reasoning is no longer valid. I don't know if LLVM actually does
reasoning like that -- I think it should not, since I think it should be
possible to have allocations that shrink -- but to remain conservative I
am not proposing that as part of this patch.
Commit: 52737ea6d69d79fb104480d9cd67bf85711fc939
https://github.com/llvm/llvm-project/commit/52737ea6d69d79fb104480d9cd67bf85711fc939
Author: David Spickett <david.spickett at linaro.org>
Date: 2025-07-23 (Wed, 23 Jul 2025)
Changed paths:
M clang/test/CodeGenCXX/microsoft-abi-eh-disabled.cpp
M clang/test/CodeGenCXX/microsoft-abi-eh-ip2state.cpp
Log Message:
-----------
[clang][test] Require x86 target for new Windows EH tests
Added by https://github.com/llvm/llvm-project/pull/144745.
These tests cause Clang -cc1 to generate the option
-x86-asm-syntax=intel, which is only available if you have
included the x86 target.
<<<<<<
1: clang: warning: argument unused during compilation: '-c' [-Wunused-command-line-argument]
label:38'0 X~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ error: no match found
label:38'1 ? possible intended match
2: clang (LLVM option parsing): Unknown command line argument '-x86-asm-syntax=intel'. Try: 'clang (LLVM option parsing) --help'
label:38'0 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
3: clang (LLVM option parsing): Did you mean '--asan-stack=intel'?
label:38'0 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
>>>>>>
Commit: 2a5cd50c469891a0bc918b42785cbf6fd6132a50
https://github.com/llvm/llvm-project/commit/2a5cd50c469891a0bc918b42785cbf6fd6132a50
Author: Zhaoxin Yang <yangzhaoxin at loongson.cn>
Date: 2025-07-23 (Wed, 23 Jul 2025)
Changed paths:
M lld/ELF/Arch/LoongArch.cpp
M lld/test/ELF/loongarch-relax-tlsdesc.s
Log Message:
-----------
[lld][LoongArch] Support relaxation during TLSDESC GD/LD to IE/LE conversion (#123730)
Complement https://github.com/llvm/llvm-project/pull/123715. When
relaxation enable, remove redundant NOPs.
Commit: c295f050633ba4feb3e2ed74811b9c9d7add758d
https://github.com/llvm/llvm-project/commit/c295f050633ba4feb3e2ed74811b9c9d7add758d
Author: Aaron Danen <aaron.danen at gmail.com>
Date: 2025-07-23 (Wed, 23 Jul 2025)
Changed paths:
M clang/lib/Interpreter/Interpreter.cpp
M clang/unittests/Interpreter/InterpreterTest.cpp
Log Message:
-----------
[clang-repl] Improve error message on failed undos (#149396)
Updated error message logic for undo function. Throws different errors
for the case of there being nothing to undo, and for the case of
requesting more undos than there are operations to undo.
Fixes https://github.com/llvm/llvm-project/issues/143668
Commit: 61ce6d70a2fe309d65fe3b7db5b94c17067b9628
https://github.com/llvm/llvm-project/commit/61ce6d70a2fe309d65fe3b7db5b94c17067b9628
Author: Momchil Velikov <momchil.velikov at arm.com>
Date: 2025-07-23 (Wed, 23 Jul 2025)
Changed paths:
M mlir/include/mlir/Dialect/ArmNeon/TransformOps/ArmNeonVectorTransformOps.td
M mlir/include/mlir/Dialect/ArmNeon/Transforms.h
M mlir/include/mlir/Dialect/ArmSVE/Transforms/Transforms.h
M mlir/lib/Conversion/VectorToLLVM/ConvertVectorToLLVMPass.cpp
M mlir/lib/Dialect/ArmNeon/TransformOps/ArmNeonVectorTransformOps.cpp
M mlir/lib/Dialect/ArmNeon/Transforms/CMakeLists.txt
A mlir/lib/Dialect/ArmNeon/Transforms/LowerContractToNeonPatterns.cpp
R mlir/lib/Dialect/ArmNeon/Transforms/LowerContractionToNeonI8MMPattern.cpp
M mlir/lib/Dialect/ArmSVE/TransformOps/ArmSVEVectorTransformOps.cpp
M mlir/lib/Dialect/ArmSVE/Transforms/LowerContractToSVEPatterns.cpp
A mlir/test/Dialect/ArmNeon/vector-bfmmla.mlir
A mlir/test/Integration/Dialect/Vector/CPU/ArmNeon/vector-contract-bfmmla.mlir
M mlir/test/Integration/Dialect/Vector/CPU/ArmNeon/vector-contract-i8mm.mlir
Log Message:
-----------
[MLIR][AArch64] Lower vector.contract to Neon FEAT_BF16 operations (#148198)
This builds upon the framework established by
https://github.com/llvm/llvm-project/pull/149810
to add lowering to `bfmmla`.
Commit: 77b1b956da234d3b3be31c4f04e6af3173b306a1
https://github.com/llvm/llvm-project/commit/77b1b956da234d3b3be31c4f04e6af3173b306a1
Author: Florian Hahn <flo at fhahn.com>
Date: 2025-07-23 (Wed, 23 Jul 2025)
Changed paths:
M llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
M llvm/test/Transforms/LoopVectorize/AArch64/interleave-with-gaps.ll
M llvm/test/Transforms/LoopVectorize/AArch64/partial-reduce-dot-product.ll
Log Message:
-----------
[LV] Also clamp MaxVF by trip count when maximizing vector bandwidth. (#149794)
Also clamp the max VF when maximizing vector bandwidth by the maximum
trip count. Otherwise we may end up choosing a VF for which the vector
loop never executes.
PR: https://github.com/llvm/llvm-project/pull/149794
Commit: 36c37b019b5daae79785e8558d693e6ec42b0ebd
https://github.com/llvm/llvm-project/commit/36c37b019b5daae79785e8558d693e6ec42b0ebd
Author: Kareem Ergawy <kareem.ergawy at amd.com>
Date: 2025-07-23 (Wed, 23 Jul 2025)
Changed paths:
M flang/include/flang/Lower/Support/ReductionProcessor.h
M flang/lib/Lower/Bridge.cpp
M flang/lib/Lower/OpenMP/ClauseProcessor.cpp
M flang/lib/Lower/Support/ReductionProcessor.cpp
A flang/test/Lower/OpenMP/wsloop-reduction-non-intrinsic.f90
Log Message:
-----------
[flang][OpenMP] Restore reduction processor behavior broken by #145837 (#150178)
Fixes #149089 and #149700.
Before #145837, when processing a reduction symbol not yet supported by
OpenMP lowering, the reduction processor would simply skip filling in
the reduction symbols and variables. With #145837, this behvaior was
slightly changed because the reduction symbols are populated before
invoking the reduction processor (this is more convenient to shared the
code with `do concurrent`).
This PR restores the previous behavior.
Commit: 3ab64c5b29643f8d10e5e6286f7a1b9f0f2c0792
https://github.com/llvm/llvm-project/commit/3ab64c5b29643f8d10e5e6286f7a1b9f0f2c0792
Author: Alexandros Lamprineas <alexandros.lamprineas at arm.com>
Date: 2025-07-23 (Wed, 23 Jul 2025)
Changed paths:
M clang/include/clang/Basic/TargetInfo.h
M clang/lib/Basic/Targets/AArch64.cpp
M clang/lib/Basic/Targets/AArch64.h
M clang/lib/Basic/Targets/RISCV.cpp
M clang/lib/Basic/Targets/RISCV.h
M clang/lib/Basic/Targets/X86.cpp
M clang/lib/Basic/Targets/X86.h
M clang/lib/CodeGen/ABIInfo.cpp
M clang/lib/CodeGen/CodeGenModule.cpp
M clang/lib/CodeGen/TargetBuiltins/ARM.cpp
M llvm/include/llvm/Analysis/TargetTransformInfo.h
M llvm/include/llvm/Analysis/TargetTransformInfoImpl.h
M llvm/include/llvm/TargetParser/AArch64TargetParser.h
M llvm/lib/Analysis/TargetTransformInfo.cpp
M llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp
M llvm/lib/Target/AArch64/AArch64TargetTransformInfo.h
M llvm/lib/TargetParser/AArch64TargetParser.cpp
M llvm/lib/Transforms/IPO/GlobalOpt.cpp
Log Message:
-----------
[NFC][Clang][FMV] Make FMV priority data type future proof. (#150079)
FMV priority is the returned value of a polymorphic function. On RISC-V
and X86 targets a 32-bit value is enough. On AArch64 we currently need
64 bits and we will soon exceed that. APInt seems to be a suitable
replacement for uint64_t, presumably with minimal compile time overhead.
It allows bit manipulation, comparison and variable bit width.
Commit: 2726b7fb1c0768bf404a712e5940b64db9fed5e1
https://github.com/llvm/llvm-project/commit/2726b7fb1c0768bf404a712e5940b64db9fed5e1
Author: Ross Brunton <ross at codeplay.com>
Date: 2025-07-23 (Wed, 23 Jul 2025)
Changed paths:
M offload/liboffload/API/Event.td
M offload/liboffload/API/Queue.td
M offload/liboffload/src/OffloadImpl.cpp
M offload/unittests/OffloadAPI/CMakeLists.txt
M offload/unittests/OffloadAPI/common/Fixtures.hpp
M offload/unittests/OffloadAPI/event/olDestroyEvent.cpp
A offload/unittests/OffloadAPI/event/olSyncEvent.cpp
R offload/unittests/OffloadAPI/event/olWaitEvent.cpp
M offload/unittests/OffloadAPI/kernel/olLaunchKernel.cpp
M offload/unittests/OffloadAPI/memory/olMemcpy.cpp
A offload/unittests/OffloadAPI/queue/olSyncQueue.cpp
R offload/unittests/OffloadAPI/queue/olWaitQueue.cpp
Log Message:
-----------
[Offload] Rename olWaitEvent/Queue to olSyncEvent/Queue (#150023)
This more closely matches the nomenclature used by CUDA, AMDGPU and
the plugin interface.
Commit: ffdada166689172e54bd664ff3e43c824c22c69b
https://github.com/llvm/llvm-project/commit/ffdada166689172e54bd664ff3e43c824c22c69b
Author: Utkarsh Saxena <usx at google.com>
Date: 2025-07-23 (Wed, 23 Jul 2025)
Changed paths:
M clang/include/clang/Analysis/Analyses/LifetimeSafety.h
M clang/lib/Analysis/LifetimeSafety.cpp
M clang/unittests/Analysis/LifetimeSafetyTest.cpp
Log Message:
-----------
[LifetimeSafety] Add loan expiry analysis (#148712)
This PR adds the `ExpiredLoansAnalysis` class to track which loans have expired. The analysis uses a dataflow lattice (`ExpiredLattice`) to maintain the set of expired loans at each program point.
This is a very light weight dataflow analysis and is expected to reach fixed point in ~2 iterations.
In principle, this does not need a dataflow analysis but is used for convenience in favour of lean code.
Commit: 5de443a4d37e1b7580f9ccee389572aef7233a85
https://github.com/llvm/llvm-project/commit/5de443a4d37e1b7580f9ccee389572aef7233a85
Author: Andrey Karlov <dein.negativ at gmail.com>
Date: 2025-07-23 (Wed, 23 Jul 2025)
Changed paths:
M clang-tools-extra/clang-tidy/bugprone/UnhandledSelfAssignmentCheck.cpp
M clang-tools-extra/docs/ReleaseNotes.rst
M clang-tools-extra/test/clang-tidy/checkers/bugprone/unhandled-self-assignment.cpp
Log Message:
-----------
[clang-tidy] Make copy-and-swap idiom more general for `bugprone-unhandled-self-assignment` (#147066)
This change enhances the `bugprone-unhandled-self-assignment` checker by
adding an additional matcher that generalizes the copy-and-swap idiom
pattern detection.
# What Changed
Added a new matcher that checks for:
- An instance of the current class being created in operator=
(regardless of constructor arguments)
- That instance being passed to a `swap` function call
# Problem Solved
This fix reduces false positives in PMR-like scenarios where "extended"
constructors are used (typically taking an additional allocator
argument). The checker now properly recognizes copy-and-swap
implementations that use extended copy/move constructors instead of
flagging them as unhandled self-assignment cases.
Fixes #146324
---------
Co-authored-by: Baranov Victor <bar.victor.2002 at gmail.com>
Commit: a7edc95c799c46665ecf4465a4dc7ff4bee3ced0
https://github.com/llvm/llvm-project/commit/a7edc95c799c46665ecf4465a4dc7ff4bee3ced0
Author: Nikita Popov <npopov at redhat.com>
Date: 2025-07-23 (Wed, 23 Jul 2025)
Changed paths:
M llvm/lib/IR/Value.cpp
Log Message:
-----------
[IR] Optimize stripAndAccumulateConstantOffsets() for common case (NFC)
For the common case where we don't have bit width changing address
space casts, we can directly call accumulateConstantOffset() on the
original Offset. Skip the bit width reconciliation logic in that
case.
Commit: 33455825428f9e1b7998a66e228da7f6d483acf8
https://github.com/llvm/llvm-project/commit/33455825428f9e1b7998a66e228da7f6d483acf8
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2025-07-23 (Wed, 23 Jul 2025)
Changed paths:
M llvm/lib/Target/X86/X86ISelLowering.cpp
M llvm/test/CodeGen/X86/vec_extract.ll
Log Message:
-----------
[X86] getTargetConstantBitsFromNode - early-out if the element bitsize doesn't align with the source bitsize (#150184)
As we use getTargetConstantBitsFromNode in a wider variety of places we can't guarantee that all the sources match (or are legal) anymore - better to early out than assert.
Fixes #150117
Commit: 756ac65987b84b7427c25d76f069a04a4a817a5c
https://github.com/llvm/llvm-project/commit/756ac65987b84b7427c25d76f069a04a4a817a5c
Author: Jay Foad <jay.foad at amd.com>
Date: 2025-07-23 (Wed, 23 Jul 2025)
Changed paths:
M llvm/include/llvm/CodeGen/MachineInstrBundle.h
M llvm/include/llvm/Passes/MachinePassRegistry.def
M llvm/lib/CodeGen/MachineInstrBundle.cpp
M llvm/lib/Passes/PassBuilder.cpp
A llvm/test/CodeGen/AMDGPU/finalizebundle.mir
Log Message:
-----------
[CodeGen] Add a pass for testing finalizeBundle (#149813)
This allows for unit testing of finalizeBundle with standard MIR tests
using update_mir_test_checks.py.
Commit: d449d3dc13daff388cbf6a7bb910e0511804eb84
https://github.com/llvm/llvm-project/commit/d449d3dc13daff388cbf6a7bb910e0511804eb84
Author: Jay Foad <jay.foad at amd.com>
Date: 2025-07-23 (Wed, 23 Jul 2025)
Changed paths:
M llvm/docs/ReleaseNotes.md
M llvm/include/llvm/CodeGen/Passes.h
M llvm/include/llvm/InitializePasses.h
M llvm/lib/CodeGen/CodeGen.cpp
M llvm/lib/CodeGen/MachineInstrBundle.cpp
M llvm/lib/Target/AMDGPU/R600ExpandSpecialInstrs.cpp
M llvm/lib/Target/AMDGPU/R600TargetMachine.cpp
Log Message:
-----------
[CodeGen] Remove FinalizeMachineBundles pass (#149806)
Replace its only use in the AMDGPU R600 backend with a call to
finalizeBundles.
Commit: 283fd3f09a3d1fac283a991d2d0f3f9cfbd69e1d
https://github.com/llvm/llvm-project/commit/283fd3f09a3d1fac283a991d2d0f3f9cfbd69e1d
Author: Valentin Clement (バレンタイン クレメン) <clementval at gmail.com>
Date: 2025-07-23 (Wed, 23 Jul 2025)
Changed paths:
M flang-rt/unittests/Runtime/CUDA/AllocatorCUF.cpp
Log Message:
-----------
[flang][cuda] Use get() to get raw pointer (#150205)
Fix issue reported in #150136. `createAllocatable` returns an OwingPtr.
Use `get()` to get the raw pointer has it is done in the
`flang-rt/unittests/Runtime/CUDA/Memory.cpp` tests.
Commit: f992ae4fd16357116b341a1c8291b970787dc462
https://github.com/llvm/llvm-project/commit/f992ae4fd16357116b341a1c8291b970787dc462
Author: Luke Drummond <luke.drummond at codeplay.com>
Date: 2025-07-23 (Wed, 23 Jul 2025)
Changed paths:
M llvm/include/llvm/CodeGen/LinkAllAsmWriterComponents.h
M llvm/include/llvm/CodeGen/LinkAllCodegenComponents.h
M llvm/include/llvm/ExecutionEngine/MCJIT.h
M llvm/include/llvm/LinkAllIR.h
M llvm/include/llvm/LinkAllPasses.h
A llvm/include/llvm/Support/AlwaysTrue.h
M llvm/tools/bugpoint/bugpoint.cpp
M polly/include/polly/LinkAllPasses.h
Log Message:
-----------
Slightly improve the getenv("bar") linking problem
There's been a variation of the following in the code since 2005:
if (unoptimizable_true)
return;
use_this_symbol_to_force_linking(); // unreachable but never removed
Way back in 00d5508496c it was the win32 call `GetCurrentProcess`
but switched to `getenv("bar")` fairly soon after in 63e504ff43. While
that pulled in fewer dependencies and made the code portable, it's a
bit of a weird construct. The environment variable used for the `getenv`
call is "bar", which is particularly weird to see fly past when you run
`ltrace` on a binary linked against LLVM.
In this patch I don't try to replace this construct wholesale - it's
still required for architectural reasons I'm not able to tackle right
now, but I did try and make it slightly less weird and opaque:
- It gives the construct a name
- The environment variable hints where this comes from and that its
value is ignored
Combined, this should be a bit of improvement for the next person who
wonders what LLVM is up to when they trace their process or see
smatterings of `getenv("bar")` dotted around the source.
Commit: 3affbce84342a80a0d869720353786d0db62ff4b
https://github.com/llvm/llvm-project/commit/3affbce84342a80a0d869720353786d0db62ff4b
Author: Corentin Jabot <corentinjabot at gmail.com>
Date: 2025-07-23 (Wed, 23 Jul 2025)
Changed paths:
M clang/lib/Sema/SemaConcept.cpp
M clang/test/SemaTemplate/concepts.cpp
Log Message:
-----------
[Clang] Fix a crash on invalid concept (#150186)
Fixes #149986
Commit: cc380f6e9ba48bfc7fad932d3031141ca88dde53
https://github.com/llvm/llvm-project/commit/cc380f6e9ba48bfc7fad932d3031141ca88dde53
Author: nerix <nerixdev at outlook.de>
Date: 2025-07-23 (Wed, 23 Jul 2025)
Changed paths:
M lldb/source/Plugins/Language/CPlusPlus/CMakeLists.txt
M lldb/source/Plugins/Language/CPlusPlus/CPlusPlusLanguage.cpp
M lldb/source/Plugins/Language/CPlusPlus/MsvcStl.h
A lldb/source/Plugins/Language/CPlusPlus/MsvcStlTree.cpp
M lldb/test/API/functionalities/data-formatter/data-formatter-stl/generic/map/TestDataFormatterStdMap.py
M lldb/test/API/functionalities/data-formatter/data-formatter-stl/generic/map/main.cpp
M lldb/test/API/functionalities/data-formatter/data-formatter-stl/generic/multimap/TestDataFormatterGenericMultiMap.py
M lldb/test/API/functionalities/data-formatter/data-formatter-stl/generic/multiset/TestDataFormatterGenericMultiSet.py
M lldb/test/API/functionalities/data-formatter/data-formatter-stl/generic/set/TestDataFormatterGenericSet.py
M lldb/test/API/functionalities/data-formatter/data-formatter-stl/generic/set/main.cpp
Log Message:
-----------
[LLDB] Add formatters for MSVC STL map-like types (#148385)
This PR adds formatters for `std::map`, `std::set`, `std::multimap`,
`std::multiset` as well as their iterators. It's done in one PR because
the types are essentially the same (a tree) except for their value type.
The iterators are required because of the tests.
`MsvcStlTreeIterSyntheticFrontEnd` is based on the libc++ equivalent. As
opposed to `std::list`, there aren't that many duplicates, so I didn't
create a generic type.
For reference, the tree is implemented in
https://github.com/microsoft/STL/blob/313964b78a8fd5a52e7965e13781f735bcce13c5/stl/inc/xtree.
Towards #24834.
Commit: 411e61db1cfd8d94760416bfa30cd9ad03a8cf3d
https://github.com/llvm/llvm-project/commit/411e61db1cfd8d94760416bfa30cd9ad03a8cf3d
Author: LLVM GN Syncbot <llvmgnsyncbot at gmail.com>
Date: 2025-07-23 (Wed, 23 Jul 2025)
Changed paths:
M llvm/utils/gn/secondary/lldb/source/Plugins/Language/CPlusPlus/BUILD.gn
Log Message:
-----------
[gn build] Port cc380f6e9ba4
Commit: d65cc97ab1bdc61b22e853f3882c9ba267764e53
https://github.com/llvm/llvm-project/commit/d65cc97ab1bdc61b22e853f3882c9ba267764e53
Author: Harald van Dijk <harald.vandijk at codeplay.com>
Date: 2025-07-23 (Wed, 23 Jul 2025)
Changed paths:
M clang/lib/Driver/Driver.cpp
Log Message:
-----------
[Clang] Fix build on 32-bit platforms after #125556
Commit: 114d74e39151ea60afd211a307011f3943ecc9a9
https://github.com/llvm/llvm-project/commit/114d74e39151ea60afd211a307011f3943ecc9a9
Author: Luke Lau <luke at igalia.com>
Date: 2025-07-23 (Wed, 23 Jul 2025)
Changed paths:
M llvm/lib/Transforms/Vectorize/VPlan.h
M llvm/lib/Transforms/Vectorize/VPlanRecipes.cpp
M llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp
Log Message:
-----------
[VPlan] Expand VPBlendRecipes to select instructions. NFC (#133993)
When looking at some EVL tail folded code in SPEC CPU 2017 I noticed we
sometimes have both VPBlendRecipes and select VPInstructions in the same
plan:
EMIT vp<%active.lane.mask> = active lane mask vp<%5>, vp<%3>
EMIT vp<%7> = icmp ...
EMIT vp<%8> = logical-and vp<%active.lane.mask>, vp<%7>
BLEND ir<%8> = ir<%n.015> ir<%foo>/vp<%8>
EMIT vp<%9> = select vp<%active.lane.mask>, ir<%8>, ir<%n.015>
Since a blend will ultimately generate a chain of selects, we could fold
the blend into the select:
EMIT vp<%active.lane.mask> = active lane mask vp<%5>, vp<%3>
EMIT vp<%7> = icmp ...
EMIT vp<%8> = logical-and vp<%active.lane.mask>, vp<%7>
EMIT ir<%8> = select vp<%8>, ir<%foo>, ir<%n.015>
So as a first step, this patch expands blends to a series of select
instructions, which may allow them to be simplified further with other
select instructions.
Commit: bdd638a89763046d9cbd8493c8801ef0898c8555
https://github.com/llvm/llvm-project/commit/bdd638a89763046d9cbd8493c8801ef0898c8555
Author: Nikita Popov <npopov at redhat.com>
Date: 2025-07-23 (Wed, 23 Jul 2025)
Changed paths:
M llvm/lib/Transforms/Utils/Local.cpp
Log Message:
-----------
[Local] Remove handling for lifetime intrinsic on non-alloca (NFC)
After #149310 this is guaranteed to be an alloca.
Commit: 18edd82716a710e40cbed3bd81b8c9e64060c171
https://github.com/llvm/llvm-project/commit/18edd82716a710e40cbed3bd81b8c9e64060c171
Author: Nikita Popov <npopov at redhat.com>
Date: 2025-07-23 (Wed, 23 Jul 2025)
Changed paths:
M llvm/test/Transforms/Inline/inlined-mustprogress-loop-metadata.ll
Log Message:
-----------
[Inline] Regenerate test checks (NFC)
Do not omit check lines for any functions, to avoid spurious diffs
on regeneration. Also update to a newer UTC version which properly
generates the metadata checks.
Commit: 2147e29f641f22822e2b0e10c978b28b06db1aeb
https://github.com/llvm/llvm-project/commit/2147e29f641f22822e2b0e10c978b28b06db1aeb
Author: Jay Foad <jay.foad at amd.com>
Date: 2025-07-23 (Wed, 23 Jul 2025)
Changed paths:
M llvm/test/CodeGen/AMDGPU/wait-xcnt.mir
Log Message:
-----------
[AMDGPU] Tests for unnecessary S_WAIT_XCNT insertion (#145688)
Hardware does an implicit "S_WAIT_XCNT 0" between SMEM and VMEM
instructions, so there will never be outstanding address translations
for both SMEM and VMEM at the same time.
Commit: efa25c4737440887772e6c6ed72029afa0bf05ca
https://github.com/llvm/llvm-project/commit/efa25c4737440887772e6c6ed72029afa0bf05ca
Author: Joseph Huber <huberjn at outlook.com>
Date: 2025-07-23 (Wed, 23 Jul 2025)
Changed paths:
M clang/lib/Driver/Driver.cpp
M clang/test/Driver/hip-phases.hip
Log Message:
-----------
[Clang] Fix new driver device only compilation for `amdgcnspirv` target (#150110)
Summary:
This is broken with the current target because it was not bundling the
output as HIP likes and this would fail if targeting both at the same
time.
Commit: 01e23c3d626c30000820465f029793e44e2062e4
https://github.com/llvm/llvm-project/commit/01e23c3d626c30000820465f029793e44e2062e4
Author: Alex Voicu <alexandru.voicu at amd.com>
Date: 2025-07-23 (Wed, 23 Jul 2025)
Changed paths:
M clang/docs/HIPSupport.rst
M llvm/lib/Transforms/HipStdPar/HipStdPar.cpp
A llvm/test/Transforms/HipStdPar/global-var-indirection-wrong-table-member-0.ll
A llvm/test/Transforms/HipStdPar/global-var-indirection-wrong-table-member-1.ll
A llvm/test/Transforms/HipStdPar/global-var-indirection-wrong-table-member-2.ll
A llvm/test/Transforms/HipStdPar/global-var-indirection-wrong-table-member-count.ll
A llvm/test/Transforms/HipStdPar/global-var-indirection-wrong-table-type.ll
A llvm/test/Transforms/HipStdPar/global-var-indirection.ll
M llvm/test/Transforms/HipStdPar/global-var.ll
Log Message:
-----------
[HIPSTDPAR] Add support for globals (#146813)
This (mostly) removes one of the largest remaining limitations of
`hipstdpar` based algorithm acceleration, by adding support for global
variable usage in offloaded algorithms. It is mean to compose with a run
time component that will live in the support library, and fires iff a
special variable is provided by the latter. In short, things work as
follows:
- We replace uses some global `G` with an indirect access via an
implicitly created anonymous global `F`, which is of pointer type and is
expected to hold the program-wide address of `G`;
- We append 'F', alongside 'G''s name, to an table structure;
- At run-time, the support library uses the table to look-up the
program-wide address of a contained symbol based on its name, and then
stores the address via the paired pointer.
This doesn't handle internal linkage symbols (`static foo` or `namespace
{ foo }`) if they are not unique i.e. if there's a name clash that is
solved by the linker, as the resolution would not be visible. Also,
initially we will only support "true" globals in RDC mode. Things would
be much simpler if we had direct access to the accelerator loader, but
since the expectation is to compose at the HIP RT level we have to jump
through additional hoops.
Commit: 6ed921f9675b7f1bb840f115d81cede4d182cdc2
https://github.com/llvm/llvm-project/commit/6ed921f9675b7f1bb840f115d81cede4d182cdc2
Author: James Newling <james.newling at gmail.com>
Date: 2025-07-23 (Wed, 23 Jul 2025)
Changed paths:
M mlir/lib/Dialect/Arith/Transforms/EmulateUnsupportedFloats.cpp
M mlir/lib/Dialect/NVGPU/TransformOps/NVGPUTransformOps.cpp
M mlir/lib/Dialect/XeGPU/Transforms/XeGPUUnroll.cpp
M mlir/test/Dialect/NVGPU/transform-matmul-to-nvvm.mlir
Log Message:
-----------
Reland "[mlir][vector] Use vector.broadcast in place of vector.splat" (#150138)
This reverts commit 228c45f13dc92546661b6825b7b32c3808b0d2eb (PR
#148937) . Now that #148027 is landed, I think it is safe to "reland"
the original PR: #148028
Commit: 2c6eec219d7791cb083d8add242f0b1d2a0e3160
https://github.com/llvm/llvm-project/commit/2c6eec219d7791cb083d8add242f0b1d2a0e3160
Author: Nikita Popov <npopov at redhat.com>
Date: 2025-07-23 (Wed, 23 Jul 2025)
Changed paths:
M llvm/test/Analysis/MemorySSA/pr39197.ll
M llvm/test/Analysis/MemorySSA/pr43044.ll
M llvm/test/Analysis/MemorySSA/renamephis.ll
M llvm/test/Analysis/ScalarEvolution/add-expr-pointer-operand-sorting.ll
M llvm/test/Analysis/ScalarEvolution/sdiv.ll
M llvm/test/Analysis/ScalarEvolution/srem.ll
M llvm/test/Transforms/Attributor/memory_locations.ll
M llvm/test/Transforms/GVN/lifetime-simple.ll
M llvm/test/Transforms/InferAddressSpaces/AMDGPU/lifetime.ll
M llvm/test/Transforms/InferAddressSpaces/NVPTX/lifetime.ll
M llvm/test/Transforms/Mem2Reg/alloca_addrspace.ll
M llvm/test/Transforms/Mem2Reg/ignore-droppable.ll
M llvm/test/Transforms/Mem2Reg/ignore-lifetime.ll
M llvm/test/Transforms/NewGVN/verify-memoryphi.ll
M llvm/test/Transforms/SROA/alloca-address-space.ll
M llvm/test/Transforms/SROA/basictest.ll
M llvm/test/Transforms/SROA/ignore-droppable.ll
M llvm/test/Transforms/SimplifyCFG/X86/empty-cleanuppad.ll
M llvm/test/Transforms/SimplifyCFG/invoke_unwind_lifetime.ll
Log Message:
-----------
[Tests] Avoid lifetime intrinsics on non-allocas (NFC)
Don't rely on auto-upgrade, instead either remove unnecessary
casts or remove no longer applicable tests.
Commit: 081b74caf5fbfe04abc372c453cb1d6fc8f781a7
https://github.com/llvm/llvm-project/commit/081b74caf5fbfe04abc372c453cb1d6fc8f781a7
Author: Ross Brunton <ross at codeplay.com>
Date: 2025-07-23 (Wed, 23 Jul 2025)
Changed paths:
M offload/liboffload/API/Queue.td
M offload/liboffload/src/OffloadImpl.cpp
M offload/unittests/OffloadAPI/CMakeLists.txt
M offload/unittests/OffloadAPI/device_code/CMakeLists.txt
A offload/unittests/OffloadAPI/device_code/sequence.c
A offload/unittests/OffloadAPI/queue/olWaitEvents.cpp
Log Message:
-----------
[Offload] Add olWaitEvents (#150036)
This function causes a queue to wait until all the provided events have
completed before running any future scheduled work.
Commit: 43db6c5cc1a81b540ddca49bee197895c420ec2d
https://github.com/llvm/llvm-project/commit/43db6c5cc1a81b540ddca49bee197895c420ec2d
Author: Krzysztof Parzyszek <Krzysztof.Parzyszek at amd.com>
Date: 2025-07-23 (Wed, 23 Jul 2025)
Changed paths:
A flang/include/flang/Parser/openmp-utils.h
M flang/lib/Lower/OpenMP/DataSharingProcessor.cpp
M flang/lib/Lower/OpenMP/OpenMP.cpp
M flang/lib/Lower/OpenMP/Utils.cpp
M flang/lib/Lower/OpenMP/Utils.h
Log Message:
-----------
[flang][OpenMP] General utility to get directive id from AST node (#150121)
Fortran::parser::omp::GetOmpDirectiveName(t) will get the
OmpDirectiveName object that corresponds to construct t. That object (an
AST node) contains the enum id and the source information of the
directive.
Replace uses of extractOmpDirective and getOpenMPDirectiveEnum with the
new function.
Commit: 8e072b9d495293b08d939c880d185025751b4269
https://github.com/llvm/llvm-project/commit/8e072b9d495293b08d939c880d185025751b4269
Author: Jake Egan <Jake.egan at ibm.com>
Date: 2025-07-23 (Wed, 23 Jul 2025)
Changed paths:
M compiler-rt/lib/asan/asan_thread.cpp
M compiler-rt/lib/asan/asan_thread.h
M compiler-rt/lib/hwasan/hwasan_thread.cpp
M compiler-rt/lib/hwasan/hwasan_thread.h
M compiler-rt/lib/lsan/lsan_common.cpp
M compiler-rt/lib/lsan/lsan_common.h
M compiler-rt/lib/lsan/lsan_interceptors.cpp
M compiler-rt/lib/lsan/lsan_posix.cpp
M compiler-rt/lib/lsan/lsan_posix.h
M compiler-rt/lib/lsan/lsan_thread.cpp
M compiler-rt/lib/lsan/lsan_thread.h
M compiler-rt/lib/memprof/memprof_thread.cpp
M compiler-rt/lib/memprof/memprof_thread.h
M compiler-rt/lib/sanitizer_common/sanitizer_common.h
M compiler-rt/lib/sanitizer_common/sanitizer_fuchsia.cpp
M compiler-rt/lib/sanitizer_common/sanitizer_haiku.cpp
M compiler-rt/lib/sanitizer_common/sanitizer_internal_defs.h
M compiler-rt/lib/sanitizer_common/sanitizer_linux.cpp
M compiler-rt/lib/sanitizer_common/sanitizer_linux.h
M compiler-rt/lib/sanitizer_common/sanitizer_mac.cpp
M compiler-rt/lib/sanitizer_common/sanitizer_netbsd.cpp
M compiler-rt/lib/sanitizer_common/sanitizer_stoptheworld.h
M compiler-rt/lib/sanitizer_common/sanitizer_stoptheworld_linux_libcdep.cpp
M compiler-rt/lib/sanitizer_common/sanitizer_stoptheworld_mac.cpp
M compiler-rt/lib/sanitizer_common/sanitizer_stoptheworld_netbsd_libcdep.cpp
M compiler-rt/lib/sanitizer_common/sanitizer_stoptheworld_win.cpp
M compiler-rt/lib/sanitizer_common/sanitizer_thread_registry.cpp
M compiler-rt/lib/sanitizer_common/sanitizer_thread_registry.h
M compiler-rt/lib/sanitizer_common/sanitizer_win.cpp
M compiler-rt/lib/sanitizer_common/tests/sanitizer_linux_test.cpp
M compiler-rt/lib/tsan/rtl/tsan_debugging.cpp
M compiler-rt/lib/tsan/rtl/tsan_interceptors_posix.cpp
M compiler-rt/lib/tsan/rtl/tsan_interface.h
M compiler-rt/lib/tsan/rtl/tsan_report.h
M compiler-rt/lib/tsan/rtl/tsan_rtl.h
M compiler-rt/lib/tsan/rtl/tsan_rtl_thread.cpp
M compiler-rt/lib/xray/xray_fdr_controller.h
M compiler-rt/lib/xray/xray_profile_collector.cpp
M compiler-rt/lib/xray/xray_profile_collector.h
Log Message:
-----------
[sanitizer_common][nfc] Rename `tid_t` to avoid conflicting declarations (#149011)
`tid_t` is also defined in the AIX header `/usr/include/sys/types.h`
which is included by system `pthread.h`. The use of `tid_t` by AIX is
conforming according to
[POSIX](https://pubs.opengroup.org/onlinepubs/9799919799/functions/V2_chap02.html):
> Implementations may add symbols to the headers shown in the following
table [ ... ]
Commit: f1bb5de611922bfd76846d0b36a9b92a1dfce80e
https://github.com/llvm/llvm-project/commit/f1bb5de611922bfd76846d0b36a9b92a1dfce80e
Author: Connector Switch <c8ef at outlook.com>
Date: 2025-07-23 (Wed, 23 Jul 2025)
Changed paths:
M flang/include/flang/Optimizer/Builder/IntrinsicCall.h
M flang/lib/Evaluate/intrinsics.cpp
M flang/lib/Optimizer/Builder/IntrinsicCall.cpp
A flang/test/Lower/Intrinsics/tanpi.f90
Log Message:
-----------
[flang] Implement `tanpi` (#149527)
Commit: 594b6f7b3f70b26bf9c7b34d54340797e3e07a1d
https://github.com/llvm/llvm-project/commit/594b6f7b3f70b26bf9c7b34d54340797e3e07a1d
Author: Krishna Pandey <kpandey81930 at gmail.com>
Date: 2025-07-23 (Wed, 23 Jul 2025)
Changed paths:
M libc/src/__support/FPUtil/CMakeLists.txt
M libc/src/__support/FPUtil/bfloat16.h
Log Message:
-----------
[libc][math][c++23] Implement comparison operations operator overloads for BFloat16 (#150087)
Signed-off-by: Krishna Pandey <kpandey81930 at gmail.com>
Commit: fc0a978327215aa8883ae6f18d1e316f3c04520a
https://github.com/llvm/llvm-project/commit/fc0a978327215aa8883ae6f18d1e316f3c04520a
Author: Carlos Seo <carlos.seo at linaro.org>
Date: 2025-07-23 (Wed, 23 Jul 2025)
Changed paths:
M flang/lib/Lower/Bridge.cpp
A flang/test/Lower/assign-statement.f90
Log Message:
-----------
[Flang] Fix ASSIGN statement (#149941)
Handle the case where the assigned variable also has a pointer
attribute.
Fixes #121721
Commit: 8fff238b2c363b036ce9e7bf7abab3acafc87ab2
https://github.com/llvm/llvm-project/commit/8fff238b2c363b036ce9e7bf7abab3acafc87ab2
Author: Maksim Levental <maksim.levental at gmail.com>
Date: 2025-07-23 (Wed, 23 Jul 2025)
Changed paths:
M mlir/lib/Dialect/Tensor/Extensions/MeshShardingExtensions.cpp
M mlir/lib/Dialect/Tensor/IR/TensorOps.cpp
M mlir/lib/Dialect/Tensor/IR/TensorTilingInterfaceImpl.cpp
M mlir/lib/Dialect/Tensor/TransformOps/TensorTransformOps.cpp
M mlir/lib/Dialect/Tensor/Transforms/BufferizableOpInterfaceImpl.cpp
M mlir/lib/Dialect/Tensor/Transforms/EmptyOpPatterns.cpp
M mlir/lib/Dialect/Tensor/Transforms/ExtractSliceFromReshapeUtils.cpp
M mlir/lib/Dialect/Tensor/Transforms/FoldTensorSubsetOps.cpp
M mlir/lib/Dialect/Tensor/Transforms/IndependenceTransforms.cpp
M mlir/lib/Dialect/Tensor/Transforms/ReshapePatterns.cpp
M mlir/lib/Dialect/Tensor/Transforms/RewriteAsConstant.cpp
M mlir/lib/Dialect/Tensor/Transforms/RuntimeOpVerification.cpp
M mlir/lib/Dialect/Tensor/Transforms/SubsetInsertionOpInterfaceImpl.cpp
M mlir/lib/Dialect/Tensor/Transforms/SwapExtractSliceWithProducerPatterns.cpp
M mlir/lib/Dialect/Tensor/Utils/Utils.cpp
Log Message:
-----------
[mlir][NFC] update `mlir/Dialect` create APIs (23/n) (#149930)
See https://github.com/llvm/llvm-project/pull/147168 for more info.
Commit: c1130360902082e5d11fcf9a6a4ddd5dfc1a8ec9
https://github.com/llvm/llvm-project/commit/c1130360902082e5d11fcf9a6a4ddd5dfc1a8ec9
Author: Carlos Seo <carlos.seo at linaro.org>
Date: 2025-07-23 (Wed, 23 Jul 2025)
Changed paths:
M flang/lib/Lower/IO.cpp
A flang/test/Lower/equivalence-3.f
Log Message:
-----------
[Flang] Fix a crash when equivalence and namelist statements are used (#150081)
Check for equivalence when generating namelist descriptors in IO.cpp.
Fixes #124489
Commit: 72df5464eda2c0986200a4bfb30e086ee59fe1d6
https://github.com/llvm/llvm-project/commit/72df5464eda2c0986200a4bfb30e086ee59fe1d6
Author: Krishna Pandey <kpandey81930 at gmail.com>
Date: 2025-07-23 (Wed, 23 Jul 2025)
Changed paths:
M libc/src/__support/FPUtil/bfloat16.h
Log Message:
-----------
[libc][math] Remove constexpr from bfloat16 comparison operations (#150227)
Signed-off-by: Krishna Pandey <kpandey81930 at gmail.com>
Commit: dfd3935e4ff72ab85bab758e297f93e04f8effed
https://github.com/llvm/llvm-project/commit/dfd3935e4ff72ab85bab758e297f93e04f8effed
Author: Petar Avramovic <Petar.Avramovic at amd.com>
Date: 2025-07-23 (Wed, 23 Jul 2025)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp
A llvm/test/CodeGen/AMDGPU/GlobalISel/load-uniform-in-vgpr.ll
Log Message:
-----------
AMDGPU/GlobalISel: Add regbanklegalize rules for uniform global loads (#145909)
Commit: 9563e7a94095c3c55e9598b8b3d86e5ca76b3c29
https://github.com/llvm/llvm-project/commit/9563e7a94095c3c55e9598b8b3d86e5ca76b3c29
Author: Luke Lau <luke at igalia.com>
Date: 2025-07-23 (Wed, 23 Jul 2025)
Changed paths:
M llvm/lib/Transforms/Vectorize/VPlanRecipes.cpp
M llvm/test/Transforms/LoopVectorize/RISCV/vplan-vp-call-intrinsics.ll
M llvm/test/Transforms/LoopVectorize/RISCV/vplan-vp-cast-intrinsics.ll
M llvm/test/Transforms/LoopVectorize/RISCV/vplan-vp-intrinsics-fixed-order-recurrence.ll
M llvm/test/Transforms/LoopVectorize/RISCV/vplan-vp-intrinsics-reduction.ll
M llvm/test/Transforms/LoopVectorize/RISCV/vplan-vp-intrinsics.ll
Log Message:
-----------
[VPlan] Mark VPInstruction::ExplicitVectorLength as single scalar. NFC (#150221)
This allows it to be broadcasted without an explicit
VPInstruction::Broadcast in #150202
Commit: 5ae83b0ccd28e994e29dd1fa00f676eb31aa0a7a
https://github.com/llvm/llvm-project/commit/5ae83b0ccd28e994e29dd1fa00f676eb31aa0a7a
Author: Petar Avramovic <Petar.Avramovic at amd.com>
Date: 2025-07-23 (Wed, 23 Jul 2025)
Changed paths:
A llvm/test/CodeGen/AMDGPU/GlobalISel/readanylane-combines.ll
A llvm/test/CodeGen/AMDGPU/GlobalISel/readanylane-combines.mir
Log Message:
-----------
AMDGPU/GlobalISel: Add tests for missing readanylane combines (#145910)
Commit: 933ba273063f5a4289f0fce109f8f8c17124aa41
https://github.com/llvm/llvm-project/commit/933ba273063f5a4289f0fce109f8f8c17124aa41
Author: Martin Wehking <martin.wehking at arm.com>
Date: 2025-07-23 (Wed, 23 Jul 2025)
Changed paths:
M clang/include/clang/Basic/arm_neon.td
M clang/test/CodeGen/AArch64/neon-intrinsics.c
Log Message:
-----------
Fix implicit vector conversion (#149970)
Previously, the unsigned NEON intrinsic variants of 'vqshrun_high_n' and
'vqrshrun_high_n' were using signed integer types for their first
argument and return values.
These should be unsigned according to developer.arm.com, however.
Adjust the test cases accordingly.
Commit: 4bdef46fe89a3359a2eec631c0f6722a736aae0c
https://github.com/llvm/llvm-project/commit/4bdef46fe89a3359a2eec631c0f6722a736aae0c
Author: Petar Avramovic <Petar.Avramovic at amd.com>
Date: 2025-07-23 (Wed, 23 Jul 2025)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPURegBankLegalize.cpp
M llvm/test/CodeGen/AMDGPU/GlobalISel/readanylane-combines.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/readanylane-combines.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-and-s1.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-anyext.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-trunc.mir
Log Message:
-----------
AMDGPU/GlobalISel: Improve readanylane combines in regbanklegalize (#145911)
Commit: 3564cfa211e932e4a9d19096ead9a241539e6bb9
https://github.com/llvm/llvm-project/commit/3564cfa211e932e4a9d19096ead9a241539e6bb9
Author: Petar Avramovic <Petar.Avramovic at amd.com>
Date: 2025-07-23 (Wed, 23 Jul 2025)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPUGlobalISelUtils.cpp
M llvm/lib/Target/AMDGPU/AMDGPUGlobalISelUtils.h
M llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeHelper.cpp
M llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeHelper.h
M llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp
M llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.h
M llvm/test/CodeGen/AMDGPU/GlobalISel/buffer-schedule.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.make.buffer.rsrc.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.raw.buffer.load.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.raw.ptr.buffer.load.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.struct.buffer.load.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.struct.ptr.buffer.load.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.buffer.load-last-use.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.atomic.buffer.load.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.ptr.atomic.buffer.load.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.atomic.buffer.load.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.atomic.buffer.load.ll
M llvm/test/CodeGen/AMDGPU/swizzle.bit.extract.ll
Log Message:
-----------
AMDGPU/GlobalISel: Add waterfall lowering in regbanklegalize (#145912)
Add rules for G_AMDGPU_BUFFER_LOAD and implement waterfall lowering
for divergent operands that must be sgpr.
Commit: e0a48bb256ffa380d226d9cc50b29196ef587741
https://github.com/llvm/llvm-project/commit/e0a48bb256ffa380d226d9cc50b29196ef587741
Author: lntue <lntue at google.com>
Date: 2025-07-23 (Wed, 23 Jul 2025)
Changed paths:
M libc/src/__support/FPUtil/CMakeLists.txt
M libc/src/__support/FPUtil/rounding_mode.h
Log Message:
-----------
[libc] Make FPUtils' rounding_mode.h functions constexpr. (#149167)
Commit: 5ebbc258d4f410c45f247eb53bc722798b4d4f45
https://github.com/llvm/llvm-project/commit/5ebbc258d4f410c45f247eb53bc722798b4d4f45
Author: Krzysztof Drewniak <Krzysztof.Drewniak at amd.com>
Date: 2025-07-23 (Wed, 23 Jul 2025)
Changed paths:
M mlir/include/mlir/Conversion/ArithToAMDGPU/ArithToAMDGPU.h
M mlir/lib/Conversion/ArithToAMDGPU/ArithToAMDGPU.cpp
Log Message:
-----------
[mlir][ArithToAMDGPU][NFC] Add PatternBenefit (#150091)
Since there may be caseses where these patterns are run alongside the
generic patterns from ArithExpandOps, add a PatternBenefit argument to
allow these architecture-specific patterns to be prioritized.
Commit: d2dedcd11f51c23d8401b7e5eff11b23faea652b
https://github.com/llvm/llvm-project/commit/d2dedcd11f51c23d8401b7e5eff11b23faea652b
Author: AZero13 <gfunni234 at gmail.com>
Date: 2025-07-23 (Wed, 23 Jul 2025)
Changed paths:
M llvm/lib/Transforms/ObjCARC/ARCRuntimeEntryPoints.h
M llvm/lib/Transforms/ObjCARC/ObjCARCOpts.cpp
A llvm/test/Transforms/ObjCARC/test_autorelease_pool.ll
Log Message:
-----------
[ObjCARC] Delete empty autoreleasepools with no autoreleases in them (#144788)
Erase empty autorelease pools that have no autorelease in them
Commit: 38a977d00c4e22f4a2a21e5f577c57df2053872e
https://github.com/llvm/llvm-project/commit/38a977d00c4e22f4a2a21e5f577c57df2053872e
Author: Devajith <devajith.valaparambil.sreeramaswamy at cern.ch>
Date: 2025-07-23 (Wed, 23 Jul 2025)
Changed paths:
M clang/lib/Parse/ParseDecl.cpp
M clang/lib/Sema/SemaDecl.cpp
M clang/test/Interpreter/fail.cpp
Log Message:
-----------
[clang-repl] Always clean up scope and context for TopLevelStmtDecl (#150215)
This fixes an issue introduced by
https://github.com/llvm/llvm-project/pull/84150, where failing to pop
compound scope, function scope info, and decl context after a failed
statement could lead to an inconsistent internal state.
Commit: 06233892e84f96a3b4e05338cd4f6c12b8f5a185
https://github.com/llvm/llvm-project/commit/06233892e84f96a3b4e05338cd4f6c12b8f5a185
Author: Rainer Orth <ro at gcc.gnu.org>
Date: 2025-07-23 (Wed, 23 Jul 2025)
Changed paths:
M clang/lib/Driver/ToolChains/Arch/Sparc.cpp
M clang/test/Driver/sparc-target-features.c
Log Message:
-----------
[Driver] Default to -mv8plus on 32-bit Solaris/SPARC (#150176)
While investigating PR #149990, I noticed that while both the Oracle
Studio compilers and GCC default to `-mv8plus` on 32-bit Solaris/SPARC,
Clang does not.
This patch fixes this by enabling the `v8plus` feature.
Tested on `sparcv9-sun-solaris2.11` and `sparc64-unknown-linux-gnu`.
Commit: 97eec759e69e7534e020b4e2ad1858842eec50ee
https://github.com/llvm/llvm-project/commit/97eec759e69e7534e020b4e2ad1858842eec50ee
Author: Andres-Salamanca <andrealebarbaritos at gmail.com>
Date: 2025-07-23 (Wed, 23 Jul 2025)
Changed paths:
M clang/lib/CIR/CodeGen/CIRGenExprScalar.cpp
M clang/test/CIR/CodeGen/bitfields.c
Log Message:
-----------
[CIR] Add support for binary operations on bitfield members (#149676)
This PR introduces support for binary operations on bitfield members.
Commit: f0f3194e198e05fe9094cfb39a2cf63f3b4a1a7d
https://github.com/llvm/llvm-project/commit/f0f3194e198e05fe9094cfb39a2cf63f3b4a1a7d
Author: Nikita Popov <npopov at redhat.com>
Date: 2025-07-23 (Wed, 23 Jul 2025)
Changed paths:
M llvm/lib/Transforms/InstCombine/InstCombineCompares.cpp
M llvm/test/Transforms/InstCombine/icmp-gep.ll
Log Message:
-----------
[InstCombine] Fold icmp of gep chains (#146714)
This extends https://github.com/llvm/llvm-project/pull/144065 to the
general case of an icmp between two GEP chains that have a common base.
Commit: d5c8303af86f8f4f50320b831c027df4febcd5ea
https://github.com/llvm/llvm-project/commit/d5c8303af86f8f4f50320b831c027df4febcd5ea
Author: nerix <nerixdev at outlook.de>
Date: 2025-07-23 (Wed, 23 Jul 2025)
Changed paths:
M lldb/source/Plugins/Language/CPlusPlus/CMakeLists.txt
M lldb/source/Plugins/Language/CPlusPlus/CPlusPlusLanguage.cpp
M lldb/source/Plugins/Language/CPlusPlus/MsvcStl.h
A lldb/source/Plugins/Language/CPlusPlus/MsvcStlDeque.cpp
M lldb/test/API/functionalities/data-formatter/data-formatter-stl/generic/deque/TestDataFormatterGenericDeque.py
Log Message:
-----------
[LLDB] Add formatters for MSVC STL std::deque (#150097)
This PR adds synthetic children for std::deque from MSVC's STL.
Similar to libstdc++ and libc++, the elements are in a `T**`, so we need
to "subscript" twice. The [NatVis for
deque](https://github.com/microsoft/STL/blob/313964b78a8fd5a52e7965e13781f735bcce13c5/stl/debugger/STL.natvis#L1103-L1112)
uses `_EEN_DS` which contains the block size. We can't access this, but
we can access the [constexpr
`_Block_size`](https://github.com/microsoft/STL/blob/313964b78a8fd5a52e7965e13781f735bcce13c5/stl/inc/deque#L641).
Towards #24834.
Commit: 05f0dd2e917e90579ac49f94b29d12099d489efd
https://github.com/llvm/llvm-project/commit/05f0dd2e917e90579ac49f94b29d12099d489efd
Author: LLVM GN Syncbot <llvmgnsyncbot at gmail.com>
Date: 2025-07-23 (Wed, 23 Jul 2025)
Changed paths:
M llvm/utils/gn/secondary/lldb/source/Plugins/Language/CPlusPlus/BUILD.gn
Log Message:
-----------
[gn build] Port d5c8303af86f
Commit: dbc63f1e3724b6f2348c431dc1216537d9c042e8
https://github.com/llvm/llvm-project/commit/dbc63f1e3724b6f2348c431dc1216537d9c042e8
Author: Alan Li <me at alanli.org>
Date: 2025-07-23 (Wed, 23 Jul 2025)
Changed paths:
M mlir/include/mlir/Dialect/AMDGPU/Transforms/Passes.h
M mlir/include/mlir/Dialect/AMDGPU/Transforms/Passes.td
M mlir/include/mlir/Dialect/MemRef/Utils/MemRefUtils.h
M mlir/lib/Dialect/AMDGPU/Transforms/CMakeLists.txt
A mlir/lib/Dialect/AMDGPU/Transforms/FoldMemRefsOps.cpp
M mlir/lib/Dialect/MemRef/Transforms/FoldMemRefAliasOps.cpp
M mlir/lib/Dialect/MemRef/Utils/MemRefUtils.cpp
A mlir/test/Dialect/AMDGPU/amdgpu-fold-memrefs.mlir
Log Message:
-----------
[AMDGPU] fold `memref.subview/expand_shape/collapse_shape` into `amdgpu.gather_to_lds` (#149851)
This PR adds a new optimization pass to fold
`memref.subview/expand_shape/collapse_shape` ops into consumer
`amdgpu.gather_to_lds` operations.
* Implements a new pass `AmdgpuFoldMemRefOpsPass` with pattern
`FoldMemRefOpsIntoGatherToLDSOp`
* Adds corresponding folding tests
---------
Co-authored-by: Copilot <175728472+Copilot at users.noreply.github.com>
Commit: 7dcd90df454e47a8db17c5ec956222e6b7858945
https://github.com/llvm/llvm-project/commit/7dcd90df454e47a8db17c5ec956222e6b7858945
Author: Mingming Liu <mingmingl at google.com>
Date: 2025-07-23 (Wed, 23 Jul 2025)
Changed paths:
M lld/ELF/Config.h
M lld/ELF/Driver.cpp
M lld/ELF/Writer.cpp
A lld/test/ELF/keep-text-section-prefix.s
Log Message:
-----------
[lld][ELF] Allow `data.rel.ro.hot` and `.data.rel.ro.unlikely` to be RELRO (#148920)
https://discourse.llvm.org/t/rfc-profile-guided-static-data-partitioning/83744
proposes to partition a static data section (like `.data.rel.ro`) into
two sections, one grouping the cold ones and the other grouping the
rest.
lld requires all relro sections to be contiguous. To place
`.data.rel.ro.unlikely` in the middle of all relro sections, this change
proposes to add `.data.rel.ro.unlikely` explicitly as RELRO section.
---------
Co-authored-by: Sam Elliott <quic_aelliott at quicinc.com>
Commit: 97faab7bc279516a31001621203f4ff5a158ed13
https://github.com/llvm/llvm-project/commit/97faab7bc279516a31001621203f4ff5a158ed13
Author: Kazu Hirata <kazu at google.com>
Date: 2025-07-23 (Wed, 23 Jul 2025)
Changed paths:
M flang/lib/Lower/Bridge.cpp
Log Message:
-----------
[flang] Fix a warning
This patch fixes:
flang/lib/Lower/Bridge.cpp:2128:10: error: unused variable 'result'
[-Werror,-Wunused-variable]
Commit: f4d0d124cb5e2157d32aef69d9ab52abcea7fb23
https://github.com/llvm/llvm-project/commit/f4d0d124cb5e2157d32aef69d9ab52abcea7fb23
Author: Juan Manuel Martinez Caamaño <jmartinezcaamao at gmail.com>
Date: 2025-07-23 (Wed, 23 Jul 2025)
Changed paths:
M llvm/test/CodeGen/AMDGPU/amdgpu-attributor-accesslist-offsetbins-out-of-sync.ll
M llvm/test/CodeGen/AMDGPU/attributor-flatscratchinit.ll
M llvm/test/CodeGen/AMDGPU/duplicate-attribute-indirect.ll
M llvm/test/CodeGen/AMDGPU/simple-indirect-call.ll
Log Message:
-----------
[NFC][AMDGPU] Re-run update_test_checks over some tests (#150231)
Commit: a7867fcd94555fb056bcaac66de45d4635da99bf
https://github.com/llvm/llvm-project/commit/a7867fcd94555fb056bcaac66de45d4635da99bf
Author: Jon Roelofs <jonathan_roelofs at apple.com>
Date: 2025-07-23 (Wed, 23 Jul 2025)
Changed paths:
M llvm/lib/FileCheck/FileCheck.cpp
A llvm/test/FileCheck/long-check.txt
Log Message:
-----------
[FileCheck] Limit quadratic partial-match search behavior (#147833)
Commit: 56b263b1bdd1713dd4062bfd3b3a7fce4aad4b2c
https://github.com/llvm/llvm-project/commit/56b263b1bdd1713dd4062bfd3b3a7fce4aad4b2c
Author: Nishant Patel <nishant.b.patel at intel.com>
Date: 2025-07-23 (Wed, 23 Jul 2025)
Changed paths:
M mlir/lib/Dialect/XeGPU/Transforms/XeGPUWgToSgDistribute.cpp
M mlir/test/Dialect/XeGPU/xegpu-wg-to-sg-rr.mlir
M mlir/test/Dialect/XeGPU/xegpu-wg-to-sg.mlir
Log Message:
-----------
[MLIR][XeGPU] Add transformation pattern for vector.broadcast in Wg to Sg pass (#144417)
This PR adds transformation pattern for vector.broadcast op in
xegpu-wg-to-sg-distribute pass
Commit: 10c38943a074033143cfb86118e4e6251db97e9a
https://github.com/llvm/llvm-project/commit/10c38943a074033143cfb86118e4e6251db97e9a
Author: Craig Topper <craig.topper at sifive.com>
Date: 2025-07-23 (Wed, 23 Jul 2025)
Changed paths:
M llvm/lib/Target/RISCV/RISCVInstrInfoP.td
Log Message:
-----------
[RISCV] Refactor the tablegen classes for P-ext shift instructions. NFC (#150175)
-Rename based on element size suffix rather than immediate size.
-Use _ri suffix like we do for shifts in the base ISA.
-Push some common code to the base class.
-Use shamt for the field name to enable more sharing.
-Add funct3 as a parameter which we'll need for right shifts.
Commit: b0434925c98c9a8906afea60a1304c870b1f574a
https://github.com/llvm/llvm-project/commit/b0434925c98c9a8906afea60a1304c870b1f574a
Author: Maksim Levental <maksim.levental at gmail.com>
Date: 2025-07-23 (Wed, 23 Jul 2025)
Changed paths:
M mlir/lib/Conversion/AMDGPUToROCDL/AMDGPUToROCDL.cpp
M mlir/lib/Conversion/AffineToStandard/AffineToStandard.cpp
M mlir/lib/Conversion/ArithToAMDGPU/ArithToAMDGPU.cpp
M mlir/lib/Conversion/ArithToArmSME/ArithToArmSME.cpp
M mlir/lib/Conversion/ArithToEmitC/ArithToEmitC.cpp
M mlir/lib/Conversion/ArithToLLVM/ArithToLLVM.cpp
M mlir/lib/Conversion/ArithToSPIRV/ArithToSPIRV.cpp
M mlir/lib/Conversion/ArmNeon2dToIntr/ArmNeon2dToIntr.cpp
M mlir/lib/Conversion/ArmSMEToLLVM/ArmSMEToLLVM.cpp
M mlir/lib/Conversion/ArmSMEToSCF/ArmSMEToSCF.cpp
M mlir/lib/Conversion/AsyncToLLVM/AsyncToLLVM.cpp
M mlir/lib/Conversion/BufferizationToMemRef/BufferizationToMemRef.cpp
Log Message:
-----------
[mlir][NFC] update `Conversion` create APIs (4/n) (#149879)
See https://github.com/llvm/llvm-project/pull/147168 for more info.
Commit: 4471d59a10f70b502b036f57f4728f2411442fc4
https://github.com/llvm/llvm-project/commit/4471d59a10f70b502b036f57f4728f2411442fc4
Author: Connector Switch <c8ef at outlook.com>
Date: 2025-07-23 (Wed, 23 Jul 2025)
Changed paths:
M flang/include/flang/Optimizer/Builder/IntrinsicCall.h
M flang/lib/Evaluate/intrinsics.cpp
M flang/lib/Optimizer/Builder/IntrinsicCall.cpp
A flang/test/Lower/Intrinsics/acospi.f90
Log Message:
-----------
[flang] Implement `acospi` (#150234)
Commit: 01b23c8d81662ed8383df78c2de0ea100d92d503
https://github.com/llvm/llvm-project/commit/01b23c8d81662ed8383df78c2de0ea100d92d503
Author: Connector Switch <c8ef at outlook.com>
Date: 2025-07-24 (Thu, 24 Jul 2025)
Changed paths:
M flang/include/flang/Optimizer/Builder/IntrinsicCall.h
M flang/lib/Evaluate/intrinsics.cpp
M flang/lib/Optimizer/Builder/IntrinsicCall.cpp
A flang/test/Lower/Intrinsics/asinpi.f90
Log Message:
-----------
[flang] Implement `asinpi` (#150238)
Commit: 90944b85c5331a4cf8b720b5a966bc2c735499d7
https://github.com/llvm/llvm-project/commit/90944b85c5331a4cf8b720b5a966bc2c735499d7
Author: Jianhui Li <jian.hui.li at intel.com>
Date: 2025-07-23 (Wed, 23 Jul 2025)
Changed paths:
M mlir/include/mlir/Dialect/XeGPU/IR/XeGPUOps.td
M mlir/lib/Dialect/XeGPU/IR/XeGPUOps.cpp
M mlir/lib/Dialect/XeGPU/Transforms/XeGPUSubgroupDistribute.cpp
M mlir/lib/Dialect/XeGPU/Transforms/XeGPUUnroll.cpp
M mlir/lib/Dialect/XeGPU/Transforms/XeGPUWgToSgDistribute.cpp
M mlir/test/Dialect/XeGPU/invalid.mlir
M mlir/test/Dialect/XeGPU/ops.mlir
Log Message:
-----------
[MLIR][XeGPU] Add offset operands to load_nd/store_nd/prefetch_nd (#149424)
This PR allows load_nd/store_nd/prefetch_nd to take an additional offset
operand.
It is based on this PR https://github.com/llvm/llvm-project/pull/148335.
Now user can create a nd_tdesc with no offset, and instead set the
offset with the load_nd operation.
Commit: f97adea477069e57422a2446162fe41feb4e1277
https://github.com/llvm/llvm-project/commit/f97adea477069e57422a2446162fe41feb4e1277
Author: Fangrui Song <i at maskray.me>
Date: 2025-07-23 (Wed, 23 Jul 2025)
Changed paths:
M lld/ELF/Writer.cpp
A lld/test/ELF/keep-data-section-prefix.s
R lld/test/ELF/keep-text-section-prefix.s
Log Message:
-----------
ELF: Simplify isRelRoDataSection and rename the text file
PR #148920 was merged before I could share my comments.
* Fix the text filename. There are other minor suggestions, but can be
done in #148985
* Make `isRelRoDataSection` concise, to be consistent with the majority of
helper functions.
Commit: 317dae1a7e5fb81038177d8c58ee1e376d50ea5c
https://github.com/llvm/llvm-project/commit/317dae1a7e5fb81038177d8c58ee1e376d50ea5c
Author: Chao Chen <chao.chen at intel.com>
Date: 2025-07-23 (Wed, 23 Jul 2025)
Changed paths:
M mlir/include/mlir/Dialect/XeGPU/IR/XeGPUOps.td
M mlir/include/mlir/Dialect/XeGPU/IR/XeGPUTypes.td
M mlir/lib/Dialect/XeGPU/IR/XeGPUOps.cpp
M mlir/lib/Dialect/XeGPU/Transforms/XeGPUBlocking.cpp
M mlir/lib/Dialect/XeGPU/Transforms/XeGPUWgToSgDistribute.cpp
M mlir/lib/Dialect/XeGPU/Utils/XeGPUUtils.cpp
M mlir/test/Dialect/XeGPU/invalid.mlir
M mlir/test/Dialect/XeGPU/layout.mlir
M mlir/test/Dialect/XeGPU/xegpu-blocking.mlir
M mlir/test/Dialect/XeGPU/xegpu-wg-to-sg-rr.mlir
Log Message:
-----------
[mlir][xegpu] Add initial skeleton implementation for lowering ConvertLayoutOp (#146176)
This PR adds initial skeleton implementation for lowering
ConvertLayoutOp. It currently only supports cases where SLM is not
needed.
---------
Co-authored-by: Adam Siemieniuk <adam.siemieniuk at intel.com>
Commit: 5daaaf8d7d8dcf97b9d1bd4c697290db3760d406
https://github.com/llvm/llvm-project/commit/5daaaf8d7d8dcf97b9d1bd4c697290db3760d406
Author: Fazlay Rabbi <106703039+mdfazlay at users.noreply.github.com>
Date: 2025-07-23 (Wed, 23 Jul 2025)
Changed paths:
M clang/docs/OpenMPSupport.rst
M clang/docs/ReleaseNotes.rst
M clang/include/clang/Basic/DiagnosticParseKinds.td
M clang/lib/Sema/SemaOpenMP.cpp
M clang/test/OpenMP/declare_variant_clauses_ast_print.cpp
M clang/test/OpenMP/declare_variant_clauses_messages.cpp
Log Message:
-----------
[OpenMP 6.0] Allow only byref arguments with `need_device_addr` modifier on `adjust_args` clause (#149586)
If the need_device_addr adjust-op modifier is present, each list item
that appears in the clause must refer to an argument in the declaration
of the function variant that has a reference type.
Reference:
OpenMP 6.0 [Sec 9.6.2, page 332, line 31-33, adjust_args clause,
Restrictions]
Commit: d174743674fe06833a79d59e9ffcffb3048de524
https://github.com/llvm/llvm-project/commit/d174743674fe06833a79d59e9ffcffb3048de524
Author: Jordan Rupprecht <rupprecht at google.com>
Date: 2025-07-23 (Wed, 23 Jul 2025)
Changed paths:
M utils/bazel/llvm-project-overlay/libc/BUILD.bazel
M utils/bazel/llvm-project-overlay/libc/test/src/__support/FPUtil/BUILD.bazel
M utils/bazel/llvm-project-overlay/libc/utils/MPFRWrapper/BUILD.bazel
Log Message:
-----------
[bazel] Port #150087 and #144983 (#150255)
Commit: ce9d515813f8e1fe8578a3f889abe5325250309e
https://github.com/llvm/llvm-project/commit/ce9d515813f8e1fe8578a3f889abe5325250309e
Author: Jon Roelofs <jonathan_roelofs at apple.com>
Date: 2025-07-23 (Wed, 23 Jul 2025)
Changed paths:
M llvm/test/FileCheck/long-check.txt
Log Message:
-----------
[test][FileCheck] Disable color output in FileCheck test. NFC
This broke a few of the buildbots:
https://github.com/llvm/llvm-project/pull/147833#issuecomment-3109248167
Commit: 9cb5c00bf7c69fd4da5afea7ee08c5d89bee3b5e
https://github.com/llvm/llvm-project/commit/9cb5c00bf7c69fd4da5afea7ee08c5d89bee3b5e
Author: Alan Li <me at alanli.org>
Date: 2025-07-23 (Wed, 23 Jul 2025)
Changed paths:
M mlir/include/mlir/Dialect/AMDGPU/Transforms/Passes.h
M mlir/include/mlir/Dialect/AMDGPU/Transforms/Passes.td
M mlir/include/mlir/Dialect/MemRef/Utils/MemRefUtils.h
M mlir/lib/Dialect/AMDGPU/Transforms/CMakeLists.txt
R mlir/lib/Dialect/AMDGPU/Transforms/FoldMemRefsOps.cpp
M mlir/lib/Dialect/MemRef/Transforms/FoldMemRefAliasOps.cpp
M mlir/lib/Dialect/MemRef/Utils/MemRefUtils.cpp
R mlir/test/Dialect/AMDGPU/amdgpu-fold-memrefs.mlir
Log Message:
-----------
Revert "[AMDGPU] fold `memref.subview/expand_shape/collapse_shape` in… (#150256)
…to `amdgpu.gather_to_lds` (#149851)"
This reverts commit dbc63f1e3724b6f2348c431dc1216537d9c042e8.
Having build deps issue.
Commit: e3b79afa673a029b3b6f546ba59d2998f9cff681
https://github.com/llvm/llvm-project/commit/e3b79afa673a029b3b6f546ba59d2998f9cff681
Author: Hood Chatham <roberthoodchatham at gmail.com>
Date: 2025-07-23 (Wed, 23 Jul 2025)
Changed paths:
M llvm/lib/Target/WebAssembly/WebAssemblyISelDAGToDAG.cpp
M llvm/test/CodeGen/WebAssembly/ref-test-func.ll
Log Message:
-----------
[WebAssembly,llvm] Fix buildbot problems with llvm.wasm.ref.test.func (#150116)
PR #147486 broke the sanitizer and expensive-checks buildbot.
These captures were needed when toWasmValType emitted a diagnostic but
are no longer needed since we changed it to an assertion failure. This
removes the unneeded captures and should fix the sanitizer-buildbot.
I also fixed the codegen in the wasm64 target: table.get requires an i32
but in wasm64 the function pointer is an i64. We need an additional
`i32.wrap_i64` to convert it. I also added `-verify-machineinstrs` to
the tests so that the test suite validates this fix.
Finally, I noticed that #150201 uses a feature of the intrinsic that is
not covered by the tests, namely `ptr` arguments. So I added one
additional test case to ensure that it works properly.
cc @dschuff
Commit: 30a6644ffbc479a9a75f840e48dc42aa29f377e5
https://github.com/llvm/llvm-project/commit/30a6644ffbc479a9a75f840e48dc42aa29f377e5
Author: Qinkun Bao <qinkun at google.com>
Date: 2025-07-23 (Wed, 23 Jul 2025)
Changed paths:
M clang/test/Interpreter/pretty-print.cpp
Log Message:
-----------
[Interp] Mark the test unsupported with Asan (#150242)
See https://github.com/llvm/llvm-project/pull/148701
The test is very flaky with asan
Fail: https://lab.llvm.org/buildbot/#/builders/52/builds/9890
Pass: https://lab.llvm.org/buildbot/#/builders/52/builds/9891
Fail again: https://lab.llvm.org/buildbot/#/builders/52/builds/9892
Commit: 108023b7b16297291553650ea6aea809bd7eb78b
https://github.com/llvm/llvm-project/commit/108023b7b16297291553650ea6aea809bd7eb78b
Author: Jon Roelofs <jonathan_roelofs at apple.com>
Date: 2025-07-23 (Wed, 23 Jul 2025)
Changed paths:
M llvm/test/FileCheck/long-check.txt
Log Message:
-----------
Revert "[test][FileCheck] Disable color output in FileCheck test. NFC"
This reverts commit ce9d515813f8e1fe8578a3f889abe5325250309e.
I applied it to the wrong FileCheck invocation.
Commit: 9a12037c573e884b8f027654b56a6151bd5c0a56
https://github.com/llvm/llvm-project/commit/9a12037c573e884b8f027654b56a6151bd5c0a56
Author: Jon Roelofs <jonathan_roelofs at apple.com>
Date: 2025-07-23 (Wed, 23 Jul 2025)
Changed paths:
M llvm/test/FileCheck/long-check.txt
Log Message:
-----------
[test][FileCheck] Disable color output in FileCheck test. NFC
This broke a few of the buildbots:
https://github.com/llvm/llvm-project/pull/147833#issuecomment-3109248167
Second try, applied it to the wrong FileCheck invocation last time:
https://github.com/llvm/llvm-project/pull/147833#issuecomment-3109427750
Commit: 7baf4bdd164cad61f8f3e34ed833a695c4033250
https://github.com/llvm/llvm-project/commit/7baf4bdd164cad61f8f3e34ed833a695c4033250
Author: Prabhu Rajasekaran <prabhukr at google.com>
Date: 2025-07-23 (Wed, 23 Jul 2025)
Changed paths:
M llvm/include/llvm/CodeGen/CommandFlags.h
M llvm/include/llvm/CodeGen/MIRYamlMapping.h
M llvm/include/llvm/CodeGen/MachineFunction.h
M llvm/include/llvm/Target/TargetOptions.h
M llvm/lib/CodeGen/CommandFlags.cpp
M llvm/lib/CodeGen/MIRParser/MIRParser.cpp
M llvm/lib/CodeGen/MIRPrinter.cpp
M llvm/lib/CodeGen/MachineFunction.cpp
A llvm/test/CodeGen/MIR/X86/call-site-info-ambiguous-indirect-call-typeid.mir
A llvm/test/CodeGen/MIR/X86/call-site-info-direct-calls-typeid.mir
A llvm/test/CodeGen/MIR/X86/call-site-info-typeid.mir
Log Message:
-----------
[llvm] Add CalleeTypeIds field to CallSiteInfo
Introducing `EnableCallGraphSection` target option to add
CalleeTypeIds field in CallSiteInfo. Read the callee type ids
in and out by the MIR parser/printer.
Reviewers: ilovepi
Reviewed By: ilovepi
Pull Request: https://github.com/llvm/llvm-project/pull/87574
Commit: 8ef0c50ecac8f1e707c02bee855f43eda114f8db
https://github.com/llvm/llvm-project/commit/8ef0c50ecac8f1e707c02bee855f43eda114f8db
Author: lntue <lntue at google.com>
Date: 2025-07-23 (Wed, 23 Jul 2025)
Changed paths:
M libc/src/__support/CPP/type_traits/is_constant_evaluated.h
M libc/src/__support/macros/attributes.h
Log Message:
-----------
[libc] Fix problem with older compilers that do not have __has_builtin. (#150264)
Fixing bot failures:
https://lab.llvm.org/buildbot/#/builders/10/builds/10025
Commit: e67f3237d6242d1c362fa52e782ddfd5ae54a8af
https://github.com/llvm/llvm-project/commit/e67f3237d6242d1c362fa52e782ddfd5ae54a8af
Author: James Newling <james.newling at gmail.com>
Date: 2025-07-23 (Wed, 23 Jul 2025)
Changed paths:
M mlir/lib/Conversion/ArmSMEToLLVM/ArmSMEToLLVM.cpp
M mlir/lib/Conversion/ArmSMEToSCF/ArmSMEToSCF.cpp
M mlir/lib/Conversion/VectorToArmSME/VectorToArmSME.cpp
M mlir/test/Conversion/ArmSMEToSCF/arm-sme-to-scf.mlir
Log Message:
-----------
[mlir][armsme][vector] Replace splat with broadcast (#148024)
Part of deprecation of vector.splat
RFC: https://discourse.llvm.org/t/rfc-mlir-vector-deprecate-then-remove-vector-splat/87143/4
Commit: eb817c7950d3f7b555034a983240a11b8c693dc4
https://github.com/llvm/llvm-project/commit/eb817c7950d3f7b555034a983240a11b8c693dc4
Author: Amr Hesham <amr96 at programmer.net>
Date: 2025-07-23 (Wed, 23 Jul 2025)
Changed paths:
M clang/include/clang/CIR/Dialect/IR/CIROps.td
M clang/lib/CIR/CodeGen/CIRGenExprComplex.cpp
M clang/lib/CIR/CodeGen/CIRGenExprScalar.cpp
M clang/lib/CIR/Dialect/IR/CIRDialect.cpp
M clang/lib/CIR/Dialect/Transforms/LoweringPrepare.cpp
A clang/test/CIR/CodeGen/complex-cast.cpp
Log Message:
-----------
[CIR] Upstream Cast kinds for ComplexType (#149717)
This change adds support for cast kinds for ComplexType
https://github.com/llvm/llvm-project/issues/141365
Commit: 32c985485500b214d57cb25306734eb73833d59b
https://github.com/llvm/llvm-project/commit/32c985485500b214d57cb25306734eb73833d59b
Author: Delaram Talaashrafi <dtalaashrafi at nvidia.com>
Date: 2025-07-23 (Wed, 23 Jul 2025)
Changed paths:
M flang/lib/Optimizer/Transforms/ExternalNameConversion.cpp
A flang/test/Transforms/external-name-interop-symref-array.fir
Log Message:
-----------
[flang] Extend symbol update to ArrayAttrext in `external-name-interop` (#150061)
In the `external-name-interop` pass, when a symbol is changed, all the
uses of the renamed symbols should also be updated. The update was only
applied to the `SymbolRefAttr` type. With this change, the update will
be applied to `ArrayAttr` containing elements of type `SymbolRefAttr`.
---------
Co-authored-by: Delaram Talaashrafi <dtalaashrafi at nvidia.com>
Commit: 81185f7a2bd1a023ab7046a8adb4d132fdbd7ffd
https://github.com/llvm/llvm-project/commit/81185f7a2bd1a023ab7046a8adb4d132fdbd7ffd
Author: Changpeng Fang <changpeng.fang at amd.com>
Date: 2025-07-23 (Wed, 23 Jul 2025)
Changed paths:
M llvm/lib/Target/AMDGPU/VOP3PInstructions.td
M llvm/test/CodeGen/AMDGPU/packed-fp32.ll
M llvm/test/MC/AMDGPU/gfx1250_asm_vop3p.s
M llvm/test/MC/Disassembler/AMDGPU/gfx1250_dasm_vop3p.txt
Log Message:
-----------
AMDGPU: Add packed fp32 instructions for gfx1250 (#150253)
Co-authored-by: Stanislav Mekhanoshin <Stanislav.Mekhanoshin at amd.com>
Commit: 5ce04b473cd6cd3cc0c85cf21d69aa956e7ba868
https://github.com/llvm/llvm-project/commit/5ce04b473cd6cd3cc0c85cf21d69aa956e7ba868
Author: thetruestblue <bblueconway at gmail.com>
Date: 2025-07-23 (Wed, 23 Jul 2025)
Changed paths:
M compiler-rt/lib/asan/asan_mac.cpp
M compiler-rt/lib/asan/tests/asan_mac_test.cpp
M compiler-rt/lib/asan/tests/asan_mac_test.h
M compiler-rt/lib/asan/tests/asan_mac_test_helpers.mm
A compiler-rt/test/asan/TestCases/Darwin/dispatch_apply_threadno.c
Log Message:
-----------
[ASan][Darwin][GCD] Add interceptor for dispatch_apply (#149238)
ASan had a gap in coverage for wqthreads blocks submitted by
dispatch_apply
This adds interceptor for dispatch_apply and dispatch_apply_f and adds a
test that a failure in a dispatch apply block contains thread and stack
info.
rdar://139660648
Commit: e89e678839f48d54dc906e8ebed370a6e304083e
https://github.com/llvm/llvm-project/commit/e89e678839f48d54dc906e8ebed370a6e304083e
Author: Sergei Barannikov <barannikov88 at gmail.com>
Date: 2025-07-23 (Wed, 23 Jul 2025)
Changed paths:
A llvm/test/TableGen/SDNodeInfoEmitter/advanced.td
A llvm/test/TableGen/SDNodeInfoEmitter/ambiguous-constraints-1.td
A llvm/test/TableGen/SDNodeInfoEmitter/ambiguous-constraints-2.td
R llvm/test/TableGen/SDNodeInfoEmitter/ambiguous-constraints.td
R llvm/test/TableGen/SDNodeInfoEmitter/basic.td
A llvm/test/TableGen/SDNodeInfoEmitter/no-nodes.td
A llvm/test/TableGen/SDNodeInfoEmitter/trivial-node.td
Log Message:
-----------
[test] Split SDNodeInfoEmitter tests into multiple files
To simplify updating.
Commit: a36508483e1a36612175500d2dc4754f9aadacc2
https://github.com/llvm/llvm-project/commit/a36508483e1a36612175500d2dc4754f9aadacc2
Author: Maksim Levental <maksim.levental at gmail.com>
Date: 2025-07-23 (Wed, 23 Jul 2025)
Changed paths:
M mlir/include/mlir-c/IR.h
M mlir/lib/Bindings/Python/IRCore.cpp
M mlir/lib/Bindings/Python/IRModule.h
M mlir/lib/CAPI/IR/IR.cpp
M mlir/test/python/ir/operation.py
Log Message:
-----------
[mlir][python,CAPI] expose Op::isBeforeInBlock (#150271)
Commit: fc0653f31c2a153eaa87f7fe87bd5f1090c4c8ba
https://github.com/llvm/llvm-project/commit/fc0653f31c2a153eaa87f7fe87bd5f1090c4c8ba
Author: Shilei Tian <i at tianshilei.me>
Date: 2025-07-23 (Wed, 23 Jul 2025)
Changed paths:
M llvm/test/CodeGen/AMDGPU/32-bit-local-address-space.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/add_shl.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/addo.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/addsubu64.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/artifact-combiner-asserts.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/assert-align.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/atomic_load_local.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/atomic_optimizations_mul_one.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/atomic_store_local.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/atomicrmw_udec_wrap.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/atomicrmw_uinc_wrap.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/bitcast_38_i16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/bool-legalization.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/buffer-atomic-fadd.f32-no-rtn.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/buffer-atomic-fadd.f32-rtn.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/buffer-atomic-fadd.f64.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/buffer-atomic-fadd.v2f16-no-rtn.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/buffer-atomic-fadd.v2f16-rtn.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/buffer-load-store-pointers.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/buffer-schedule.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/call-outgoing-stack-args.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/clamp-fmed3-const-combine.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/clamp-minmax-const-combine.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/combine-rsq.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/combine-shift-imm-chain.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/combine-shift-of-shifted-logic.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/combine-short-clamp.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/constant-bus-restriction.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/cvt_f32_ubyte.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/divergence-divergent-i1-phis-no-lane-mask-merging.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/divergence-divergent-i1-used-outside-loop.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/divergence-structurizer.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/divergence-temporal-divergent-i1.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/divergence-temporal-divergent-reg.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/divergent-control-flow.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/dynamic-alloca-uniform.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/extractelement-stack-lower.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/extractelement.i128.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/extractelement.i16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/extractelement.i8.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/extractelement.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/fdiv.f16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/fdiv.f32.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/fdiv.f64.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/flat-atomic-fadd.f32.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/flat-atomic-fadd.v2f16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/flat-scratch.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/fmed3-min-max-const-combine.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/fp64-atomics-gfx90a.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/frem.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/function-returns.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/hip.extern.shared.array.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/image-waterfall-loop-O0.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/inline-asm-mismatched-size.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/inline-asm.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/insertelement-stack-lower.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/insertelement.i16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/insertelement.i8.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/insertelement.large.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-amdgcn-cs-chain.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-amdgcn-sendmsg.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-amdgpu_kernel.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-assert-align.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-call-abi-attribute-hints.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-call-implicit-args.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-call-non-fixed.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-call-return-values.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-call-sret.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-call.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-constantexpr.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-constrained-fp.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-fence.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-function-args.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-indirect-call.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-inline-asm.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-invariant.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-memory-intrinsics.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-prefetch.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-ptrmask.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-sibling-call.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-tail-call.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-zext-vec-index.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/is-safe-to-sink-bug.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/lds-global-value.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/lds-misaligned-bug.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/lds-relocs.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/lds-zero-initializer.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-llvm.amdgcn.image.atomic.dim.a16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.abs.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.ballot.i32.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.ballot.i64.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.dispatch.ptr.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.div.scale.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.end.cf.i32.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.end.cf.i64.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.fdot2.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.fmul.legacy.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.global.atomic.csub.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.if.break.i32.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.if.break.i64.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.getresinfo.a16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.getresinfo.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.load.1d.d16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.load.1d.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.load.2d.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.load.2darraymsaa.a16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.load.2darraymsaa.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.load.3d.a16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.load.3d.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.sample.cd.g16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.sample.g16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.implicit.ptr.buffer.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.interp.inreg.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.interp.p1.f16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.intersect_ray.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.kernarg.segment.ptr.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.make.buffer.rsrc.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.mfma.gfx90a.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.mov.dpp.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.queue.ptr.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.buffer.atomic.add.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.buffer.atomic.cmpswap.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.buffer.atomic.fadd-with-ret.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.buffer.atomic.fadd.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.buffer.load.format.f16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.buffer.load.format.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.buffer.load.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.buffer.load.tfe.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.buffer.store.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.ptr.buffer.atomic.add.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.ptr.buffer.atomic.cmpswap.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.ptr.buffer.atomic.fadd-with-ret.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.ptr.buffer.atomic.fadd.ll
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M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.ptr.buffer.load.format.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.ptr.buffer.load.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.ptr.buffer.store.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.ptr.tbuffer.load.f16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.ptr.tbuffer.load.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.ptr.tbuffer.store.f16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.ptr.tbuffer.store.i8.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.ptr.tbuffer.store.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.tbuffer.load.f16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.tbuffer.load.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.tbuffer.store.f16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.tbuffer.store.i8.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.tbuffer.store.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.rsq.clamp.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.s.buffer.load.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.s.setreg.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.s.sleep.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.sbfe.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.sdot2.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.sdot4.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.sdot8.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.set.inactive.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.softwqm.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.buffer.atomic.add.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.buffer.atomic.cmpswap.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.buffer.atomic.fadd-with-ret.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.buffer.atomic.fadd.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.buffer.load.format.f16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.buffer.load.format.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.buffer.load.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.buffer.load.tfe.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.buffer.store.format.f16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.buffer.store.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.ptr.buffer.atomic.add.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.ptr.buffer.atomic.cmpswap.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.ptr.buffer.atomic.fadd-with-ret.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.ptr.buffer.atomic.fadd.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.ptr.buffer.load.format.f16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.ptr.buffer.load.format.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.ptr.buffer.load.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.ptr.buffer.store.format.f16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.ptr.buffer.store.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.ptr.tbuffer.load.f16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.ptr.tbuffer.load.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.tbuffer.load.f16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.tbuffer.load.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.sudot4.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.sudot8.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.ubfe.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.udot2.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.udot4.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.udot8.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.update.dpp.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.wmma_32.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.wmma_64.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.workitem.id.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.wqm.demote.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.wqm.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.writelane.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.wwm.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.memcpy.inline.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.memcpy.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.memmove.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.memset.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/load-local.128.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/load-local.96.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/load-unaligned.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/merge-buffer-stores.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/mul-known-bits.i64.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/mul.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/non-entry-alloca.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/sdivrem.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/select-to-fmin-fmax.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/shader-epilogs.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/shl-ext-reduce.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/shlN_add.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/shufflevector.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/smed3.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/smrd.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/store-local.128.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/store-local.96.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/subo.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/trunc.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/udivrem.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/umed3.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/v_bfe_i32.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/widen-i8-i16-scalar-loads.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/wmma-gfx12-w32-f16-f32-matrix-modifiers.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/wmma-gfx12-w32-imm.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/wmma-gfx12-w32-iu-modifiers.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/wmma-gfx12-w32-swmmac-index_key.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/wmma-gfx12-w32.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/wmma-gfx12-w64-f16-f32-matrix-modifiers.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/wmma-gfx12-w64-imm.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/wmma-gfx12-w64-iu-modifiers.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/wmma-gfx12-w64-swmmac-index_key.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/wmma-gfx12-w64.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/xnor.ll
M llvm/test/CodeGen/AMDGPU/InlineAsmCrash.ll
M llvm/test/CodeGen/AMDGPU/acc-ldst.ll
M llvm/test/CodeGen/AMDGPU/add.i16.ll
M llvm/test/CodeGen/AMDGPU/add.ll
M llvm/test/CodeGen/AMDGPU/add.v2i16.ll
M llvm/test/CodeGen/AMDGPU/add3.ll
M llvm/test/CodeGen/AMDGPU/add_i1.ll
M llvm/test/CodeGen/AMDGPU/add_i128.ll
M llvm/test/CodeGen/AMDGPU/add_i64.ll
M llvm/test/CodeGen/AMDGPU/add_shl.ll
M llvm/test/CodeGen/AMDGPU/addrspacecast-initializer-unsupported.ll
M llvm/test/CodeGen/AMDGPU/addrspacecast-initializer.ll
M llvm/test/CodeGen/AMDGPU/adjust-writemask-invalid-copy.ll
M llvm/test/CodeGen/AMDGPU/adjust-writemask-vectorized.ll
M llvm/test/CodeGen/AMDGPU/agpr-csr.ll
M llvm/test/CodeGen/AMDGPU/agpr-register-count.ll
M llvm/test/CodeGen/AMDGPU/agpr-remat.ll
M llvm/test/CodeGen/AMDGPU/alignbit-pat.ll
M llvm/test/CodeGen/AMDGPU/always-uniform.ll
M llvm/test/CodeGen/AMDGPU/amd.endpgm.ll
M llvm/test/CodeGen/AMDGPU/amdgcn-ieee.ll
M llvm/test/CodeGen/AMDGPU/amdgcn-load-offset-from-reg.ll
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.1024bit.ll
M llvm/test/CodeGen/AMDGPU/amdgcn.private-memory.ll
M llvm/test/CodeGen/AMDGPU/amdgpu-cs-chain-cc.ll
M llvm/test/CodeGen/AMDGPU/amdgpu-cs-chain-preserve-cc.ll
M llvm/test/CodeGen/AMDGPU/amdgpu-mul24-knownbits.ll
M llvm/test/CodeGen/AMDGPU/amdgpu-nsa-threshold.ll
M llvm/test/CodeGen/AMDGPU/amdgpu-reloc-const.ll
M llvm/test/CodeGen/AMDGPU/amdgpu-shader-calling-convention.ll
M llvm/test/CodeGen/AMDGPU/amdgpu.private-memory.ll
M llvm/test/CodeGen/AMDGPU/amdgpu.work-item-intrinsics.deprecated.ll
M llvm/test/CodeGen/AMDGPU/amdpal-callable.ll
M llvm/test/CodeGen/AMDGPU/amdpal-cs.ll
M llvm/test/CodeGen/AMDGPU/amdpal-es.ll
M llvm/test/CodeGen/AMDGPU/amdpal-gs.ll
M llvm/test/CodeGen/AMDGPU/amdpal-hs.ll
M llvm/test/CodeGen/AMDGPU/amdpal-ls.ll
M llvm/test/CodeGen/AMDGPU/amdpal-msgpack-cs.ll
M llvm/test/CodeGen/AMDGPU/amdpal-msgpack-default.ll
M llvm/test/CodeGen/AMDGPU/amdpal-msgpack-denormal.ll
M llvm/test/CodeGen/AMDGPU/amdpal-msgpack-dx10-clamp.ll
M llvm/test/CodeGen/AMDGPU/amdpal-msgpack-es.ll
M llvm/test/CodeGen/AMDGPU/amdpal-msgpack-gs.ll
M llvm/test/CodeGen/AMDGPU/amdpal-msgpack-hs.ll
M llvm/test/CodeGen/AMDGPU/amdpal-msgpack-ieee.ll
M llvm/test/CodeGen/AMDGPU/amdpal-msgpack-ls.ll
M llvm/test/CodeGen/AMDGPU/amdpal-msgpack-ps.ll
M llvm/test/CodeGen/AMDGPU/amdpal-msgpack-psenable.ll
M llvm/test/CodeGen/AMDGPU/amdpal-msgpack-vs.ll
M llvm/test/CodeGen/AMDGPU/amdpal-ps.ll
M llvm/test/CodeGen/AMDGPU/amdpal-psenable.ll
M llvm/test/CodeGen/AMDGPU/amdpal-usersgpr-init.ll
M llvm/test/CodeGen/AMDGPU/amdpal-vs.ll
M llvm/test/CodeGen/AMDGPU/amdpal_scratch_mergedshader.ll
M llvm/test/CodeGen/AMDGPU/and-gcn.ll
M llvm/test/CodeGen/AMDGPU/and.ll
M llvm/test/CodeGen/AMDGPU/and_or.ll
M llvm/test/CodeGen/AMDGPU/andorbitset.ll
M llvm/test/CodeGen/AMDGPU/andorn2.ll
M llvm/test/CodeGen/AMDGPU/andorxorinvimm.ll
M llvm/test/CodeGen/AMDGPU/any_extend_vector_inreg.ll
M llvm/test/CodeGen/AMDGPU/anyext.ll
M llvm/test/CodeGen/AMDGPU/are-loads-from-same-base-ptr.ll
M llvm/test/CodeGen/AMDGPU/array-ptr-calc-i32.ll
M llvm/test/CodeGen/AMDGPU/array-ptr-calc-i64.ll
M llvm/test/CodeGen/AMDGPU/ashr.v2i16.ll
M llvm/test/CodeGen/AMDGPU/atomic_cmp_swap_local.ll
M llvm/test/CodeGen/AMDGPU/atomic_load_add.ll
M llvm/test/CodeGen/AMDGPU/atomic_load_local.ll
M llvm/test/CodeGen/AMDGPU/atomic_load_sub.ll
M llvm/test/CodeGen/AMDGPU/atomic_optimizations_buffer.ll
M llvm/test/CodeGen/AMDGPU/atomic_optimizations_global_pointer.ll
M llvm/test/CodeGen/AMDGPU/atomic_optimizations_pixelshader.ll
M llvm/test/CodeGen/AMDGPU/atomic_optimizations_raw_buffer.ll
M llvm/test/CodeGen/AMDGPU/atomic_optimizations_struct_buffer.ll
M llvm/test/CodeGen/AMDGPU/atomic_store_local.ll
M llvm/test/CodeGen/AMDGPU/atomicrmw-expand.ll
M llvm/test/CodeGen/AMDGPU/atomicrmw-nand.ll
M llvm/test/CodeGen/AMDGPU/atomics-cas-remarks-gfx90a.ll
M llvm/test/CodeGen/AMDGPU/atomics-hw-remarks-gfx90a.ll
M llvm/test/CodeGen/AMDGPU/atomics_cond_sub.ll
M llvm/test/CodeGen/AMDGPU/attr-amdgpu-flat-work-group-size-vgpr-limit.ll
M llvm/test/CodeGen/AMDGPU/attr-amdgpu-flat-work-group-size.ll
M llvm/test/CodeGen/AMDGPU/attr-amdgpu-num-sgpr.ll
M llvm/test/CodeGen/AMDGPU/attr-amdgpu-num-vgpr.ll
M llvm/test/CodeGen/AMDGPU/attr-amdgpu-waves-per-eu.ll
M llvm/test/CodeGen/AMDGPU/attr-unparseable.ll
M llvm/test/CodeGen/AMDGPU/back-off-barrier-subtarget-feature.ll
M llvm/test/CodeGen/AMDGPU/basic-branch.ll
M llvm/test/CodeGen/AMDGPU/basic-call-return.ll
M llvm/test/CodeGen/AMDGPU/basic-loop.ll
M llvm/test/CodeGen/AMDGPU/bb-prolog-spill-during-regalloc.ll
M llvm/test/CodeGen/AMDGPU/bfe-patterns.ll
M llvm/test/CodeGen/AMDGPU/bfi_int.ll
M llvm/test/CodeGen/AMDGPU/bfi_nested.ll
M llvm/test/CodeGen/AMDGPU/bfm.ll
M llvm/test/CodeGen/AMDGPU/bitcast-constant-to-vector.ll
M llvm/test/CodeGen/AMDGPU/bitcast-v4f16-v4i16.ll
M llvm/test/CodeGen/AMDGPU/bitcast-vector-extract.ll
M llvm/test/CodeGen/AMDGPU/bitreverse-inline-immediates.ll
M llvm/test/CodeGen/AMDGPU/bitreverse.ll
M llvm/test/CodeGen/AMDGPU/br_cc.f16.ll
M llvm/test/CodeGen/AMDGPU/branch-relax-bundle.ll
M llvm/test/CodeGen/AMDGPU/branch-relax-spill.ll
M llvm/test/CodeGen/AMDGPU/branch-relaxation-gfx10-branch-offset-bug.ll
M llvm/test/CodeGen/AMDGPU/branch-relaxation-inst-size-gfx10.ll
M llvm/test/CodeGen/AMDGPU/branch-relaxation.ll
M llvm/test/CodeGen/AMDGPU/branch-uniformity.ll
M llvm/test/CodeGen/AMDGPU/bswap.ll
M llvm/test/CodeGen/AMDGPU/buffer-atomic-fadd.f32-no-rtn.ll
M llvm/test/CodeGen/AMDGPU/buffer-atomic-fadd.f32-rtn.ll
M llvm/test/CodeGen/AMDGPU/buffer-atomic-fadd.f64.ll
M llvm/test/CodeGen/AMDGPU/buffer-atomic-fadd.v2f16-no-rtn.ll
M llvm/test/CodeGen/AMDGPU/buffer-atomic-fadd.v2f16-rtn.ll
M llvm/test/CodeGen/AMDGPU/buffer-intrinsics-mmo-offsets.ll
M llvm/test/CodeGen/AMDGPU/buffer-rsrc-ptr-ops.ll
M llvm/test/CodeGen/AMDGPU/buffer-schedule.ll
M llvm/test/CodeGen/AMDGPU/bug-deadlanes.ll
M llvm/test/CodeGen/AMDGPU/bug-sdag-scheduler-cycle.ll
M llvm/test/CodeGen/AMDGPU/bug-v4f64-subvector.ll
M llvm/test/CodeGen/AMDGPU/build-vector-insert-elt-infloop.ll
M llvm/test/CodeGen/AMDGPU/build-vector-packed-partial-undef.ll
M llvm/test/CodeGen/AMDGPU/byval-frame-setup.ll
M llvm/test/CodeGen/AMDGPU/call-args-inreg-no-sgpr-for-csrspill-xfail.ll
M llvm/test/CodeGen/AMDGPU/call-argument-types.ll
M llvm/test/CodeGen/AMDGPU/call-c-function.ll
M llvm/test/CodeGen/AMDGPU/call-constexpr.ll
M llvm/test/CodeGen/AMDGPU/call-encoding.ll
M llvm/test/CodeGen/AMDGPU/call-graph-register-usage.ll
M llvm/test/CodeGen/AMDGPU/call-preserved-registers.ll
M llvm/test/CodeGen/AMDGPU/call-return-types.ll
M llvm/test/CodeGen/AMDGPU/callee-frame-setup.ll
M llvm/test/CodeGen/AMDGPU/calling-conventions.ll
M llvm/test/CodeGen/AMDGPU/captured-frame-index.ll
M llvm/test/CodeGen/AMDGPU/carryout-selection.ll
M llvm/test/CodeGen/AMDGPU/cc-sgpr-limit.ll
M llvm/test/CodeGen/AMDGPU/cc-sgpr-over-limit.ll
M llvm/test/CodeGen/AMDGPU/cf-loop-on-constant.ll
M llvm/test/CodeGen/AMDGPU/cgp-bitfield-extract.ll
M llvm/test/CodeGen/AMDGPU/chain-hi-to-lo.ll
M llvm/test/CodeGen/AMDGPU/clamp-modifier.ll
M llvm/test/CodeGen/AMDGPU/clamp.ll
M llvm/test/CodeGen/AMDGPU/cluster_stores.ll
M llvm/test/CodeGen/AMDGPU/cndmask-no-def-vcc.ll
M llvm/test/CodeGen/AMDGPU/coalesce-vgpr-alignment.ll
M llvm/test/CodeGen/AMDGPU/coalescer_remat.ll
M llvm/test/CodeGen/AMDGPU/codegen-prepare-addrmode-sext.ll
M llvm/test/CodeGen/AMDGPU/collapse-endcf.ll
M llvm/test/CodeGen/AMDGPU/combine-add-zext-xor.ll
M llvm/test/CodeGen/AMDGPU/combine-and-sext-bool.ll
M llvm/test/CodeGen/AMDGPU/combine-cond-add-sub.ll
M llvm/test/CodeGen/AMDGPU/combine-ftrunc.ll
M llvm/test/CodeGen/AMDGPU/combine-vload-extract.ll
M llvm/test/CodeGen/AMDGPU/combine_andor_with_cmps.ll
M llvm/test/CodeGen/AMDGPU/commute-compares-scalar-float.ll
M llvm/test/CodeGen/AMDGPU/commute-compares.ll
M llvm/test/CodeGen/AMDGPU/commute-shifts.ll
M llvm/test/CodeGen/AMDGPU/commute_modifiers.ll
M llvm/test/CodeGen/AMDGPU/computeKnownBits-scalar-to-vector-crash.ll
M llvm/test/CodeGen/AMDGPU/concat_vectors.ll
M llvm/test/CodeGen/AMDGPU/constant-fold-mi-operands.ll
M llvm/test/CodeGen/AMDGPU/control-flow-fastregalloc.ll
M llvm/test/CodeGen/AMDGPU/control-flow-optnone.ll
M llvm/test/CodeGen/AMDGPU/convergence-tokens.ll
M llvm/test/CodeGen/AMDGPU/convergent-inlineasm.ll
M llvm/test/CodeGen/AMDGPU/copy_to_scc.ll
M llvm/test/CodeGen/AMDGPU/cross-block-use-is-not-abi-copy.ll
M llvm/test/CodeGen/AMDGPU/cse-convergent.ll
M llvm/test/CodeGen/AMDGPU/cse-phi-incoming-val.ll
M llvm/test/CodeGen/AMDGPU/ctlz.ll
M llvm/test/CodeGen/AMDGPU/ctlz_zero_undef.ll
M llvm/test/CodeGen/AMDGPU/ctpop.ll
M llvm/test/CodeGen/AMDGPU/ctpop16.ll
M llvm/test/CodeGen/AMDGPU/ctpop64.ll
M llvm/test/CodeGen/AMDGPU/cttz.ll
M llvm/test/CodeGen/AMDGPU/cttz_zero_undef.ll
M llvm/test/CodeGen/AMDGPU/cube.ll
M llvm/test/CodeGen/AMDGPU/cvt_f32_ubyte.ll
M llvm/test/CodeGen/AMDGPU/cvt_flr_i32_f32.ll
M llvm/test/CodeGen/AMDGPU/cvt_rpi_i32_f32.ll
M llvm/test/CodeGen/AMDGPU/dag-divergence.ll
M llvm/test/CodeGen/AMDGPU/dagcomb-shuffle-vecextend-non2.ll
M llvm/test/CodeGen/AMDGPU/dagcombine-fma-fmad.ll
M llvm/test/CodeGen/AMDGPU/dagcombine-lshr-and-cmp.ll
M llvm/test/CodeGen/AMDGPU/dagcombine-reassociate-bug.ll
M llvm/test/CodeGen/AMDGPU/dagcombine-select.ll
M llvm/test/CodeGen/AMDGPU/dagcombine-setcc-select.ll
M llvm/test/CodeGen/AMDGPU/debug-value.ll
M llvm/test/CodeGen/AMDGPU/debug-value2.ll
M llvm/test/CodeGen/AMDGPU/debug.ll
M llvm/test/CodeGen/AMDGPU/default-fp-mode.ll
M llvm/test/CodeGen/AMDGPU/disable_form_clauses.ll
M llvm/test/CodeGen/AMDGPU/div_v2i128.ll
M llvm/test/CodeGen/AMDGPU/diverge-extra-formal-args.ll
M llvm/test/CodeGen/AMDGPU/diverge-interp-mov-lower.ll
M llvm/test/CodeGen/AMDGPU/divergence-driven-bfe-isel.ll
M llvm/test/CodeGen/AMDGPU/divergent-branch-uniform-condition.ll
M llvm/test/CodeGen/AMDGPU/dpp64_combine.ll
M llvm/test/CodeGen/AMDGPU/dpp_combine.ll
M llvm/test/CodeGen/AMDGPU/drop-mem-operand-move-smrd.ll
M llvm/test/CodeGen/AMDGPU/ds-combine-large-stride.ll
M llvm/test/CodeGen/AMDGPU/ds-combine-with-dependence.ll
M llvm/test/CodeGen/AMDGPU/ds-negative-offset-addressing-mode-loop.ll
M llvm/test/CodeGen/AMDGPU/ds-sub-offset.ll
M llvm/test/CodeGen/AMDGPU/ds-vectorization-alignment.ll
M llvm/test/CodeGen/AMDGPU/ds_gws_align.ll
M llvm/test/CodeGen/AMDGPU/ds_read2.ll
M llvm/test/CodeGen/AMDGPU/ds_read2_offset_order.ll
M llvm/test/CodeGen/AMDGPU/ds_read2_superreg.ll
M llvm/test/CodeGen/AMDGPU/ds_read2st64.ll
M llvm/test/CodeGen/AMDGPU/ds_write2.ll
M llvm/test/CodeGen/AMDGPU/ds_write2st64.ll
M llvm/test/CodeGen/AMDGPU/dual-source-blend-export.ll
M llvm/test/CodeGen/AMDGPU/early-if-convert-cost.ll
M llvm/test/CodeGen/AMDGPU/early-if-convert.ll
M llvm/test/CodeGen/AMDGPU/elf.ll
M llvm/test/CodeGen/AMDGPU/else.ll
M llvm/test/CodeGen/AMDGPU/empty-function.ll
M llvm/test/CodeGen/AMDGPU/endcf-loop-header.ll
M llvm/test/CodeGen/AMDGPU/exceed-max-sgprs.ll
M llvm/test/CodeGen/AMDGPU/expand-atomicrmw-syncscope.ll
M llvm/test/CodeGen/AMDGPU/extend-bit-ops-i16.ll
M llvm/test/CodeGen/AMDGPU/extload-align.ll
M llvm/test/CodeGen/AMDGPU/extload-private.ll
M llvm/test/CodeGen/AMDGPU/extload.ll
M llvm/test/CodeGen/AMDGPU/extract-lowbits.ll
M llvm/test/CodeGen/AMDGPU/extract-subvector-16bit.ll
M llvm/test/CodeGen/AMDGPU/extract-subvector-equal-length.ll
M llvm/test/CodeGen/AMDGPU/extract-subvector.ll
M llvm/test/CodeGen/AMDGPU/extract-vector-elt-build-vector-combine.ll
M llvm/test/CodeGen/AMDGPU/extract_vector_elt-f16.ll
M llvm/test/CodeGen/AMDGPU/extract_vector_elt-f64.ll
M llvm/test/CodeGen/AMDGPU/extract_vector_elt-i16.ll
M llvm/test/CodeGen/AMDGPU/extract_vector_elt-i64.ll
M llvm/test/CodeGen/AMDGPU/extractelt-to-trunc.ll
M llvm/test/CodeGen/AMDGPU/fabs.f16.ll
M llvm/test/CodeGen/AMDGPU/fabs.f64.ll
M llvm/test/CodeGen/AMDGPU/fadd-fma-fmul-combine.ll
M llvm/test/CodeGen/AMDGPU/fadd.f16.ll
M llvm/test/CodeGen/AMDGPU/fadd.ll
M llvm/test/CodeGen/AMDGPU/fadd64.ll
M llvm/test/CodeGen/AMDGPU/fcanonicalize-elimination.ll
M llvm/test/CodeGen/AMDGPU/fcanonicalize.f16.ll
M llvm/test/CodeGen/AMDGPU/fcanonicalize.ll
M llvm/test/CodeGen/AMDGPU/fceil.ll
M llvm/test/CodeGen/AMDGPU/fceil64.ll
M llvm/test/CodeGen/AMDGPU/fcmp.f16.ll
M llvm/test/CodeGen/AMDGPU/fcmp64.ll
M llvm/test/CodeGen/AMDGPU/fconst64.ll
M llvm/test/CodeGen/AMDGPU/fdiv.f16.ll
M llvm/test/CodeGen/AMDGPU/fdiv.f64.ll
M llvm/test/CodeGen/AMDGPU/fdot2.ll
M llvm/test/CodeGen/AMDGPU/fence-barrier.ll
M llvm/test/CodeGen/AMDGPU/fence-lds-read2-write2.ll
M llvm/test/CodeGen/AMDGPU/ffloor.f64.ll
M llvm/test/CodeGen/AMDGPU/ffloor.ll
M llvm/test/CodeGen/AMDGPU/fix-frame-ptr-reg-copy-livein.ll
M llvm/test/CodeGen/AMDGPU/fix-frame-reg-in-custom-csr-spills.ll
M llvm/test/CodeGen/AMDGPU/fix-wwm-vgpr-copy.ll
M llvm/test/CodeGen/AMDGPU/flat-atomic-fadd.f32.ll
M llvm/test/CodeGen/AMDGPU/flat-atomic-fadd.f64.ll
M llvm/test/CodeGen/AMDGPU/flat-offset-bug.ll
M llvm/test/CodeGen/AMDGPU/flat-scratch-i8-i16.ll
M llvm/test/CodeGen/AMDGPU/fma-combine.ll
M llvm/test/CodeGen/AMDGPU/fma.f16.ll
M llvm/test/CodeGen/AMDGPU/fma.f64.ll
M llvm/test/CodeGen/AMDGPU/fma.ll
M llvm/test/CodeGen/AMDGPU/fmac.sdwa.ll
M llvm/test/CodeGen/AMDGPU/fmax3.f64.ll
M llvm/test/CodeGen/AMDGPU/fmax3.ll
M llvm/test/CodeGen/AMDGPU/fmax_legacy.f16.ll
M llvm/test/CodeGen/AMDGPU/fmax_legacy.ll
M llvm/test/CodeGen/AMDGPU/fmed3.ll
M llvm/test/CodeGen/AMDGPU/fmin3.ll
M llvm/test/CodeGen/AMDGPU/fmin_legacy.f16.ll
M llvm/test/CodeGen/AMDGPU/fmin_legacy.ll
M llvm/test/CodeGen/AMDGPU/fmul-2-combine-multi-use.ll
M llvm/test/CodeGen/AMDGPU/fmul.f16.ll
M llvm/test/CodeGen/AMDGPU/fmul64.ll
M llvm/test/CodeGen/AMDGPU/fmuladd.f16.ll
M llvm/test/CodeGen/AMDGPU/fmuladd.f32.ll
M llvm/test/CodeGen/AMDGPU/fmuladd.f64.ll
M llvm/test/CodeGen/AMDGPU/fmuladd.v2f16.ll
M llvm/test/CodeGen/AMDGPU/fnearbyint.ll
M llvm/test/CodeGen/AMDGPU/fneg-combines-gfx1200.ll
M llvm/test/CodeGen/AMDGPU/fneg-combines.si.ll
M llvm/test/CodeGen/AMDGPU/fneg-fabs.f16.ll
M llvm/test/CodeGen/AMDGPU/fneg.f16.ll
M llvm/test/CodeGen/AMDGPU/fneg.f64.ll
M llvm/test/CodeGen/AMDGPU/fold-fabs.ll
M llvm/test/CodeGen/AMDGPU/fold-fmaak-bug.ll
M llvm/test/CodeGen/AMDGPU/fold-fmul-to-neg-abs.ll
M llvm/test/CodeGen/AMDGPU/fold-int-pow2-with-fmul-or-fdiv.ll
M llvm/test/CodeGen/AMDGPU/fp-classify.ll
M llvm/test/CodeGen/AMDGPU/fp-min-max-buffer-atomics.ll
M llvm/test/CodeGen/AMDGPU/fp-min-max-buffer-ptr-atomics.ll
M llvm/test/CodeGen/AMDGPU/fp-min-max-image-atomics.ll
M llvm/test/CodeGen/AMDGPU/fp-min-max-num-flat-atomics.ll
M llvm/test/CodeGen/AMDGPU/fp-min-max-num-global-atomics.ll
M llvm/test/CodeGen/AMDGPU/fp16_to_fp32.ll
M llvm/test/CodeGen/AMDGPU/fp16_to_fp64.ll
M llvm/test/CodeGen/AMDGPU/fp32_to_fp16.ll
M llvm/test/CodeGen/AMDGPU/fp64-min-max-buffer-atomics.ll
M llvm/test/CodeGen/AMDGPU/fp64-min-max-buffer-ptr-atomics.ll
M llvm/test/CodeGen/AMDGPU/fp_to_sint.f64.ll
M llvm/test/CodeGen/AMDGPU/fp_to_sint.ll
M llvm/test/CodeGen/AMDGPU/fp_to_uint.f64.ll
M llvm/test/CodeGen/AMDGPU/fp_to_uint.ll
M llvm/test/CodeGen/AMDGPU/fpext-free.ll
M llvm/test/CodeGen/AMDGPU/fpext.f16.ll
M llvm/test/CodeGen/AMDGPU/fpext.ll
M llvm/test/CodeGen/AMDGPU/fptosi.f16.ll
M llvm/test/CodeGen/AMDGPU/fptoui.f16.ll
M llvm/test/CodeGen/AMDGPU/fptrunc.f16.ll
M llvm/test/CodeGen/AMDGPU/fptrunc.ll
M llvm/test/CodeGen/AMDGPU/fract.f64.ll
M llvm/test/CodeGen/AMDGPU/fract.ll
M llvm/test/CodeGen/AMDGPU/frame-index-elimination.ll
M llvm/test/CodeGen/AMDGPU/frame-setup-without-sgpr-to-vgpr-spills.ll
M llvm/test/CodeGen/AMDGPU/frem.ll
M llvm/test/CodeGen/AMDGPU/fshl.ll
M llvm/test/CodeGen/AMDGPU/fshr.ll
M llvm/test/CodeGen/AMDGPU/fsqrt.f64.ll
M llvm/test/CodeGen/AMDGPU/fsub.f16.ll
M llvm/test/CodeGen/AMDGPU/fsub.ll
M llvm/test/CodeGen/AMDGPU/fsub64.ll
M llvm/test/CodeGen/AMDGPU/function-args.ll
M llvm/test/CodeGen/AMDGPU/function-returns.ll
M llvm/test/CodeGen/AMDGPU/fused-bitlogic.ll
M llvm/test/CodeGen/AMDGPU/gds-allocation.ll
M llvm/test/CodeGen/AMDGPU/gds-atomic.ll
M llvm/test/CodeGen/AMDGPU/gep-address-space.ll
M llvm/test/CodeGen/AMDGPU/gfx-call-non-gfx-func.ll
M llvm/test/CodeGen/AMDGPU/gfx-callable-argument-types.ll
M llvm/test/CodeGen/AMDGPU/gfx-callable-preserved-registers.ll
M llvm/test/CodeGen/AMDGPU/gfx-callable-return-types.ll
M llvm/test/CodeGen/AMDGPU/gfx10-vop-literal.ll
M llvm/test/CodeGen/AMDGPU/gfx12_scalar_subword_loads.ll
M llvm/test/CodeGen/AMDGPU/gfx90a-enc.ll
M llvm/test/CodeGen/AMDGPU/global-address.ll
M llvm/test/CodeGen/AMDGPU/global-atomic-fadd.f32-no-rtn.ll
M llvm/test/CodeGen/AMDGPU/global-atomic-fadd.f32-rtn.ll
M llvm/test/CodeGen/AMDGPU/global-constant.ll
M llvm/test/CodeGen/AMDGPU/global-directive.ll
M llvm/test/CodeGen/AMDGPU/global-extload-i16.ll
M llvm/test/CodeGen/AMDGPU/global-i16-load-store.ll
M llvm/test/CodeGen/AMDGPU/global-load-saddr-to-vaddr.ll
M llvm/test/CodeGen/AMDGPU/global_atomics.ll
M llvm/test/CodeGen/AMDGPU/global_atomics_i32_system.ll
M llvm/test/CodeGen/AMDGPU/global_atomics_i64.ll
M llvm/test/CodeGen/AMDGPU/global_atomics_i64_system.ll
M llvm/test/CodeGen/AMDGPU/global_atomics_scan_fmax.ll
M llvm/test/CodeGen/AMDGPU/global_atomics_scan_fmin.ll
M llvm/test/CodeGen/AMDGPU/global_atomics_scan_fsub.ll
M llvm/test/CodeGen/AMDGPU/global_smrd.ll
M llvm/test/CodeGen/AMDGPU/global_smrd_cfg.ll
M llvm/test/CodeGen/AMDGPU/gv-const-addrspace.ll
M llvm/test/CodeGen/AMDGPU/half.ll
M llvm/test/CodeGen/AMDGPU/hip.extern.shared.array.ll
M llvm/test/CodeGen/AMDGPU/hoist-cond.ll
M llvm/test/CodeGen/AMDGPU/hsa-fp-mode.ll
M llvm/test/CodeGen/AMDGPU/hsa-metadata-agpr-register-count.ll
M llvm/test/CodeGen/AMDGPU/huge-private-buffer.ll
M llvm/test/CodeGen/AMDGPU/i1-copy-from-loop.ll
M llvm/test/CodeGen/AMDGPU/i1-copy-implicit-def.ll
M llvm/test/CodeGen/AMDGPU/i1-copy-phi-uniform-branch.ll
M llvm/test/CodeGen/AMDGPU/i1-copy-phi.ll
M llvm/test/CodeGen/AMDGPU/icmp.i16.ll
M llvm/test/CodeGen/AMDGPU/icmp64.ll
M llvm/test/CodeGen/AMDGPU/idemponent-atomics.ll
M llvm/test/CodeGen/AMDGPU/idiv-licm.ll
M llvm/test/CodeGen/AMDGPU/illegal-sgpr-to-vgpr-copy.ll
M llvm/test/CodeGen/AMDGPU/image-load-d16-tfe.ll
M llvm/test/CodeGen/AMDGPU/image-sample-waterfall.ll
M llvm/test/CodeGen/AMDGPU/image-schedule.ll
M llvm/test/CodeGen/AMDGPU/img-nouse-adjust.ll
M llvm/test/CodeGen/AMDGPU/imm.ll
M llvm/test/CodeGen/AMDGPU/imm16.ll
M llvm/test/CodeGen/AMDGPU/immv216.ll
M llvm/test/CodeGen/AMDGPU/implicit-def-muse.ll
M llvm/test/CodeGen/AMDGPU/indirect-addressing-si-gfx9.ll
M llvm/test/CodeGen/AMDGPU/indirect-addressing-term.ll
M llvm/test/CodeGen/AMDGPU/indirect-call.ll
M llvm/test/CodeGen/AMDGPU/indirect-private-64.ll
M llvm/test/CodeGen/AMDGPU/infinite-loop.ll
M llvm/test/CodeGen/AMDGPU/inline-asm-reserved-regs.ll
M llvm/test/CodeGen/AMDGPU/inline-asm.ll
M llvm/test/CodeGen/AMDGPU/inline-calls.ll
M llvm/test/CodeGen/AMDGPU/inline-constraints.ll
M llvm/test/CodeGen/AMDGPU/inlineasm-16.ll
M llvm/test/CodeGen/AMDGPU/inlineasm-illegal-type.ll
M llvm/test/CodeGen/AMDGPU/inlineasm-packed.ll
M llvm/test/CodeGen/AMDGPU/inlineasm-v16.ll
M llvm/test/CodeGen/AMDGPU/insert-delay-alu-bug.ll
M llvm/test/CodeGen/AMDGPU/insert-subvector-unused-scratch.ll
M llvm/test/CodeGen/AMDGPU/insert-waitcnts-crash.ll
M llvm/test/CodeGen/AMDGPU/insert_subreg.ll
M llvm/test/CodeGen/AMDGPU/insert_vector_elt.v2bf16.ll
M llvm/test/CodeGen/AMDGPU/insert_vector_elt.v2i16.ll
M llvm/test/CodeGen/AMDGPU/insert_vector_elt.v2i16.subtest-nosaddr.ll
M llvm/test/CodeGen/AMDGPU/insert_vector_elt.v2i16.subtest-saddr.ll
M llvm/test/CodeGen/AMDGPU/invariant-load-no-alias-store.ll
M llvm/test/CodeGen/AMDGPU/ipra-return-address-save-restore.ll
M llvm/test/CodeGen/AMDGPU/ipra.ll
M llvm/test/CodeGen/AMDGPU/irtranslator-whole-wave-functions.ll
M llvm/test/CodeGen/AMDGPU/isel-amdgcn-cs-chain-intrinsic-w32.ll
M llvm/test/CodeGen/AMDGPU/isel-amdgcn-cs-chain-intrinsic-w64.ll
M llvm/test/CodeGen/AMDGPU/isel-amdgpu-cs-chain-cc.ll
M llvm/test/CodeGen/AMDGPU/isel-amdgpu-cs-chain-intrinsic-dyn-vgpr-w32.ll
M llvm/test/CodeGen/AMDGPU/isel-amdgpu-cs-chain-preserve-cc.ll
M llvm/test/CodeGen/AMDGPU/issue92561-restore-undef-scc-verifier-error.ll
M llvm/test/CodeGen/AMDGPU/issue98474-need-live-out-undef-subregister-def.ll
M llvm/test/CodeGen/AMDGPU/kernarg-stack-alignment.ll
M llvm/test/CodeGen/AMDGPU/kernel-args.ll
M llvm/test/CodeGen/AMDGPU/kernel-argument-dag-lowering.ll
M llvm/test/CodeGen/AMDGPU/kernel-vgpr-spill-mubuf-with-voffset.ll
M llvm/test/CodeGen/AMDGPU/kill-infinite-loop.ll
M llvm/test/CodeGen/AMDGPU/known-never-nan.ll
M llvm/test/CodeGen/AMDGPU/known-never-snan.ll
M llvm/test/CodeGen/AMDGPU/lds-bounds.ll
M llvm/test/CodeGen/AMDGPU/lds-frame-extern.ll
M llvm/test/CodeGen/AMDGPU/lds-global-non-entry-func.ll
M llvm/test/CodeGen/AMDGPU/lds-m0-init-in-loop.ll
M llvm/test/CodeGen/AMDGPU/lds-misaligned-bug.ll
M llvm/test/CodeGen/AMDGPU/lds-oqap-crash.ll
M llvm/test/CodeGen/AMDGPU/lds-output-queue.ll
M llvm/test/CodeGen/AMDGPU/lds-relocs.ll
M llvm/test/CodeGen/AMDGPU/lds-size-hsa-gfx950.ll
M llvm/test/CodeGen/AMDGPU/lds-size-pal-gfx950.ll
M llvm/test/CodeGen/AMDGPU/lds-zero-initializer.ll
M llvm/test/CodeGen/AMDGPU/legalize-amdgcn.raw.buffer.load.format.f16.ll
M llvm/test/CodeGen/AMDGPU/legalize-amdgcn.raw.buffer.load.format.ll
M llvm/test/CodeGen/AMDGPU/legalize-amdgcn.raw.buffer.load.ll
M llvm/test/CodeGen/AMDGPU/legalize-amdgcn.raw.buffer.store.format.f16.ll
M llvm/test/CodeGen/AMDGPU/legalize-amdgcn.raw.buffer.store.format.f32.ll
M llvm/test/CodeGen/AMDGPU/legalize-amdgcn.raw.buffer.store.ll
M llvm/test/CodeGen/AMDGPU/legalize-amdgcn.raw.ptr.buffer.load.format.f16.ll
M llvm/test/CodeGen/AMDGPU/legalize-amdgcn.raw.ptr.buffer.load.format.ll
M llvm/test/CodeGen/AMDGPU/legalize-amdgcn.raw.ptr.buffer.load.ll
M llvm/test/CodeGen/AMDGPU/legalize-amdgcn.raw.ptr.buffer.store.format.f16.ll
M llvm/test/CodeGen/AMDGPU/legalize-amdgcn.raw.ptr.buffer.store.format.f32.ll
M llvm/test/CodeGen/AMDGPU/legalize-amdgcn.raw.ptr.buffer.store.ll
M llvm/test/CodeGen/AMDGPU/legalize-amdgcn.raw.ptr.tbuffer.load.f16.ll
M llvm/test/CodeGen/AMDGPU/legalize-amdgcn.raw.ptr.tbuffer.load.ll
M llvm/test/CodeGen/AMDGPU/legalize-amdgcn.raw.ptr.tbuffer.store.f16.ll
M llvm/test/CodeGen/AMDGPU/legalize-amdgcn.raw.ptr.tbuffer.store.ll
M llvm/test/CodeGen/AMDGPU/legalize-amdgcn.raw.tbuffer.load.f16.ll
M llvm/test/CodeGen/AMDGPU/legalize-amdgcn.raw.tbuffer.load.ll
M llvm/test/CodeGen/AMDGPU/legalize-amdgcn.raw.tbuffer.store.f16.ll
M llvm/test/CodeGen/AMDGPU/legalize-amdgcn.raw.tbuffer.store.ll
M llvm/test/CodeGen/AMDGPU/legalize-fp-load-invariant.ll
M llvm/test/CodeGen/AMDGPU/legalize-soffset-mbuf.ll
M llvm/test/CodeGen/AMDGPU/literal-constant-like-operand-instruction-size.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.alignbyte.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.atomic.cond.sub.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.atomic.dec.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.atomic.inc.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.bitop3.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.bitreplicate.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.buffer.load.dwordx3.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.buffer.store.dwordx3.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.class.f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.class.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cos.f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cos.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cubeid.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cubema.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cubesc.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cubetc.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.fp8.dpp.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.fp8.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.pk.i16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.pk.u16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.pknorm.i16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.pknorm.u16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.pkrtz.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.scalef32.pk.gfx950.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.scalef32.pk.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.scalef32.sr.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.scalef32.sr.pk.gfx950.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.scalef32.sr.pk.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.dispatch.ptr.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.div.fixup.f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.div.fixup.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.div.fmas.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.div.scale.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.dot4.f32.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.ds.add.gs.reg.rtn.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.ds.append.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.ds.bpermute.fi.b32.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.ds.bpermute.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.ds.bvh.stack.rtn.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.ds.consume.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.ds.gws.barrier-fastregalloc.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.ds.gws.barrier.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.ds.gws.init.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.ds.gws.sema.br.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.ds.gws.sema.p.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.ds.gws.sema.release.all.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.ds.gws.sema.v.ll
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M llvm/test/CodeGen/AMDGPU/load-range-metadata-assert.ll
M llvm/test/CodeGen/AMDGPU/load-select-ptr.ll
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M llvm/test/CodeGen/AMDGPU/local-atomics.ll
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M llvm/test/CodeGen/AMDGPU/local-memory.amdgcn.ll
M llvm/test/CodeGen/AMDGPU/local-memory.ll
M llvm/test/CodeGen/AMDGPU/local-stack-slot-offset.ll
M llvm/test/CodeGen/AMDGPU/long-branch-reserve-register.ll
M llvm/test/CodeGen/AMDGPU/loop-idiom.ll
M llvm/test/CodeGen/AMDGPU/loop-live-out-copy-undef-subrange.ll
M llvm/test/CodeGen/AMDGPU/loop-prefetch.ll
M llvm/test/CodeGen/AMDGPU/loop_break.ll
M llvm/test/CodeGen/AMDGPU/loop_exit_with_xor.ll
M llvm/test/CodeGen/AMDGPU/lower-buffer-fat-pointers-nontemporal-metadata.ll
M llvm/test/CodeGen/AMDGPU/lower-module-lds-offsets.ll
M llvm/test/CodeGen/AMDGPU/lower-module-lds-via-hybrid.ll
M llvm/test/CodeGen/AMDGPU/lower-module-lds-via-table.ll
M llvm/test/CodeGen/AMDGPU/lower-work-group-id-intrinsics-hsa.ll
M llvm/test/CodeGen/AMDGPU/lower-work-group-id-intrinsics-pal.ll
M llvm/test/CodeGen/AMDGPU/lshl-add-u64.ll
M llvm/test/CodeGen/AMDGPU/lshl64-to-32.ll
M llvm/test/CodeGen/AMDGPU/lshr.v2i16.ll
M llvm/test/CodeGen/AMDGPU/mad-combine.ll
M llvm/test/CodeGen/AMDGPU/mad-mix-hi.ll
M llvm/test/CodeGen/AMDGPU/mad-mix-lo.ll
M llvm/test/CodeGen/AMDGPU/mad-mix.ll
M llvm/test/CodeGen/AMDGPU/mad.u16.ll
M llvm/test/CodeGen/AMDGPU/mad24-get-global-id.ll
M llvm/test/CodeGen/AMDGPU/mad_64_32.ll
M llvm/test/CodeGen/AMDGPU/mad_int24.ll
M llvm/test/CodeGen/AMDGPU/mad_u64_u32.ll
M llvm/test/CodeGen/AMDGPU/mad_uint24.ll
M llvm/test/CodeGen/AMDGPU/madak.ll
M llvm/test/CodeGen/AMDGPU/madmk.ll
M llvm/test/CodeGen/AMDGPU/mai-inline.ll
M llvm/test/CodeGen/AMDGPU/match-perm-extract-vector-elt-bug.ll
M llvm/test/CodeGen/AMDGPU/max-sgprs.ll
M llvm/test/CodeGen/AMDGPU/max.i16.ll
M llvm/test/CodeGen/AMDGPU/max.ll
M llvm/test/CodeGen/AMDGPU/med3-no-simplify.ll
M llvm/test/CodeGen/AMDGPU/memory_clause.ll
M llvm/test/CodeGen/AMDGPU/merge-out-of-order-ldst.ll
M llvm/test/CodeGen/AMDGPU/merge-store-crash.ll
M llvm/test/CodeGen/AMDGPU/merge-store-usedef.ll
M llvm/test/CodeGen/AMDGPU/merge-stores.ll
M llvm/test/CodeGen/AMDGPU/mesa3d.ll
M llvm/test/CodeGen/AMDGPU/mesa_regression.ll
M llvm/test/CodeGen/AMDGPU/mfma-bf16-vgpr-cd-select.ll
M llvm/test/CodeGen/AMDGPU/mfma-cd-select.ll
M llvm/test/CodeGen/AMDGPU/mfma-loop.ll
M llvm/test/CodeGen/AMDGPU/mfma-no-register-aliasing.ll
M llvm/test/CodeGen/AMDGPU/mfma-vgpr-cd-select-gfx942.ll
M llvm/test/CodeGen/AMDGPU/mfma-vgpr-cd-select.ll
M llvm/test/CodeGen/AMDGPU/min-waves-per-eu-not-respected.ll
M llvm/test/CodeGen/AMDGPU/min.ll
M llvm/test/CodeGen/AMDGPU/minimummaximum.ll
M llvm/test/CodeGen/AMDGPU/minmax.ll
M llvm/test/CodeGen/AMDGPU/missing-store.ll
M llvm/test/CodeGen/AMDGPU/mixed-vmem-types.ll
M llvm/test/CodeGen/AMDGPU/mixed-wave32-wave64.ll
M llvm/test/CodeGen/AMDGPU/mixed_wave32_wave64.ll
M llvm/test/CodeGen/AMDGPU/module-lds-false-sharing.ll
M llvm/test/CodeGen/AMDGPU/move-to-valu-addsubu64.ll
M llvm/test/CodeGen/AMDGPU/move-to-valu-atomicrmw-system.ll
M llvm/test/CodeGen/AMDGPU/move-to-valu-atomicrmw.ll
M llvm/test/CodeGen/AMDGPU/move-to-valu-ctlz-cttz.ll
M llvm/test/CodeGen/AMDGPU/move-to-valu-pseudo-scalar-trans-f16-fake16.ll
M llvm/test/CodeGen/AMDGPU/move-to-valu-pseudo-scalar-trans-f16-true16.ll
M llvm/test/CodeGen/AMDGPU/move-to-valu-pseudo-scalar-trans.ll
M llvm/test/CodeGen/AMDGPU/move-to-valu-vimage-vsample.ll
M llvm/test/CodeGen/AMDGPU/move-to-valu-worklist.ll
M llvm/test/CodeGen/AMDGPU/movreld-bug.ll
M llvm/test/CodeGen/AMDGPU/mubuf-legalize-operands-non-ptr-intrinsics.ll
M llvm/test/CodeGen/AMDGPU/mubuf-legalize-operands.ll
M llvm/test/CodeGen/AMDGPU/mubuf-shader-vgpr-non-ptr-intrinsics.ll
M llvm/test/CodeGen/AMDGPU/mubuf-shader-vgpr.ll
M llvm/test/CodeGen/AMDGPU/mubuf.ll
M llvm/test/CodeGen/AMDGPU/mul.i16.ll
M llvm/test/CodeGen/AMDGPU/mul.ll
M llvm/test/CodeGen/AMDGPU/mul24-pass-ordering.ll
M llvm/test/CodeGen/AMDGPU/mul_int24.ll
M llvm/test/CodeGen/AMDGPU/mul_uint24-amdgcn.ll
M llvm/test/CodeGen/AMDGPU/multi-divergent-exit-region.ll
M llvm/test/CodeGen/AMDGPU/multilevel-break.ll
M llvm/test/CodeGen/AMDGPU/nand.ll
M llvm/test/CodeGen/AMDGPU/need-fp-from-vgpr-spills.ll
M llvm/test/CodeGen/AMDGPU/nested-calls.ll
M llvm/test/CodeGen/AMDGPU/nested-loop-conditions.ll
M llvm/test/CodeGen/AMDGPU/no-dup-inst-prefetch.ll
M llvm/test/CodeGen/AMDGPU/no-shrink-extloads.ll
M llvm/test/CodeGen/AMDGPU/no-source-locations-in-prologue.ll
M llvm/test/CodeGen/AMDGPU/noclobber-barrier.ll
M llvm/test/CodeGen/AMDGPU/non-entry-alloca.ll
M llvm/test/CodeGen/AMDGPU/noop-shader-O0.ll
M llvm/test/CodeGen/AMDGPU/nor.ll
M llvm/test/CodeGen/AMDGPU/nsa-reassign.ll
M llvm/test/CodeGen/AMDGPU/nullptr.ll
M llvm/test/CodeGen/AMDGPU/offset-split-flat.ll
M llvm/test/CodeGen/AMDGPU/offset-split-global.ll
M llvm/test/CodeGen/AMDGPU/omod.ll
M llvm/test/CodeGen/AMDGPU/opencl-image-metadata.ll
M llvm/test/CodeGen/AMDGPU/operand-folding.ll
M llvm/test/CodeGen/AMDGPU/operand-spacing.ll
M llvm/test/CodeGen/AMDGPU/optimize-compare.ll
M llvm/test/CodeGen/AMDGPU/optimize-negated-cond.ll
M llvm/test/CodeGen/AMDGPU/or.ll
M llvm/test/CodeGen/AMDGPU/or3.ll
M llvm/test/CodeGen/AMDGPU/overlapping-tuple-copy-implicit-op-failure.ll
M llvm/test/CodeGen/AMDGPU/pack.v2f16.ll
M llvm/test/CodeGen/AMDGPU/pack.v2i16.ll
M llvm/test/CodeGen/AMDGPU/packed-fp32.ll
M llvm/test/CodeGen/AMDGPU/pal-metadata-3.0-callable-dvgpr.ll
M llvm/test/CodeGen/AMDGPU/pal-metadata-3.0-callable.ll
M llvm/test/CodeGen/AMDGPU/parallelandifcollapse.ll
M llvm/test/CodeGen/AMDGPU/partial-regcopy-and-spill-missed-at-regalloc.ll
M llvm/test/CodeGen/AMDGPU/partial-sgpr-to-vgpr-spills.ll
M llvm/test/CodeGen/AMDGPU/partial-shift-shrink.ll
M llvm/test/CodeGen/AMDGPU/partially-dead-super-register-immediate.ll
M llvm/test/CodeGen/AMDGPU/permlane16_opsel.ll
M llvm/test/CodeGen/AMDGPU/permute.ll
M llvm/test/CodeGen/AMDGPU/permute_i8.ll
M llvm/test/CodeGen/AMDGPU/pk_max_f16_literal.ll
M llvm/test/CodeGen/AMDGPU/post-ra-soft-clause-dbg-info.ll
M llvm/test/CodeGen/AMDGPU/preload-kernargs.ll
M llvm/test/CodeGen/AMDGPU/preserve-hi16.ll
M llvm/test/CodeGen/AMDGPU/preserve-user-waitcnt.ll
M llvm/test/CodeGen/AMDGPU/preserve-wwm-copy-dst-reg.ll
M llvm/test/CodeGen/AMDGPU/private-access-no-objects.ll
M llvm/test/CodeGen/AMDGPU/prologue-epilogue-markers.ll
M llvm/test/CodeGen/AMDGPU/promote-alloca-stored-pointer-value.ll
M llvm/test/CodeGen/AMDGPU/promote-alloca-vector-to-vector.ll
M llvm/test/CodeGen/AMDGPU/promote-constOffset-to-imm.ll
M llvm/test/CodeGen/AMDGPU/promote-vect3-load.ll
M llvm/test/CodeGen/AMDGPU/propagate-attributes-bitcast-function.ll
M llvm/test/CodeGen/AMDGPU/ps-shader-arg-count.ll
M llvm/test/CodeGen/AMDGPU/ptr-buffer-alias-scheduling.ll
M llvm/test/CodeGen/AMDGPU/r600-constant-array-fixup.ll
M llvm/test/CodeGen/AMDGPU/r600.bitcast.ll
M llvm/test/CodeGen/AMDGPU/r600.extract-lowbits.ll
M llvm/test/CodeGen/AMDGPU/r600.global_atomics.ll
M llvm/test/CodeGen/AMDGPU/r600.sub.ll
M llvm/test/CodeGen/AMDGPU/r600.work-item-intrinsics.ll
M llvm/test/CodeGen/AMDGPU/ran-out-of-registers-error-all-regs-reserved.ll
M llvm/test/CodeGen/AMDGPU/rcp_iflag.ll
M llvm/test/CodeGen/AMDGPU/read-register-invalid-subtarget.ll
M llvm/test/CodeGen/AMDGPU/read-register-invalid-type-i32.ll
M llvm/test/CodeGen/AMDGPU/read-register-invalid-type-i64.ll
M llvm/test/CodeGen/AMDGPU/read_register.ll
M llvm/test/CodeGen/AMDGPU/readcyclecounter.ll
M llvm/test/CodeGen/AMDGPU/readsteadycounter.ll
M llvm/test/CodeGen/AMDGPU/reassoc-scalar.ll
M llvm/test/CodeGen/AMDGPU/recursion.ll
M llvm/test/CodeGen/AMDGPU/reduce-build-vec-ext-to-ext-build-vec.ll
M llvm/test/CodeGen/AMDGPU/reduce-load-width-alignment.ll
M llvm/test/CodeGen/AMDGPU/reduce-store-width-alignment.ll
M llvm/test/CodeGen/AMDGPU/reduction.ll
M llvm/test/CodeGen/AMDGPU/regalloc-illegal-eviction-assert.ll
M llvm/test/CodeGen/AMDGPU/register-count-comments.ll
M llvm/test/CodeGen/AMDGPU/register-killed-error-after-alloc-failure1.ll
M llvm/test/CodeGen/AMDGPU/reject-agpr-usage-before-gfx908.ll
M llvm/test/CodeGen/AMDGPU/rel32.ll
M llvm/test/CodeGen/AMDGPU/remaining-virtual-register-operands.ll
M llvm/test/CodeGen/AMDGPU/remat-fp64-constants.ll
M llvm/test/CodeGen/AMDGPU/remove-incompatible-extended-image-insts.ll
M llvm/test/CodeGen/AMDGPU/remove-incompatible-functions.ll
M llvm/test/CodeGen/AMDGPU/remove-incompatible-gws.ll
M llvm/test/CodeGen/AMDGPU/remove-incompatible-s-time.ll
M llvm/test/CodeGen/AMDGPU/remove-incompatible-wave32-feature.ll
M llvm/test/CodeGen/AMDGPU/rename-disconnected-bug.ll
M llvm/test/CodeGen/AMDGPU/resource-usage-pal.ll
M llvm/test/CodeGen/AMDGPU/ret.ll
M llvm/test/CodeGen/AMDGPU/ret_jump.ll
M llvm/test/CodeGen/AMDGPU/returnaddress.ll
M llvm/test/CodeGen/AMDGPU/rotate-add.ll
M llvm/test/CodeGen/AMDGPU/rotl.i64.ll
M llvm/test/CodeGen/AMDGPU/rotl.ll
M llvm/test/CodeGen/AMDGPU/rotr.i64.ll
M llvm/test/CodeGen/AMDGPU/rotr.ll
M llvm/test/CodeGen/AMDGPU/s-getpc-b64-remat.ll
M llvm/test/CodeGen/AMDGPU/s_addk_i32.ll
M llvm/test/CodeGen/AMDGPU/s_movk_i32.ll
M llvm/test/CodeGen/AMDGPU/s_mulk_i32.ll
M llvm/test/CodeGen/AMDGPU/sad.ll
M llvm/test/CodeGen/AMDGPU/saddo.ll
M llvm/test/CodeGen/AMDGPU/salu-to-valu.ll
M llvm/test/CodeGen/AMDGPU/save-fp.ll
M llvm/test/CodeGen/AMDGPU/scalar-branch-missing-and-exec.ll
M llvm/test/CodeGen/AMDGPU/scalar-float-sop1.ll
M llvm/test/CodeGen/AMDGPU/scalar-float-sop2.ll
M llvm/test/CodeGen/AMDGPU/scalar-float-sopc.ll
M llvm/test/CodeGen/AMDGPU/scalar_to_vector.ll
M llvm/test/CodeGen/AMDGPU/scalar_to_vector.v8i16.ll
M llvm/test/CodeGen/AMDGPU/scalar_to_vector_v2x16.ll
M llvm/test/CodeGen/AMDGPU/scc-clobbered-sgpr-to-vmem-spill.ll
M llvm/test/CodeGen/AMDGPU/sched-setprio.ll
M llvm/test/CodeGen/AMDGPU/schedule-avoid-spills.ll
M llvm/test/CodeGen/AMDGPU/schedule-fs-loop-nested-if.ll
M llvm/test/CodeGen/AMDGPU/schedule-fs-loop-nested.ll
M llvm/test/CodeGen/AMDGPU/schedule-fs-loop.ll
M llvm/test/CodeGen/AMDGPU/schedule-global-loads.ll
M llvm/test/CodeGen/AMDGPU/schedule-if-2.ll
M llvm/test/CodeGen/AMDGPU/schedule-if.ll
M llvm/test/CodeGen/AMDGPU/schedule-ilp.ll
M llvm/test/CodeGen/AMDGPU/schedule-kernel-arg-loads.ll
M llvm/test/CodeGen/AMDGPU/schedule-regpressure-lds.ll
M llvm/test/CodeGen/AMDGPU/schedule-regpressure-limit-clustering.ll
M llvm/test/CodeGen/AMDGPU/schedule-regpressure-limit.ll
M llvm/test/CodeGen/AMDGPU/schedule-regpressure-limit2.ll
M llvm/test/CodeGen/AMDGPU/schedule-regpressure-limit3.ll
M llvm/test/CodeGen/AMDGPU/schedule-regpressure-misched-max-waves.ll
M llvm/test/CodeGen/AMDGPU/schedule-relaxed-occupancy.ll
M llvm/test/CodeGen/AMDGPU/schedule-vs-if-nested-loop-failure.ll
M llvm/test/CodeGen/AMDGPU/schedule-xdl-resource.ll
M llvm/test/CodeGen/AMDGPU/scratch-buffer.ll
M llvm/test/CodeGen/AMDGPU/scratch-pointer-sink.ll
M llvm/test/CodeGen/AMDGPU/scratch-simple.ll
M llvm/test/CodeGen/AMDGPU/sdag-print-divergence.ll
M llvm/test/CodeGen/AMDGPU/sdiv64.ll
M llvm/test/CodeGen/AMDGPU/sdwa-op64-test.ll
M llvm/test/CodeGen/AMDGPU/sdwa-peephole.ll
M llvm/test/CodeGen/AMDGPU/select-constant-cttz.ll
M llvm/test/CodeGen/AMDGPU/select-fabs-fneg-extract-legacy.ll
M llvm/test/CodeGen/AMDGPU/select-fabs-fneg-extract.ll
M llvm/test/CodeGen/AMDGPU/select-i1.ll
M llvm/test/CodeGen/AMDGPU/select-opt.ll
M llvm/test/CodeGen/AMDGPU/select-vectors.ll
M llvm/test/CodeGen/AMDGPU/select.f16.ll
M llvm/test/CodeGen/AMDGPU/select64.ll
M llvm/test/CodeGen/AMDGPU/selectcc.ll
M llvm/test/CodeGen/AMDGPU/set-inactive-wwm-overwrite.ll
M llvm/test/CodeGen/AMDGPU/set_kill_i1_for_floation_point_comparison.ll
M llvm/test/CodeGen/AMDGPU/setcc-fneg-constant.ll
M llvm/test/CodeGen/AMDGPU/setcc-limit-load-shrink.ll
M llvm/test/CodeGen/AMDGPU/setcc-opt.ll
M llvm/test/CodeGen/AMDGPU/setcc-sext.ll
M llvm/test/CodeGen/AMDGPU/setcc.ll
M llvm/test/CodeGen/AMDGPU/setcc64.ll
M llvm/test/CodeGen/AMDGPU/seto.ll
M llvm/test/CodeGen/AMDGPU/setuo.ll
M llvm/test/CodeGen/AMDGPU/sext-divergence-driven-isel.ll
M llvm/test/CodeGen/AMDGPU/sext-eliminate.ll
M llvm/test/CodeGen/AMDGPU/sext-in-reg-failure-r600.ll
M llvm/test/CodeGen/AMDGPU/sext-in-reg.ll
M llvm/test/CodeGen/AMDGPU/sgpr-control-flow.ll
M llvm/test/CodeGen/AMDGPU/sgpr-copy-duplicate-operand.ll
M llvm/test/CodeGen/AMDGPU/sgpr-copy-local-cse.ll
M llvm/test/CodeGen/AMDGPU/sgpr-copy.ll
M llvm/test/CodeGen/AMDGPU/sgpr-regalloc-flags.ll
M llvm/test/CodeGen/AMDGPU/sgpr-spill-incorrect-fi-bookkeeping-bug.ll
M llvm/test/CodeGen/AMDGPU/sgpr-spill-no-vgprs.ll
M llvm/test/CodeGen/AMDGPU/sgpr-spill-update-only-slot-indexes.ll
M llvm/test/CodeGen/AMDGPU/sgpr-spills-split-regalloc.ll
M llvm/test/CodeGen/AMDGPU/sgprcopies.ll
M llvm/test/CodeGen/AMDGPU/shader-addr64-nonuniform.ll
M llvm/test/CodeGen/AMDGPU/shift-and-i128-ubfe.ll
M llvm/test/CodeGen/AMDGPU/shift-and-i64-ubfe.ll
M llvm/test/CodeGen/AMDGPU/shift-i128.ll
M llvm/test/CodeGen/AMDGPU/shift-select.ll
M llvm/test/CodeGen/AMDGPU/shl.ll
M llvm/test/CodeGen/AMDGPU/shl.v2i16.ll
M llvm/test/CodeGen/AMDGPU/shl_add.ll
M llvm/test/CodeGen/AMDGPU/shl_add_constant.ll
M llvm/test/CodeGen/AMDGPU/shl_add_ptr.ll
M llvm/test/CodeGen/AMDGPU/shl_add_ptr_csub.ll
M llvm/test/CodeGen/AMDGPU/shl_add_ptr_global.ll
M llvm/test/CodeGen/AMDGPU/shl_or.ll
M llvm/test/CodeGen/AMDGPU/should-not-hoist-set-inactive.ll
M llvm/test/CodeGen/AMDGPU/shufflevector-physreg-copy.ll
M llvm/test/CodeGen/AMDGPU/si-annotate-cf-kill.ll
M llvm/test/CodeGen/AMDGPU/si-annotate-cf-noloop.ll
M llvm/test/CodeGen/AMDGPU/si-annotate-cf-unreachable.ll
M llvm/test/CodeGen/AMDGPU/si-annotate-cf.ll
M llvm/test/CodeGen/AMDGPU/si-annotate-cfg-loop-assert.ll
M llvm/test/CodeGen/AMDGPU/si-instr-info-correct-implicit-operands.ll
M llvm/test/CodeGen/AMDGPU/si-lower-control-flow-kill.ll
M llvm/test/CodeGen/AMDGPU/si-lower-control-flow-unreachable-block.ll
M llvm/test/CodeGen/AMDGPU/si-sgpr-spill.ll
M llvm/test/CodeGen/AMDGPU/si-spill-cf.ll
M llvm/test/CodeGen/AMDGPU/si-triv-disjoint-mem-access.ll
M llvm/test/CodeGen/AMDGPU/si-unify-exit-multiple-unreachables.ll
M llvm/test/CodeGen/AMDGPU/si-unify-exit-return-unreachable.ll
M llvm/test/CodeGen/AMDGPU/si-vector-hang.ll
M llvm/test/CodeGen/AMDGPU/sibling-call.ll
M llvm/test/CodeGen/AMDGPU/sign_extend.ll
M llvm/test/CodeGen/AMDGPU/sink-image-sample.ll
M llvm/test/CodeGen/AMDGPU/sint_to_fp.f64.ll
M llvm/test/CodeGen/AMDGPU/sint_to_fp.i64.ll
M llvm/test/CodeGen/AMDGPU/sint_to_fp.ll
M llvm/test/CodeGen/AMDGPU/sitofp.f16.ll
M llvm/test/CodeGen/AMDGPU/skip-branch-trap.ll
M llvm/test/CodeGen/AMDGPU/skip-if-dead.ll
M llvm/test/CodeGen/AMDGPU/smed3.ll
M llvm/test/CodeGen/AMDGPU/smfmac_no_agprs.ll
M llvm/test/CodeGen/AMDGPU/sminmax.ll
M llvm/test/CodeGen/AMDGPU/smrd-gfx10.ll
M llvm/test/CodeGen/AMDGPU/smrd-vccz-bug.ll
M llvm/test/CodeGen/AMDGPU/smrd.ll
M llvm/test/CodeGen/AMDGPU/smrd_vmem_war.ll
M llvm/test/CodeGen/AMDGPU/sopk-compares.ll
M llvm/test/CodeGen/AMDGPU/sopk-no-literal.ll
M llvm/test/CodeGen/AMDGPU/spill-agpr.ll
M llvm/test/CodeGen/AMDGPU/spill-alloc-sgpr-init-bug.ll
M llvm/test/CodeGen/AMDGPU/spill-cfg-position.ll
M llvm/test/CodeGen/AMDGPU/spill-csr-frame-ptr-reg-copy.ll
M llvm/test/CodeGen/AMDGPU/spill-m0.ll
M llvm/test/CodeGen/AMDGPU/spill-vector-superclass.ll
M llvm/test/CodeGen/AMDGPU/spill-vgpr-to-agpr-update-regscavenger.ll
M llvm/test/CodeGen/AMDGPU/spill-vgpr-to-agpr.ll
M llvm/test/CodeGen/AMDGPU/spill-vgpr.ll
M llvm/test/CodeGen/AMDGPU/spill-wide-sgpr.ll
M llvm/test/CodeGen/AMDGPU/spill-writelane-vgprs.ll
M llvm/test/CodeGen/AMDGPU/spill_more_than_wavesize_csr_sgprs.ll
M llvm/test/CodeGen/AMDGPU/split-scalar-i64-add.ll
M llvm/test/CodeGen/AMDGPU/split-smrd.ll
M llvm/test/CodeGen/AMDGPU/split-vector-memoperand-offsets.ll
M llvm/test/CodeGen/AMDGPU/sra.ll
M llvm/test/CodeGen/AMDGPU/srem.ll
M llvm/test/CodeGen/AMDGPU/srem64.ll
M llvm/test/CodeGen/AMDGPU/srl.ll
M llvm/test/CodeGen/AMDGPU/ssubo.ll
M llvm/test/CodeGen/AMDGPU/stack-pointer-offset-relative-frameindex.ll
M llvm/test/CodeGen/AMDGPU/stack-realign.ll
M llvm/test/CodeGen/AMDGPU/store-barrier.ll
M llvm/test/CodeGen/AMDGPU/store-global.ll
M llvm/test/CodeGen/AMDGPU/store-hi16.ll
M llvm/test/CodeGen/AMDGPU/store-local.128.ll
M llvm/test/CodeGen/AMDGPU/store-local.96.ll
M llvm/test/CodeGen/AMDGPU/store-local.ll
M llvm/test/CodeGen/AMDGPU/store-private.ll
M llvm/test/CodeGen/AMDGPU/store-v3i64.ll
M llvm/test/CodeGen/AMDGPU/store-vector-ptrs.ll
M llvm/test/CodeGen/AMDGPU/store-weird-sizes.ll
M llvm/test/CodeGen/AMDGPU/sub-zext-cc-zext-cc.ll
M llvm/test/CodeGen/AMDGPU/sub.i16.ll
M llvm/test/CodeGen/AMDGPU/sub.ll
M llvm/test/CodeGen/AMDGPU/sub.v2i16.ll
M llvm/test/CodeGen/AMDGPU/sub_i1.ll
M llvm/test/CodeGen/AMDGPU/swdev373493.ll
M llvm/test/CodeGen/AMDGPU/swdev503538-move-to-valu-stack-srd-physreg.ll
M llvm/test/CodeGen/AMDGPU/switch-default-block-unreachable.ll
M llvm/test/CodeGen/AMDGPU/switch-unreachable.ll
M llvm/test/CodeGen/AMDGPU/swizzle.bit.extract.ll
M llvm/test/CodeGen/AMDGPU/tail-call-amdgpu-gfx.ll
M llvm/test/CodeGen/AMDGPU/tail-call-inreg-arguments.error.ll
M llvm/test/CodeGen/AMDGPU/tail-call-inreg-arguments.ll
M llvm/test/CodeGen/AMDGPU/tail-call-uniform-target-in-vgprs-issue110930.ll
M llvm/test/CodeGen/AMDGPU/target-cpu.ll
M llvm/test/CodeGen/AMDGPU/token-factor-inline-limit-test.ll
M llvm/test/CodeGen/AMDGPU/transform-block-with-return-to-epilog.ll
M llvm/test/CodeGen/AMDGPU/trap-abis.ll
M llvm/test/CodeGen/AMDGPU/trap.ll
M llvm/test/CodeGen/AMDGPU/trunc-bitcast-vector.ll
M llvm/test/CodeGen/AMDGPU/trunc-cmp-constant.ll
M llvm/test/CodeGen/AMDGPU/trunc-combine.ll
M llvm/test/CodeGen/AMDGPU/trunc-store-f64-to-f16.ll
M llvm/test/CodeGen/AMDGPU/trunc-store-i1.ll
M llvm/test/CodeGen/AMDGPU/trunc-store-i64.ll
M llvm/test/CodeGen/AMDGPU/trunc-store-vec-i16-to-i8.ll
M llvm/test/CodeGen/AMDGPU/trunc.ll
M llvm/test/CodeGen/AMDGPU/twoaddr-constrain.ll
M llvm/test/CodeGen/AMDGPU/uaddo.ll
M llvm/test/CodeGen/AMDGPU/udiv.ll
M llvm/test/CodeGen/AMDGPU/udiv64.ll
M llvm/test/CodeGen/AMDGPU/udivrem.ll
M llvm/test/CodeGen/AMDGPU/udivrem24.ll
M llvm/test/CodeGen/AMDGPU/uint_to_fp.f64.ll
M llvm/test/CodeGen/AMDGPU/uint_to_fp.i64.ll
M llvm/test/CodeGen/AMDGPU/uint_to_fp.ll
M llvm/test/CodeGen/AMDGPU/uitofp.f16.ll
M llvm/test/CodeGen/AMDGPU/umed3.ll
M llvm/test/CodeGen/AMDGPU/unaligned-load-store.ll
M llvm/test/CodeGen/AMDGPU/undefined-subreg-liverange.ll
M llvm/test/CodeGen/AMDGPU/unhandled-loop-condition-assertion.ll
M llvm/test/CodeGen/AMDGPU/uniform-branch-intrinsic-cond.ll
M llvm/test/CodeGen/AMDGPU/uniform-cfg.ll
M llvm/test/CodeGen/AMDGPU/uniform-crash.ll
M llvm/test/CodeGen/AMDGPU/uniform-load-from-tid.ll
M llvm/test/CodeGen/AMDGPU/uniform-phi-with-undef.ll
M llvm/test/CodeGen/AMDGPU/unigine-liveness-crash.ll
M llvm/test/CodeGen/AMDGPU/unknown-processor.ll
M llvm/test/CodeGen/AMDGPU/unpack-half.ll
M llvm/test/CodeGen/AMDGPU/unstructured-cfg-def-use-issue.ll
M llvm/test/CodeGen/AMDGPU/unsupported-calls.ll
M llvm/test/CodeGen/AMDGPU/unsupported-cs-chain.ll
M llvm/test/CodeGen/AMDGPU/unsupported-image-a16.ll
M llvm/test/CodeGen/AMDGPU/unsupported-image-g16.ll
M llvm/test/CodeGen/AMDGPU/unsupported-image-sample.ll
M llvm/test/CodeGen/AMDGPU/urem.ll
M llvm/test/CodeGen/AMDGPU/urem64.ll
M llvm/test/CodeGen/AMDGPU/use-sgpr-multiple-times.ll
M llvm/test/CodeGen/AMDGPU/usubo.ll
M llvm/test/CodeGen/AMDGPU/v1024.ll
M llvm/test/CodeGen/AMDGPU/v_add_u64_pseudo_sdwa.ll
M llvm/test/CodeGen/AMDGPU/v_ashr_pk.ll
M llvm/test/CodeGen/AMDGPU/v_cmp_gfx11.ll
M llvm/test/CodeGen/AMDGPU/v_cndmask.ll
M llvm/test/CodeGen/AMDGPU/v_cvt_pk_u8_f32.ll
M llvm/test/CodeGen/AMDGPU/v_mac.ll
M llvm/test/CodeGen/AMDGPU/v_mac_f16.ll
M llvm/test/CodeGen/AMDGPU/v_madak_f16.ll
M llvm/test/CodeGen/AMDGPU/v_pack.ll
M llvm/test/CodeGen/AMDGPU/v_sat_pk_u8_i16.ll
M llvm/test/CodeGen/AMDGPU/v_sub_u64_pseudo_sdwa.ll
M llvm/test/CodeGen/AMDGPU/v_swap_b16.ll
M llvm/test/CodeGen/AMDGPU/valu-i1.ll
M llvm/test/CodeGen/AMDGPU/vcmp-saveexec-to-vcmpx.ll
M llvm/test/CodeGen/AMDGPU/vector-alloca-bitcast.ll
M llvm/test/CodeGen/AMDGPU/vector-alloca.ll
M llvm/test/CodeGen/AMDGPU/vector-extract-insert.ll
M llvm/test/CodeGen/AMDGPU/vector_shuffle.packed.ll
M llvm/test/CodeGen/AMDGPU/vectorize-global-local.ll
M llvm/test/CodeGen/AMDGPU/vectorize-loads.ll
M llvm/test/CodeGen/AMDGPU/vgpr-large-tuple-alloc-error.ll
M llvm/test/CodeGen/AMDGPU/vgpr-liverange-ir.ll
M llvm/test/CodeGen/AMDGPU/vgpr-liverange.ll
M llvm/test/CodeGen/AMDGPU/vgpr-spill-emergency-stack-slot-compute.ll
M llvm/test/CodeGen/AMDGPU/vgpr-spill-emergency-stack-slot.ll
M llvm/test/CodeGen/AMDGPU/vgpr-tuple-allocation.ll
M llvm/test/CodeGen/AMDGPU/vop-shrink.ll
M llvm/test/CodeGen/AMDGPU/vopc_dpp.ll
M llvm/test/CodeGen/AMDGPU/vselect.ll
M llvm/test/CodeGen/AMDGPU/wait-before-stores-with-scope_sys.ll
M llvm/test/CodeGen/AMDGPU/wait.ll
M llvm/test/CodeGen/AMDGPU/waitcnt-vscnt.ll
M llvm/test/CodeGen/AMDGPU/waterfall_kills_scc.ll
M llvm/test/CodeGen/AMDGPU/wave32.ll
M llvm/test/CodeGen/AMDGPU/wave_dispatch_regs.ll
M llvm/test/CodeGen/AMDGPU/while-break.ll
M llvm/test/CodeGen/AMDGPU/whole-wave-functions.ll
M llvm/test/CodeGen/AMDGPU/whole-wave-register-copy.ll
M llvm/test/CodeGen/AMDGPU/whole-wave-register-spill.ll
M llvm/test/CodeGen/AMDGPU/widen-smrd-loads.ll
M llvm/test/CodeGen/AMDGPU/widen-vselect-and-mask.ll
M llvm/test/CodeGen/AMDGPU/wmma-gfx12-w32-f16-f32-matrix-modifiers.ll
M llvm/test/CodeGen/AMDGPU/wmma-gfx12-w32-imm.ll
M llvm/test/CodeGen/AMDGPU/wmma-gfx12-w32-iu-modifiers.ll
M llvm/test/CodeGen/AMDGPU/wmma-gfx12-w32-swmmac-index_key.ll
M llvm/test/CodeGen/AMDGPU/wmma-gfx12-w32.ll
M llvm/test/CodeGen/AMDGPU/wmma-gfx12-w64-f16-f32-matrix-modifiers.ll
M llvm/test/CodeGen/AMDGPU/wmma-gfx12-w64-imm.ll
M llvm/test/CodeGen/AMDGPU/wmma-gfx12-w64-iu-modifiers.ll
M llvm/test/CodeGen/AMDGPU/wmma-gfx12-w64-swmmac-index_key.ll
M llvm/test/CodeGen/AMDGPU/wmma-gfx12-w64.ll
M llvm/test/CodeGen/AMDGPU/wmma_modifiers.ll
M llvm/test/CodeGen/AMDGPU/wmma_multiple_32.ll
M llvm/test/CodeGen/AMDGPU/wmma_multiple_64.ll
M llvm/test/CodeGen/AMDGPU/workgroup-id-in-arch-sgprs.ll
M llvm/test/CodeGen/AMDGPU/wqm-gfx11.ll
M llvm/test/CodeGen/AMDGPU/wqm.ll
M llvm/test/CodeGen/AMDGPU/write-register-vgpr-into-sgpr.ll
M llvm/test/CodeGen/AMDGPU/write_register.ll
M llvm/test/CodeGen/AMDGPU/wwm-reserved-spill.ll
M llvm/test/CodeGen/AMDGPU/wwm-reserved.ll
M llvm/test/CodeGen/AMDGPU/xnor.ll
M llvm/test/CodeGen/AMDGPU/xor3-i1-const.ll
M llvm/test/CodeGen/AMDGPU/xor3.ll
M llvm/test/CodeGen/AMDGPU/xor_add.ll
M llvm/test/CodeGen/AMDGPU/zero_extend.ll
M llvm/test/CodeGen/AMDGPU/zext-divergence-driven-isel.ll
M llvm/test/CodeGen/AMDGPU/zext-i64-bit-operand.ll
Log Message:
-----------
[RFC][NFC][AMDGPU] Remove `-verify-machineinstrs` from `llvm/test/CodeGen/AMDGPU/*.ll` (#150024)
Recent upstream trends have moved away from explicitly using `-verify-machineinstrs`, as it's already covered by the expensive checks. This PR removes almost all `-verify-machineinstrs` from tests in `llvm/test/CodeGen/AMDGPU/*.ll`, leaving only those tests where its removal currently causes failures.
Commit: f9d0bd02d966e5c28aca9a6ceadd5ffec6aa9f78
https://github.com/llvm/llvm-project/commit/f9d0bd02d966e5c28aca9a6ceadd5ffec6aa9f78
Author: Sterling-Augustine <56981066+Sterling-Augustine at users.noreply.github.com>
Date: 2025-07-23 (Wed, 23 Jul 2025)
Changed paths:
M llvm/include/llvm/MC/MCObjectStreamer.h
M llvm/include/llvm/MC/MCStreamer.h
M llvm/include/llvm/MC/MCTargetOptions.h
M llvm/include/llvm/MC/MCTargetOptionsCommandFlags.h
M llvm/lib/CodeGen/AsmPrinter/ARMException.cpp
M llvm/lib/CodeGen/AsmPrinter/DwarfCFIException.cpp
M llvm/lib/MC/MCAsmStreamer.cpp
M llvm/lib/MC/MCObjectStreamer.cpp
M llvm/lib/MC/MCParser/AsmParser.cpp
M llvm/lib/MC/MCStreamer.cpp
M llvm/lib/MC/MCTargetOptionsCommandFlags.cpp
M llvm/test/MC/ELF/AArch64/cfi.s
M llvm/test/MC/ELF/cfi.s
Log Message:
-----------
Support SFrame command-line and .cfi_section syntax (#149935)
This PR adds support for the llvm-mc command-line flag "--gsframe" and
adds ".sframe" to the legal values passed ".cfi_section". It plumbs the
option through the cfi handling code a fair amount. Code to support
actual section generation follows in a future PR.
These options match the gnu-assembler's support syntax for sframes, on
both the command line and in assembly files.
First in a series of changes that will allow llvm-mc to produce sframe
.cfi sections. For more information about sframes, see
https://sourceware.org/binutils/docs-2.44/sframe-spec.html
and the llvm-RFC here:
https://discourse.llvm.org/t/rfc-adding-sframe-support-to-llvm/86900
Commit: 45d99c26c3513945a454e90b69d48257886f8284
https://github.com/llvm/llvm-project/commit/45d99c26c3513945a454e90b69d48257886f8284
Author: David Pagan <dave.pagan at amd.com>
Date: 2025-07-23 (Wed, 23 Jul 2025)
Changed paths:
M clang/docs/OpenMPSupport.rst
M clang/docs/ReleaseNotes.rst
M clang/lib/Sema/SemaOpenMP.cpp
A clang/test/OpenMP/target_map_array_section_no_length_codegen.cpp
M clang/test/OpenMP/target_map_messages.cpp
Log Message:
-----------
[clang][OpenMP] In 6.0, can omit length in array section (#148048)
In OpenMP 6.0 specification, section 5.2.5 Array Sections, page 166,
lines 28-28:
When the length is absent and the size of the dimension is not known,
the array section is an assumed-size array.
Testing
- Updated LIT test
- check-all
- OpenMP_VV (formerly sollve) test case
tests/6.0/target/test_target_assumed_array_size.c
Commit: 65dec9956273309158f3feba6ea8f150ce995a2a
https://github.com/llvm/llvm-project/commit/65dec9956273309158f3feba6ea8f150ce995a2a
Author: Nishant Patel <nishant.b.patel at intel.com>
Date: 2025-07-23 (Wed, 23 Jul 2025)
Changed paths:
M mlir/include/mlir/Dialect/XeGPU/IR/XeGPUAttrs.td
M mlir/lib/Dialect/XeGPU/IR/XeGPUDialect.cpp
M mlir/lib/Dialect/XeGPU/Transforms/XeGPUWgToSgDistribute.cpp
M mlir/test/Dialect/XeGPU/xegpu-wg-to-sg.mlir
Log Message:
-----------
[MLIR][XeGPU] Add support for subgroup_id_range (#148661)
This PR adds a new attribute to the xegpu dialect called xegpu.range.
One use case of this attribute can be to attach subgroup_id_range to
scf.if of to drive the execution.
Commit: 6a9817113838a3f87e803ac71aab46b3ccf24686
https://github.com/llvm/llvm-project/commit/6a9817113838a3f87e803ac71aab46b3ccf24686
Author: Victor Chernyakin <chernyakin.victor.j at outlook.com>
Date: 2025-07-23 (Wed, 23 Jul 2025)
Changed paths:
M clang-tools-extra/clang-tidy/misc/HeaderIncludeCycleCheck.cpp
M clang-tools-extra/docs/ReleaseNotes.rst
Log Message:
-----------
[clang-tidy] Speed up `misc-header-include-cycle` (#148757)
Performance optimization of misc-header-include-cycle
based on clangd test on Sema.cpp. Check were slow due
calls to SM.translateFile. Cost reduction (+-) from 11% to 3%.
Commit: df1dd803b6a1b1dd514da5e7c1257c0b75592452
https://github.com/llvm/llvm-project/commit/df1dd803b6a1b1dd514da5e7c1257c0b75592452
Author: Joseph Huber <huberjn at outlook.com>
Date: 2025-07-23 (Wed, 23 Jul 2025)
Changed paths:
M libc/src/__support/GPU/allocator.cpp
Log Message:
-----------
[libc] Cache the most recently used slot for a chunk size (#149751)
Summary:
This patch changes the `find_slab` logic to simply cache the most
successful slot. This means the happy fast path is now a single atomic
load on this index. I removed the SIMT shuffling logic that did slab
lookups wave-parallel. Here I am considering the actual traversal to be
comparatively unlikely, so it's not overly bad that it takes longer.
ideally one thread finds a slot and shared it with the rest so we only
pay that cost once.
---------
Co-authored-by: Shilei Tian <i at tianshilei.me>
Commit: ce52f9cdc4c6873d1d5b3a970393d4b6aff12e70
https://github.com/llvm/llvm-project/commit/ce52f9cdc4c6873d1d5b3a970393d4b6aff12e70
Author: Joseph Huber <huberjn at outlook.com>
Date: 2025-07-23 (Wed, 23 Jul 2025)
Changed paths:
M libc/src/__support/GPU/allocator.cpp
Log Message:
-----------
[libc] Search empty bits after failed allocation (#149910)
Summary:
The scheme we use to find a free bit is to just do a random walk. This
works very well up until you start to completely saturate the bitfield.
Because the result of the fetch_or yields the previous value, we can
search this to go to any known empty bits as our next guess. This
effectively increases our liklihood of finding a match after two tries
by 32x since the distribution is random.
This *massively* improves performance when a lot of memory is allocated
without freeing, as it now doesn't takea one in a million shot to fill
that last bit. A further change could improve this further by only
*mostly* filling the slab, allowing 1% to be free at all times.
Commit: 17e32c921acc856498ad13ade495374bed4605b2
https://github.com/llvm/llvm-project/commit/17e32c921acc856498ad13ade495374bed4605b2
Author: Jon Roelofs <jonathan_roelofs at apple.com>
Date: 2025-07-23 (Wed, 23 Jul 2025)
Changed paths:
M llvm/test/FileCheck/long-check.txt
Log Message:
-----------
[test][FileCheck] Prefix FileCheck test with %ProtectFileCheckOutput, per post-commit review feedback
https://github.com/llvm/llvm-project/pull/147833#issuecomment-3109470352
Commit: bc1f85d234a8e8e4d1bcfb2126e7c8ec8c8f5b3d
https://github.com/llvm/llvm-project/commit/bc1f85d234a8e8e4d1bcfb2126e7c8ec8c8f5b3d
Author: Changpeng Fang <changpeng.fang at amd.com>
Date: 2025-07-23 (Wed, 23 Jul 2025)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPU.td
M llvm/lib/Target/AMDGPU/AMDGPUSubtarget.h
M llvm/lib/Target/AMDGPU/SIISelLowering.cpp
M llvm/lib/Target/AMDGPU/SIInstrInfo.td
M llvm/lib/Target/AMDGPU/VOP3PInstructions.td
M llvm/test/CodeGen/AMDGPU/bf16-math.ll
M llvm/test/MC/AMDGPU/gfx1250_asm_vop3p.s
M llvm/test/MC/Disassembler/AMDGPU/gfx1250_dasm_vop3p.txt
Log Message:
-----------
AMDGPU: Support packed bf16 instructions on gfx1250 (#150283)
Co-authored-by: Stanislav Mekhanoshin <Stanislav.Mekhanoshin at amd.com>
Commit: 9d11accf95db0ed08bd3181c25dd75fc793d089d
https://github.com/llvm/llvm-project/commit/9d11accf95db0ed08bd3181c25dd75fc793d089d
Author: Oleksandr "Alex" Zinenko <git at ozinenko.com>
Date: 2025-07-23 (Wed, 23 Jul 2025)
Changed paths:
M mlir/include/mlir/Dialect/SCF/Transforms/Passes.td
M mlir/lib/Dialect/SCF/IR/SCF.cpp
M mlir/lib/Dialect/SCF/Transforms/CMakeLists.txt
A mlir/lib/Dialect/SCF/Transforms/IfConditionPropagation.cpp
M mlir/test/Dialect/SCF/canonicalize.mlir
A mlir/test/Dialect/SCF/if-cond-prop.mlir
Log Message:
-----------
[mlir] move if-condition propagation to a standalone pass (#150278)
This offers a significant speedup over running this as a
canonicalizaiton pattern, up to 10x improvement when running on large
(>100k operations) inputs coming from Polygeist.
It is also not clear whether this transformation is a reasonable
canonicalization as it performs non-local rewrites.
Commit: 07af7409997887883ab701acc2dc5659144b0cf2
https://github.com/llvm/llvm-project/commit/07af7409997887883ab701acc2dc5659144b0cf2
Author: Jordan Rupprecht <rupprecht at google.com>
Date: 2025-07-23 (Wed, 23 Jul 2025)
Changed paths:
M utils/bazel/llvm-project-overlay/libc/BUILD.bazel
Log Message:
-----------
[bazel][libc] Add missing parse headers deps (#150295)
I believe this is from #150087 and #144983, but I didn't confirm
specific commits.
Commit: df2d2d125beffb76d5c526a5661fbb11cbcff83b
https://github.com/llvm/llvm-project/commit/df2d2d125beffb76d5c526a5661fbb11cbcff83b
Author: Mircea Trofin <mtrofin at google.com>
Date: 2025-07-23 (Wed, 23 Jul 2025)
Changed paths:
A llvm/include/llvm/Transforms/Utils/ProfileVerify.h
M llvm/lib/Passes/PassBuilder.cpp
M llvm/lib/Passes/PassRegistry.def
M llvm/lib/Transforms/Utils/CMakeLists.txt
A llvm/lib/Transforms/Utils/ProfileVerify.cpp
A llvm/test/Transforms/PGOProfile/prof-verify-as-needed.ll
A llvm/test/Transforms/PGOProfile/prof-verify-existing.ll
A llvm/test/Transforms/PGOProfile/prof-verify.ll
Log Message:
-----------
[PGO] Add ProfileInjector and ProfileVerifier passes (#147388)
Adding 2 passes, one to inject `MD_prof` and one to check its presence. A subsequent patch will add these (similar to debugify) to `opt` (and, eventually, a variant of this, to `llc`)
Tracking issue: #147390
Commit: 20a79027ca58bbde563f9a914e4ada71301eb50a
https://github.com/llvm/llvm-project/commit/20a79027ca58bbde563f9a914e4ada71301eb50a
Author: LLVM GN Syncbot <llvmgnsyncbot at gmail.com>
Date: 2025-07-23 (Wed, 23 Jul 2025)
Changed paths:
M llvm/utils/gn/secondary/llvm/lib/Transforms/Utils/BUILD.gn
Log Message:
-----------
[gn build] Port df2d2d125bef
Commit: 478130545bc41a8bb80304e5d931559a9d2b6171
https://github.com/llvm/llvm-project/commit/478130545bc41a8bb80304e5d931559a9d2b6171
Author: Piotr Zegar <me at piotrzegar.pl>
Date: 2025-07-23 (Wed, 23 Jul 2025)
Changed paths:
M clang-tools-extra/clang-tidy/portability/TemplateVirtualMemberFunctionCheck.cpp
M clang-tools-extra/docs/ReleaseNotes.rst
M clang-tools-extra/test/clang-tidy/checkers/portability/template-virtual-member-function.cpp
Log Message:
-----------
[clang-tidy] Ignore pure-virtual in portability-template... (#150290)
Ignore pure virtual member functions in
portability-template-virtual-member-function check.
Those functions will be represented in vtable
as __cxa_pure_virtual or something similar.
Fixes #139031.
Commit: 4db2f3ac89b1e62af4893b647d77f3ab1f390066
https://github.com/llvm/llvm-project/commit/4db2f3ac89b1e62af4893b647d77f3ab1f390066
Author: Erick Velez <erickvelez7 at gmail.com>
Date: 2025-07-23 (Wed, 23 Jul 2025)
Changed paths:
M clang-tools-extra/clang-doc/BitcodeReader.cpp
M clang-tools-extra/clang-doc/BitcodeWriter.cpp
M clang-tools-extra/clang-doc/BitcodeWriter.h
M clang-tools-extra/clang-doc/JSONGenerator.cpp
M clang-tools-extra/clang-doc/Representation.cpp
M clang-tools-extra/clang-doc/Representation.h
M clang-tools-extra/clang-doc/Serialize.cpp
M clang-tools-extra/test/clang-doc/json/class-requires.cpp
M clang-tools-extra/test/clang-doc/json/class-template.cpp
M clang-tools-extra/test/clang-doc/json/class.cpp
M clang-tools-extra/test/clang-doc/json/compound-constraints.cpp
M clang-tools-extra/test/clang-doc/json/concept.cpp
M clang-tools-extra/test/clang-doc/json/function-requires.cpp
M clang-tools-extra/test/clang-doc/json/method-template.cpp
M clang-tools-extra/test/clang-doc/json/namespace.cpp
M clang-tools-extra/test/clang-doc/json/nested-namespace.cpp
M clang-tools-extra/unittests/clang-doc/JSONGeneratorTest.cpp
Log Message:
-----------
[clang-doc] refactor JSON for better Mustache compatibility (#149588)
This patch contains changes for the JSON generator that will enable compatibility with Mustache templates, like booleans to check for the existence and bounds of arrays to avoid duplication.
Commit: 6925caee4bbb4f1352a347c9c05c999e86a3c61e
https://github.com/llvm/llvm-project/commit/6925caee4bbb4f1352a347c9c05c999e86a3c61e
Author: Finn Plummer <mail at inbelic.dev>
Date: 2025-07-23 (Wed, 23 Jul 2025)
Changed paths:
A llvm/docs/DirectX/RootSignatures.rst
M llvm/docs/DirectXUsage.rst
Log Message:
-----------
[Docs][DirectX] Add relevant documentation of Root Signature (#149608)
This pr adds documentation of root signatures for reference of an LLVM
user.
The target audience is an LLVM user that wants to build a custom tool,
or front-end, that requires constructing a root signature part (RTS0)
for a `DXContainer`.
With that in mind, this pr adds documentation of the metadata
representation of root signatures implemented in LLVM and utilized in
Clang.
Commit: b7ba23f91512b2e703e21e693950dc6086bb51f0
https://github.com/llvm/llvm-project/commit/b7ba23f91512b2e703e21e693950dc6086bb51f0
Author: Craig Topper <craig.topper at sifive.com>
Date: 2025-07-23 (Wed, 23 Jul 2025)
Changed paths:
M llvm/lib/Target/RISCV/RISCVInstrInfoP.td
Log Message:
-----------
[RISCV] Rename RVPUnaryWUF to RVPUnary_ri for consistency. NFC
Commit: 23469688076b334dbcf796bb2079efebf6ddf62a
https://github.com/llvm/llvm-project/commit/23469688076b334dbcf796bb2079efebf6ddf62a
Author: Stanislav Mekhanoshin <Stanislav.Mekhanoshin at amd.com>
Date: 2025-07-23 (Wed, 23 Jul 2025)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPU.td
M llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
M llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp
M llvm/lib/Target/AMDGPU/GCNSubtarget.h
M llvm/lib/Target/AMDGPU/SIISelLowering.cpp
M llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
M llvm/lib/Target/AMDGPU/SIInstrInfo.td
M llvm/lib/Target/AMDGPU/VOP2Instructions.td
M llvm/test/CodeGen/AMDGPU/GlobalISel/mul.ll
A llvm/test/CodeGen/AMDGPU/add_u64.ll
M llvm/test/CodeGen/AMDGPU/branch-relaxation-gfx1250.ll
M llvm/test/CodeGen/AMDGPU/carryout-selection.ll
M llvm/test/CodeGen/AMDGPU/code-size-estimate.ll
M llvm/test/CodeGen/AMDGPU/flat-saddr-atomics.ll
M llvm/test/CodeGen/AMDGPU/flat-saddr-load.ll
M llvm/test/CodeGen/AMDGPU/global-load-xcnt.ll
M llvm/test/CodeGen/AMDGPU/literal64.ll
M llvm/test/CodeGen/AMDGPU/mul.ll
M llvm/test/CodeGen/AMDGPU/scale-offset-flat.ll
A llvm/test/CodeGen/AMDGPU/sub_u64.ll
M llvm/test/MC/AMDGPU/gfx1250_asm_vop2.s
M llvm/test/MC/AMDGPU/gfx1250_asm_vop2_err.s
M llvm/test/MC/Disassembler/AMDGPU/gfx1250_dasm_vop2.txt
Log Message:
-----------
[AMDGPU] Add V_ADD|SUB|MUL_U64 gfx1250 opcodes (#150291)
Commit: c73c19c60efe63b2b0d171f72f1ed6f70d6c4c76
https://github.com/llvm/llvm-project/commit/c73c19c60efe63b2b0d171f72f1ed6f70d6c4c76
Author: Farzon Lotfi <farzonlotfi at microsoft.com>
Date: 2025-07-23 (Wed, 23 Jul 2025)
Changed paths:
M llvm/lib/Target/DirectX/DXILDataScalarization.cpp
A llvm/test/CodeGen/DirectX/bugfix_150050_data_scalarize_const_gep.ll
Log Message:
-----------
[DirectX] Support ConstExpr GEPs (#150082)
- Fixes #150050
- Address the issue of many nested geps
- Check for ConstantExpr GEP if we see it check if it needs a global
replacement with a new type. Create the new constExpr Gep and set the
pointer operand to it. Finally cleanup and remove the old nested geps.
Commit: 898bba311f180ed54de33dc09e7071c279a4942a
https://github.com/llvm/llvm-project/commit/898bba311f180ed54de33dc09e7071c279a4942a
Author: Alexey Bataev <a.bataev at outlook.com>
Date: 2025-07-23 (Wed, 23 Jul 2025)
Changed paths:
M llvm/docs/ReleaseNotes.md
M llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
M llvm/test/Transforms/SLPVectorizer/X86/buildvector-schedule-for-subvector.ll
M llvm/test/Transforms/SLPVectorizer/X86/extract-scalar-from-undef.ll
M llvm/test/Transforms/SLPVectorizer/X86/full-match-with-poison-scalar.ll
M llvm/test/Transforms/SLPVectorizer/X86/node-outside-used-only.ll
M llvm/test/Transforms/SLPVectorizer/X86/non-schedulable-instructions-become-schedulable.ll
M llvm/test/Transforms/SLPVectorizer/X86/pr47642.ll
M llvm/test/Transforms/SLPVectorizer/X86/revec-reduced-value-vectorized-later.ll
M llvm/test/Transforms/SLPVectorizer/alternate-non-profitable.ll
Log Message:
-----------
[SLP]Initial support for copyable elements (non-schedulable only)
Adds initial support for copyable elements. This patch only models adds
and model copyable elements as add <element>, 0, i.e. uses identity
constants for missing lanes.
Only support for elements, which do not require scheduling, is added to
reduce size of the patch.
Fixed compile time regressions, updated release notes
Reviewers: RKSimon, hiraditya
Reviewed By: RKSimon
Pull Request: https://github.com/llvm/llvm-project/pull/140279
Commit: d1ff9713bddf98eb5b3b751ba53e3db896f424ca
https://github.com/llvm/llvm-project/commit/d1ff9713bddf98eb5b3b751ba53e3db896f424ca
Author: David Green <david.green at arm.com>
Date: 2025-07-23 (Wed, 23 Jul 2025)
Changed paths:
M llvm/test/CodeGen/AArch64/urem-lkk.ll
Log Message:
-----------
[AArch64][GISel] Add test coverage for urem-lkk.ll. NFC
Commit: 1206a6165e372c904566163d50911f30809185f3
https://github.com/llvm/llvm-project/commit/1206a6165e372c904566163d50911f30809185f3
Author: Joseph Huber <huberjn at outlook.com>
Date: 2025-07-23 (Wed, 23 Jul 2025)
Changed paths:
M clang/lib/Driver/Driver.cpp
M clang/test/Driver/hip-phases.hip
Log Message:
-----------
[Clang] Fix new driver HIP SPIR-V compilation in device only mode (#150309)
Summary:
This should emit LLVM-IR. Add to the extremely ugly if statement so that
this happens correctly.
Commit: 203ea0a97e827f68b406ca0f350e971a132e58b9
https://github.com/llvm/llvm-project/commit/203ea0a97e827f68b406ca0f350e971a132e58b9
Author: Changpeng Fang <changpeng.fang at amd.com>
Date: 2025-07-23 (Wed, 23 Jul 2025)
Changed paths:
M llvm/lib/Target/AMDGPU/VOP3PInstructions.td
A llvm/test/CodeGen/AMDGPU/fmaximum3.v2f16.ll
A llvm/test/CodeGen/AMDGPU/fminimum3.v2f16.ll
M llvm/test/MC/AMDGPU/gfx1250_asm_vop3p.s
M llvm/test/MC/Disassembler/AMDGPU/gfx1250_dasm_vop3p.txt
Log Message:
-----------
AMDGPU: Support V_PK_MAXIMUM3_F16 and V_PK_MINIMUM3_F16 on gfx1250 (#150307)
Co-authored-by: Stanislav Mekhanoshin <Stanislav.Mekhanoshin at amd.com>
Commit: 34447efd4614cfc8f17aa5cb7305f76ebaf6eaf5
https://github.com/llvm/llvm-project/commit/34447efd4614cfc8f17aa5cb7305f76ebaf6eaf5
Author: Jordan Rupprecht <rupprecht at google.com>
Date: 2025-07-23 (Wed, 23 Jul 2025)
Changed paths:
M clang/test/Driver/offload-target.c
Log Message:
-----------
[clang][test] Specify value of `-fopenmp=libomp` for test. (#150301)
`libomp` is the default value when unconfigured in cmake, but llvm can
be configured to have `libgomp` be the default instead. Explicitly
specify this value so the test does not fail when it assumes libomp is
always the default.
Commit: 52499bbd90b13be8f1f95b980c13c0b044a1a049
https://github.com/llvm/llvm-project/commit/52499bbd90b13be8f1f95b980c13c0b044a1a049
Author: David Green <david.green at arm.com>
Date: 2025-07-23 (Wed, 23 Jul 2025)
Changed paths:
M llvm/test/Analysis/CostModel/ARM/arith.ll
Log Message:
-----------
[ARM] Test all cost kinds in arith.ll. NFC
Commit: 6bc54a4874eeaddf2a1f7c75aed53d9d38ed313c
https://github.com/llvm/llvm-project/commit/6bc54a4874eeaddf2a1f7c75aed53d9d38ed313c
Author: Joseph Huber <huberjn at outlook.com>
Date: 2025-07-23 (Wed, 23 Jul 2025)
Changed paths:
M clang/lib/Driver/Driver.cpp
Log Message:
-----------
[Clang] Make SPIR-V handling only for HIPSPRV
Commit: f443f561331dc54aaed6897f51d7632d62a5ea95
https://github.com/llvm/llvm-project/commit/f443f561331dc54aaed6897f51d7632d62a5ea95
Author: David Pagan <dave.pagan at amd.com>
Date: 2025-07-23 (Wed, 23 Jul 2025)
Changed paths:
M clang/lib/Sema/SemaOpenMP.cpp
Log Message:
-----------
[clang][Sema][NFC] Fixed incorrect assert messages in SemaOpenMP (#150305)
Commit: 49de210d24f616d8b4eff7656be9a27d7db5135d
https://github.com/llvm/llvm-project/commit/49de210d24f616d8b4eff7656be9a27d7db5135d
Author: lntue <lntue at google.com>
Date: 2025-07-23 (Wed, 23 Jul 2025)
Changed paths:
M libc/src/__support/CPP/type_traits/is_constant_evaluated.h
M libc/src/__support/RPC/rpc_server.h
M libc/src/__support/macros/attributes.h
Log Message:
-----------
[libc] Add support for __builtin_is_constant_evaluated for GCC 9+. (#150322)
https://lab.llvm.org/buildbot/#/builders/10/builds/10047/steps/5/logs/stdio
Commit: 1b7aa4edda2b3020f0e10f5a34e707fcadc2587d
https://github.com/llvm/llvm-project/commit/1b7aa4edda2b3020f0e10f5a34e707fcadc2587d
Author: Qinkun Bao <qinkun at google.com>
Date: 2025-07-23 (Wed, 23 Jul 2025)
Changed paths:
M clang/test/Interpreter/pretty-print.c
Log Message:
-----------
[clang-repl] Disable new test after #148701 (#150294)
https://github.com/llvm/llvm-project/pull/148701 adds new tests.
However, these tests never pass on msan buildbots.
https://lab.llvm.org/buildbot/#/builders/94/builds/9132
https://lab.llvm.org/buildbot/#/builders/94/builds/9131
https://lab.llvm.org/buildbot/#/builders/94/builds/9130
Commit: ad36e4284d66c3609ef8675ef02ff1844bc1951d
https://github.com/llvm/llvm-project/commit/ad36e4284d66c3609ef8675ef02ff1844bc1951d
Author: Sterling-Augustine <56981066+Sterling-Augustine at users.noreply.github.com>
Date: 2025-07-23 (Wed, 23 Jul 2025)
Changed paths:
M llvm/include/llvm/MC/MCObjectStreamer.h
M llvm/include/llvm/MC/MCStreamer.h
M llvm/include/llvm/MC/MCTargetOptions.h
M llvm/include/llvm/MC/MCTargetOptionsCommandFlags.h
M llvm/lib/CodeGen/AsmPrinter/ARMException.cpp
M llvm/lib/CodeGen/AsmPrinter/DwarfCFIException.cpp
M llvm/lib/MC/MCAsmStreamer.cpp
M llvm/lib/MC/MCObjectStreamer.cpp
M llvm/lib/MC/MCParser/AsmParser.cpp
M llvm/lib/MC/MCStreamer.cpp
M llvm/lib/MC/MCTargetOptionsCommandFlags.cpp
M llvm/test/MC/ELF/AArch64/cfi.s
M llvm/test/MC/ELF/cfi.s
Log Message:
-----------
Revert "Support SFrame command-line and .cfi_section syntax (#149935)" (#150316)
This reverts commit f9d0bd02d966e5c28aca9a6ceadd5ffec6aa9f78.
Commit: 71c06d7a5f99ef7039b024d75cbdcddd71872602
https://github.com/llvm/llvm-project/commit/71c06d7a5f99ef7039b024d75cbdcddd71872602
Author: Craig Topper <craig.topper at sifive.com>
Date: 2025-07-23 (Wed, 23 Jul 2025)
Changed paths:
M llvm/lib/IR/Type.cpp
Log Message:
-----------
[IR] Remove unnecessary casts from IntegerType::get. NFC (#150299)
Commit: 9a563b08e20423d848e318e0a8891205bd673724
https://github.com/llvm/llvm-project/commit/9a563b08e20423d848e318e0a8891205bd673724
Author: Changpeng Fang <changpeng.fang at amd.com>
Date: 2025-07-23 (Wed, 23 Jul 2025)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPU.td
M llvm/lib/Target/AMDGPU/GCNSubtarget.h
M llvm/lib/Target/AMDGPU/SIISelLowering.cpp
M llvm/lib/Target/AMDGPU/VOP3PInstructions.td
M llvm/test/CodeGen/AMDGPU/fmax3.ll
M llvm/test/CodeGen/AMDGPU/fmin3.ll
M llvm/test/MC/AMDGPU/gfx1250_asm_vop3p.s
M llvm/test/MC/Disassembler/AMDGPU/gfx1250_dasm_vop3p.txt
Log Message:
-----------
[AMDGPU] Support V_PK_MIN3/MAX3_NUM_F16 on gfx1250 (#150326)
Co-authored-by: Stanislav Mekhanoshin <Stanislav.Mekhanoshin at amd.com>
Commit: 21118dbbb8718313b2dc45a7913781750edea6e1
https://github.com/llvm/llvm-project/commit/21118dbbb8718313b2dc45a7913781750edea6e1
Author: Kazu Hirata <kazu at google.com>
Date: 2025-07-23 (Wed, 23 Jul 2025)
Changed paths:
M llvm/lib/CodeGen/AsmPrinter/DwarfCompileUnit.cpp
Log Message:
-----------
[AsmPrinter] Remove an unnecessary cast (NFC) (#150257)
getTag already returns dwarf::Tag.
Commit: 31281da34b7f1445ce9e39bbb8707f4eacd24e58
https://github.com/llvm/llvm-project/commit/31281da34b7f1445ce9e39bbb8707f4eacd24e58
Author: Kazu Hirata <kazu at google.com>
Date: 2025-07-23 (Wed, 23 Jul 2025)
Changed paths:
M llvm/lib/Analysis/ConstantFolding.cpp
Log Message:
-----------
[Analysis] Drop const from return types (NFC) (#150258)
We don't need const on APFloat.
Commit: 3e53d4d386626d78bf930307f0a65b6aebb48ee9
https://github.com/llvm/llvm-project/commit/3e53d4d386626d78bf930307f0a65b6aebb48ee9
Author: Kazu Hirata <kazu at google.com>
Date: 2025-07-23 (Wed, 23 Jul 2025)
Changed paths:
M llvm/lib/CodeGen/MachineLICM.cpp
M llvm/lib/CodeGen/TargetLoweringObjectFileImpl.cpp
M llvm/lib/DebugInfo/DWARF/DWARFCFIPrinter.cpp
M llvm/lib/DebugInfo/DWARF/LowLevel/DWARFExpression.cpp
M llvm/lib/MC/MCAssembler.cpp
M llvm/lib/MC/MCMachOStreamer.cpp
M llvm/lib/MC/MCObjectStreamer.cpp
M llvm/lib/Target/AArch64/MCTargetDesc/AArch64MCExpr.cpp
M llvm/lib/Target/AVR/MCTargetDesc/AVRMCExpr.cpp
M llvm/lib/Target/BPF/MCTargetDesc/BPFInstPrinter.cpp
M llvm/lib/Target/Hexagon/HexagonLoopIdiomRecognition.cpp
M llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCExpr.cpp
M llvm/lib/Target/Sparc/MCTargetDesc/SparcELFObjectWriter.cpp
M llvm/lib/Target/Sparc/MCTargetDesc/SparcMCExpr.cpp
M llvm/lib/Target/X86/MCTargetDesc/X86MCAsmInfo.cpp
M llvm/lib/TargetParser/Triple.cpp
M llvm/lib/Transforms/InstCombine/InstCombineLoadStoreAlloca.cpp
M llvm/lib/Transforms/Instrumentation/MemorySanitizer.cpp
M llvm/lib/Transforms/Scalar/LoopIdiomRecognize.cpp
M llvm/lib/Transforms/Utils/Debugify.cpp
M llvm/lib/Transforms/Utils/LCSSA.cpp
M llvm/lib/Transforms/Utils/PredicateInfo.cpp
Log Message:
-----------
[llvm] Remove unused includes (NFC) (#150265)
These are identified by misc-include-cleaner. I've filtered out those
that break builds. Also, I'm staying away from llvm-config.h,
config.h, and Compiler.h, which likely cause platform- or
compiler-specific build failures.
Commit: 0925d7572acee311bf596db294bc818536722150
https://github.com/llvm/llvm-project/commit/0925d7572acee311bf596db294bc818536722150
Author: Kazu Hirata <kazu at google.com>
Date: 2025-07-23 (Wed, 23 Jul 2025)
Changed paths:
M mlir/lib/Dialect/AMDGPU/Transforms/MaskedloadToLoad.cpp
M mlir/lib/Dialect/Affine/Analysis/AffineAnalysis.cpp
M mlir/lib/Dialect/Affine/Transforms/AffineParallelize.cpp
M mlir/lib/Dialect/Affine/Transforms/LoopUnroll.cpp
M mlir/lib/Dialect/Affine/Utils/LoopUtils.cpp
M mlir/lib/Dialect/Affine/Utils/Utils.cpp
M mlir/lib/Dialect/Arith/Transforms/ExpandOps.cpp
M mlir/lib/Dialect/Arith/Utils/Utils.cpp
M mlir/lib/Dialect/Async/Transforms/AsyncParallelFor.cpp
M mlir/lib/Dialect/Async/Transforms/AsyncToAsyncRuntime.cpp
M mlir/lib/Dialect/Bufferization/Transforms/TensorCopyInsertion.cpp
M mlir/lib/Dialect/Complex/IR/ComplexOps.cpp
M mlir/lib/Dialect/ControlFlow/IR/ControlFlowOps.cpp
M mlir/lib/Dialect/GPU/TransformOps/Utils.cpp
M mlir/lib/Dialect/GPU/Transforms/MemoryPromotion.cpp
M mlir/lib/Dialect/IRDL/IRDLVerifiers.cpp
M mlir/lib/Dialect/Index/IR/InferIntRangeInterfaceImpls.cpp
M mlir/lib/Dialect/LLVMIR/IR/LLVMTypeSyntax.cpp
M mlir/lib/Dialect/LLVMIR/IR/XeVMDialect.cpp
M mlir/lib/Dialect/Linalg/TransformOps/GPUHeuristics.cpp
M mlir/lib/Dialect/Linalg/Transforms/MeshShardingInterfaceImpl.cpp
M mlir/lib/Dialect/Linalg/Transforms/Promotion.cpp
M mlir/lib/Dialect/Math/Transforms/ExpandPatterns.cpp
M mlir/lib/Dialect/Math/Transforms/PolynomialApproximation.cpp
M mlir/lib/Dialect/MemRef/Transforms/ReifyResultShapes.cpp
M mlir/lib/Dialect/Mesh/Transforms/Simplifications.cpp
M mlir/lib/Dialect/Mesh/Transforms/Spmdization.cpp
M mlir/lib/Dialect/Mesh/Transforms/Transforms.cpp
M mlir/lib/Dialect/OpenMP/IR/OpenMPDialect.cpp
M mlir/lib/Dialect/Quant/IR/TypeParser.cpp
M mlir/lib/Dialect/SCF/Transforms/TileUsingInterface.cpp
M mlir/lib/Dialect/SCF/Utils/Utils.cpp
M mlir/lib/Dialect/SPIRV/IR/SPIRVTypes.cpp
M mlir/lib/Dialect/Tensor/Transforms/SwapExtractSliceWithProducerPatterns.cpp
M mlir/lib/Dialect/Tosa/Transforms/TosaConvertIntegerTypeToSignless.cpp
M mlir/lib/Dialect/Transform/Interfaces/TransformInterfaces.cpp
M mlir/lib/Dialect/Transform/TuneExtension/TuneExtensionOps.cpp
M mlir/lib/Dialect/Vector/Transforms/LowerVectorTranspose.cpp
M mlir/lib/Dialect/X86Vector/Transforms/AVXTranspose.cpp
M mlir/lib/Dialect/XeGPU/Transforms/XeGPUFoldAliasOps.cpp
M mlir/lib/Dialect/XeGPU/Utils/XeGPUUtils.cpp
Log Message:
-----------
[mlir] Remove unused includes (NFC) (#150266)
These are identified by misc-include-cleaner. I've filtered out those
that break builds. Also, I'm staying away from llvm-config.h,
config.h, and Compiler.h, which likely cause platform- or
compiler-specific build failures.
Commit: 9d9d971f71d3659cca7b5076b7cc8861bad176bd
https://github.com/llvm/llvm-project/commit/9d9d971f71d3659cca7b5076b7cc8861bad176bd
Author: Kazu Hirata <kazu at google.com>
Date: 2025-07-23 (Wed, 23 Jul 2025)
Changed paths:
M llvm/docs/AMDGPUUsage.rst
Log Message:
-----------
[llvm] Proofread AMDGPUUsage.rst (#150273)
Commit: 6d90715019d54376523163a7e1d588e1068cfca2
https://github.com/llvm/llvm-project/commit/6d90715019d54376523163a7e1d588e1068cfca2
Author: Erick Velez <erickvelez7 at gmail.com>
Date: 2025-07-23 (Wed, 23 Jul 2025)
Changed paths:
M clang-tools-extra/clang-doc/HTMLMustacheGenerator.cpp
M clang-tools-extra/clang-doc/assets/class-template.mustache
M clang-tools-extra/clang-doc/assets/enum-template.mustache
M clang-tools-extra/clang-doc/assets/function-template.mustache
M clang-tools-extra/clang-doc/assets/namespace-template.mustache
M clang-tools-extra/test/clang-doc/basic-project.mustache.test
M clang-tools-extra/test/clang-doc/mustache-index.cpp
M clang-tools-extra/test/clang-doc/mustache-separate-namespace.cpp
M clang-tools-extra/unittests/clang-doc/HTMLMustacheGeneratorTest.cpp
Log Message:
-----------
[clang-doc] integrate JSON as the source for Mustache templates (#149589)
This patch integrates JSON as the source to generate HTML Mustache templates. The Mustache generator calls the JSON generator and reads JSON files on the disk to produce HTML serially.
Commit: 11d97b3b58687bf4db978d3ba3c15fd6177549fa
https://github.com/llvm/llvm-project/commit/11d97b3b58687bf4db978d3ba3c15fd6177549fa
Author: Andrew Rogers <andrurogerz at gmail.com>
Date: 2025-07-23 (Wed, 23 Jul 2025)
Changed paths:
M llvm/include/llvm/Config/abi-breaking.h.cmake
Log Message:
-----------
[llvm] annotate ABIBreakingChecks symbols for DLL export (#149198)
## Purpose
This PR is a re-application of #145575 with independent definition of
`ABI_BREAKING_EXPORT_ABI` that does not depend on
`llvm/Support/Compiler.h`. It is one in a series of code-mods that
annotate LLVM’s public interface for export. This patch annotates the
ABI Breaking Checks interface in llvm/config. The annotations currently
have no meaningful impact on the LLVM build; however, they are a
prerequisite to support an LLVM Windows DLL (shared library) build.
## Background
The effort to build LLVM as a Windows DLL is tracked in #109483.
Additional context is provided in [this
discourse](https://discourse.llvm.org/t/psa-annotating-llvm-public-interface/85307),
and documentation for `LLVM_ABI` and related annotations is found in the
LLVM repo
[here](https://github.com/llvm/llvm-project/blob/main/llvm/docs/InterfaceExportAnnotations.rst).
## Validation
Local builds and tests to validate cross-platform compatibility. This
included llvm, clang, and lldb on the following configurations:
- Windows with MSVC
- Windows with Clang
- Linux with GCC
- Linux with Clang
- Darwin with Clang
Commit: 05e08cdb3e576cc0887d1507ebd2f756460c7db7
https://github.com/llvm/llvm-project/commit/05e08cdb3e576cc0887d1507ebd2f756460c7db7
Author: Haowei <haowei at google.com>
Date: 2025-07-23 (Wed, 23 Jul 2025)
Changed paths:
M llvm/include/llvm/CodeGen/CommandFlags.h
M llvm/include/llvm/CodeGen/MIRYamlMapping.h
M llvm/include/llvm/CodeGen/MachineFunction.h
M llvm/include/llvm/Target/TargetOptions.h
M llvm/lib/CodeGen/CommandFlags.cpp
M llvm/lib/CodeGen/MIRParser/MIRParser.cpp
M llvm/lib/CodeGen/MIRPrinter.cpp
M llvm/lib/CodeGen/MachineFunction.cpp
R llvm/test/CodeGen/MIR/X86/call-site-info-ambiguous-indirect-call-typeid.mir
R llvm/test/CodeGen/MIR/X86/call-site-info-direct-calls-typeid.mir
R llvm/test/CodeGen/MIR/X86/call-site-info-typeid.mir
Log Message:
-----------
Revert "[llvm] Add CalleeTypeIds field to CallSiteInfo" (#150335)
Reverts llvm/llvm-project#87574, which breaks LLVM ::
CodeGen/MIR/X86/call-site-info-ambiguous-indirect-call-typeid.mir tests
on linux-arm64 builders.
Commit: 7b66629497ea5b6cde1772fab161c028e8c972a7
https://github.com/llvm/llvm-project/commit/7b66629497ea5b6cde1772fab161c028e8c972a7
Author: Craig Topper <craig.topper at sifive.com>
Date: 2025-07-23 (Wed, 23 Jul 2025)
Changed paths:
M llvm/lib/IR/Type.cpp
Log Message:
-----------
[IR] Remove static variables from Type::getWasm_ExternrefTy/getWasm_FuncrefTy. (#150323)
These were caching pointers to memory owned by LLVMContext and can
outlive the LLVMContext. The LLVMContext already caches pointer types so
we shouldn't need any caching here.
Commit: 7ae371548f05a94f933db691424b662515afc5a7
https://github.com/llvm/llvm-project/commit/7ae371548f05a94f933db691424b662515afc5a7
Author: Shilei Tian <i at tianshilei.me>
Date: 2025-07-23 (Wed, 23 Jul 2025)
Changed paths:
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.1024bit.ll
M llvm/test/CodeGen/AMDGPU/call-args-inreg-no-sgpr-for-csrspill-xfail.ll
M llvm/test/CodeGen/AMDGPU/illegal-sgpr-to-vgpr-copy.ll
M llvm/test/CodeGen/AMDGPU/sgpr-regalloc-flags.ll
M llvm/test/CodeGen/AMDGPU/shufflevector-physreg-copy.ll
M llvm/test/CodeGen/AMDGPU/swdev503538-move-to-valu-stack-srd-physreg.ll
M llvm/test/CodeGen/AMDGPU/tail-call-inreg-arguments.error.ll
Log Message:
-----------
[NFC][FIX] Add `-verify-machineinstrs=0` explicitly to some test files
They had it before but that was removed in #150024. They need to disable the check explicitly to pass expensive checks.
Commit: c21e2a5e24c7bc55767055e25bb2fb40cbec68c3
https://github.com/llvm/llvm-project/commit/c21e2a5e24c7bc55767055e25bb2fb40cbec68c3
Author: joaosaffran <126493771+joaosaffran at users.noreply.github.com>
Date: 2025-07-23 (Wed, 23 Jul 2025)
Changed paths:
M llvm/include/llvm/Frontend/HLSL/RootSignatureMetadata.h
M llvm/include/llvm/MC/DXContainerRootSignature.h
M llvm/lib/Frontend/HLSL/RootSignatureMetadata.cpp
M llvm/lib/Target/DirectX/DXILRootSignature.cpp
M llvm/lib/Target/DirectX/DXILRootSignature.h
Log Message:
-----------
[DirectX] Moving Root Signature Metadata Parsing in to Shared Root Signature Metadata lib (#149221)
This PR, moves the existing Root Signature Metadata Parsing logic used
in `DXILRootSignature` to the common library used by both frontend and
backend. Closes:
[#145942](https://github.com/llvm/llvm-project/issues/145942)
---------
Co-authored-by: joaosaffran <joao.saffran at microsoft.com>
Commit: 66603dd1f10e0f6c0510273378334971159f6b69
https://github.com/llvm/llvm-project/commit/66603dd1f10e0f6c0510273378334971159f6b69
Author: lntue <lntue at google.com>
Date: 2025-07-23 (Wed, 23 Jul 2025)
Changed paths:
M libc/benchmarks/gpu/BenchmarkLogger.cpp
M libc/benchmarks/gpu/CMakeLists.txt
M libc/benchmarks/gpu/LibcGpuBenchmark.h
M libc/benchmarks/gpu/src/math/CMakeLists.txt
M libc/benchmarks/gpu/src/math/platform.h
M libc/benchmarks/gpu/timing/amdgpu/CMakeLists.txt
M libc/benchmarks/gpu/timing/amdgpu/timing.h
M libc/benchmarks/gpu/timing/nvptx/CMakeLists.txt
M libc/benchmarks/gpu/timing/nvptx/timing.h
M libc/config/CMakeLists.txt
M libc/config/gpu/app.h
M libc/config/linux/app.h
M libc/config/uefi/app.h
M libc/hdr/CMakeLists.txt
A libc/hdr/stdint_proxy.h
M libc/hdr/types/CMakeLists.txt
M libc/include/CMakeLists.txt
M libc/src/__support/CMakeLists.txt
M libc/src/__support/CPP/CMakeLists.txt
M libc/src/__support/CPP/bit.h
M libc/src/__support/CPP/functional.h
M libc/src/__support/FPUtil/CMakeLists.txt
M libc/src/__support/FPUtil/FPBits.h
M libc/src/__support/FPUtil/NormalFloat.h
M libc/src/__support/FPUtil/aarch64/FEnvImpl.h
M libc/src/__support/FPUtil/aarch64/fenv_darwin_impl.h
M libc/src/__support/FPUtil/arm/FEnvImpl.h
M libc/src/__support/FPUtil/bfloat16.h
M libc/src/__support/FPUtil/riscv/FEnvImpl.h
M libc/src/__support/FPUtil/x86_64/FEnvImpl.h
M libc/src/__support/FPUtil/x86_64/NextAfterLongDouble.h
M libc/src/__support/File/CMakeLists.txt
M libc/src/__support/File/file.h
M libc/src/__support/File/linux/CMakeLists.txt
M libc/src/__support/File/linux/lseekImpl.h
M libc/src/__support/GPU/CMakeLists.txt
M libc/src/__support/GPU/allocator.h
M libc/src/__support/HashTable/CMakeLists.txt
M libc/src/__support/HashTable/bitmask.h
M libc/src/__support/HashTable/table.h
M libc/src/__support/arg_list.h
M libc/src/__support/big_int.h
M libc/src/__support/block.h
M libc/src/__support/blockstore.h
M libc/src/__support/detailed_powers_of_ten.h
M libc/src/__support/endian_internal.h
M libc/src/__support/fixed_point/CMakeLists.txt
M libc/src/__support/fixed_point/fx_rep.h
M libc/src/__support/float_to_string.h
M libc/src/__support/hash.h
M libc/src/__support/high_precision_decimal.h
M libc/src/__support/integer_literals.h
M libc/src/__support/integer_to_string.h
M libc/src/__support/macros/properties/CMakeLists.txt
M libc/src/__support/macros/properties/types.h
M libc/src/__support/math/CMakeLists.txt
M libc/src/__support/math/exp10_float16_constants.h
M libc/src/__support/ryu_constants.h
M libc/src/__support/ryu_long_double_constants.h
M libc/src/__support/str_to_float.h
M libc/src/__support/threads/CMakeLists.txt
M libc/src/__support/threads/CndVar.h
M libc/src/__support/threads/linux/CMakeLists.txt
M libc/src/__support/threads/linux/futex_word.h
M libc/src/__support/threads/linux/thread.cpp
M libc/src/__support/threads/thread.h
M libc/src/__support/wchar/CMakeLists.txt
M libc/src/__support/wchar/mbstate.h
M libc/src/arpa/inet/CMakeLists.txt
M libc/src/arpa/inet/htonl.h
M libc/src/arpa/inet/htons.h
M libc/src/arpa/inet/ntohl.h
M libc/src/arpa/inet/ntohs.h
M libc/src/compiler/generic/CMakeLists.txt
M libc/src/compiler/generic/__stack_chk_fail.cpp
M libc/src/inttypes/CMakeLists.txt
M libc/src/inttypes/strtoimax.h
M libc/src/inttypes/strtoumax.h
M libc/src/link/CMakeLists.txt
M libc/src/math/generic/CMakeLists.txt
M libc/src/math/generic/expxf16.h
M libc/src/pthread/CMakeLists.txt
M libc/src/pthread/pthread_attr_setstack.cpp
M libc/src/sched/linux/CMakeLists.txt
M libc/src/sched/linux/sched_getaffinity.cpp
M libc/src/spawn/CMakeLists.txt
M libc/src/spawn/file_actions.h
M libc/src/stdio/gpu/CMakeLists.txt
M libc/src/stdio/gpu/fgets.cpp
M libc/src/stdlib/CMakeLists.txt
M libc/src/stdlib/a64l.cpp
M libc/src/stdlib/bsearch.cpp
M libc/src/stdlib/l64a.cpp
M libc/src/stdlib/qsort.cpp
M libc/src/stdlib/qsort_data.h
M libc/src/stdlib/qsort_r.cpp
M libc/src/stdlib/quick_sort.h
M libc/src/string/CMakeLists.txt
M libc/src/string/memory_utils/CMakeLists.txt
M libc/src/string/memory_utils/op_generic.h
M libc/src/string/memory_utils/utils.h
M libc/src/string/memory_utils/x86_64/inline_memcpy.h
M libc/src/string/string_utils.h
M libc/src/sys/stat/linux/CMakeLists.txt
M libc/src/sys/stat/linux/kernel_statx.h
M libc/src/time/CMakeLists.txt
M libc/src/time/linux/CMakeLists.txt
M libc/src/time/linux/nanosleep.cpp
M libc/src/time/strftime_core/CMakeLists.txt
M libc/src/time/strftime_core/core_structs.h
M libc/src/time/time_constants.h
M libc/src/time/time_utils.cpp
M libc/src/time/time_utils.h
M libc/src/unistd/linux/CMakeLists.txt
M libc/src/unistd/linux/ftruncate.cpp
M libc/src/unistd/linux/pread.cpp
M libc/src/unistd/linux/pwrite.cpp
M libc/src/unistd/linux/truncate.cpp
M libc/startup/baremetal/CMakeLists.txt
M libc/startup/baremetal/fini.cpp
M libc/startup/baremetal/init.cpp
M libc/startup/linux/CMakeLists.txt
M libc/startup/linux/do_start.cpp
M libc/test/IntegrationTest/CMakeLists.txt
M libc/test/IntegrationTest/test.cpp
M libc/test/UnitTest/CMakeLists.txt
M libc/test/UnitTest/ExecuteFunction.h
M libc/test/UnitTest/HermeticTestUtils.cpp
M libc/test/UnitTest/PrintfMatcher.cpp
M libc/test/UnitTest/RoundingModeUtils.h
M libc/test/UnitTest/ScanfMatcher.cpp
M libc/test/UnitTest/TestLogger.cpp
M libc/test/integration/src/pthread/CMakeLists.txt
M libc/test/integration/src/pthread/pthread_equal_test.cpp
M libc/test/integration/src/pthread/pthread_mutex_test.cpp
M libc/test/integration/src/pthread/pthread_name_test.cpp
M libc/test/integration/src/pthread/pthread_once_test.cpp
M libc/test/integration/src/pthread/pthread_test.cpp
M libc/test/integration/src/spawn/CMakeLists.txt
M libc/test/integration/src/spawn/posix_spawn_test.cpp
M libc/test/src/CMakeLists.txt
M libc/test/src/__support/CMakeLists.txt
M libc/test/src/__support/CPP/CMakeLists.txt
M libc/test/src/__support/CPP/bit_test.cpp
M libc/test/src/__support/HashTable/CMakeLists.txt
M libc/test/src/__support/HashTable/group_test.cpp
M libc/test/src/__support/str_to_float_comparison_test.cpp
M libc/test/src/fenv/feclearexcept_test.cpp
M libc/test/src/math/LdExpTest.h
M libc/test/src/math/acosf_test.cpp
M libc/test/src/math/acoshf16_test.cpp
M libc/test/src/math/acoshf_test.cpp
M libc/test/src/math/asinf_test.cpp
M libc/test/src/math/asinhf_test.cpp
M libc/test/src/math/atanf_test.cpp
M libc/test/src/math/atanhf16_test.cpp
M libc/test/src/math/atanhf_test.cpp
M libc/test/src/math/cosf_test.cpp
M libc/test/src/math/coshf_test.cpp
M libc/test/src/math/erff_test.cpp
M libc/test/src/math/exp10_test.cpp
M libc/test/src/math/exp10f_test.cpp
M libc/test/src/math/exp10m1f_test.cpp
M libc/test/src/math/exp2_test.cpp
M libc/test/src/math/exp2f_test.cpp
M libc/test/src/math/exp2m1f_test.cpp
M libc/test/src/math/exp_test.cpp
M libc/test/src/math/expf_test.cpp
M libc/test/src/math/expm1_test.cpp
M libc/test/src/math/expm1f_test.cpp
M libc/test/src/math/in_float_range_test_helper.h
M libc/test/src/math/log10_test.cpp
M libc/test/src/math/log10f_test.cpp
M libc/test/src/math/log1p_test.cpp
M libc/test/src/math/log1pf_test.cpp
M libc/test/src/math/log2_test.cpp
M libc/test/src/math/log2f_test.cpp
M libc/test/src/math/log_test.cpp
M libc/test/src/math/logf_test.cpp
M libc/test/src/math/performance_testing/Timer.h
M libc/test/src/math/performance_testing/fmodf16_perf.cpp
M libc/test/src/math/powf_test.cpp
M libc/test/src/math/sdcomp26094.h
M libc/test/src/math/sincosf_test.cpp
M libc/test/src/math/sinf_test.cpp
M libc/test/src/math/sinhf_test.cpp
M libc/test/src/math/sinpif_test.cpp
M libc/test/src/math/smoke/LdExpTest.h
M libc/test/src/math/smoke/acosf_test.cpp
M libc/test/src/math/smoke/acoshf_test.cpp
M libc/test/src/math/smoke/asinf_test.cpp
M libc/test/src/math/smoke/asinhf_test.cpp
M libc/test/src/math/smoke/atanf_test.cpp
M libc/test/src/math/smoke/atanhf_test.cpp
M libc/test/src/math/smoke/cosf_test.cpp
M libc/test/src/math/smoke/coshf_test.cpp
M libc/test/src/math/smoke/cospif_test.cpp
M libc/test/src/math/smoke/erff_test.cpp
M libc/test/src/math/smoke/exp10_test.cpp
M libc/test/src/math/smoke/exp10f_test.cpp
M libc/test/src/math/smoke/exp2_test.cpp
M libc/test/src/math/smoke/exp2f_test.cpp
M libc/test/src/math/smoke/exp_test.cpp
M libc/test/src/math/smoke/expf_test.cpp
M libc/test/src/math/smoke/expm1_test.cpp
M libc/test/src/math/smoke/expm1f_test.cpp
M libc/test/src/math/smoke/log10_test.cpp
M libc/test/src/math/smoke/log10f_test.cpp
M libc/test/src/math/smoke/log1pf_test.cpp
M libc/test/src/math/smoke/log2_test.cpp
M libc/test/src/math/smoke/log2f_test.cpp
M libc/test/src/math/smoke/log_test.cpp
M libc/test/src/math/smoke/logf_test.cpp
M libc/test/src/math/smoke/powf_test.cpp
M libc/test/src/math/smoke/sincosf_test.cpp
M libc/test/src/math/smoke/sinf_test.cpp
M libc/test/src/math/smoke/sinhf_test.cpp
M libc/test/src/math/smoke/sinpif_test.cpp
M libc/test/src/math/smoke/tanf_test.cpp
M libc/test/src/math/smoke/tanhf_test.cpp
M libc/test/src/math/tanf_test.cpp
M libc/test/src/math/tanhf_test.cpp
M libc/test/src/signal/CMakeLists.txt
M libc/test/src/signal/sigaltstack_test.cpp
M libc/test/src/spawn/CMakeLists.txt
M libc/test/src/spawn/posix_spawn_file_actions_test.cpp
M libc/test/src/stdlib/CMakeLists.txt
M libc/test/src/stdlib/memalignment_test.cpp
M libc/test/src/stdlib/strtoint32_test.cpp
M libc/test/src/stdlib/strtoint64_test.cpp
M libc/test/src/string/memory_utils/CMakeLists.txt
M libc/test/src/string/memory_utils/memory_check_utils.h
M libc/test/src/string/memory_utils/protected_pages.h
M libc/utils/MPCWrapper/CMakeLists.txt
M libc/utils/MPCWrapper/MPCUtils.cpp
M libc/utils/MPCWrapper/MPCUtils.h
M libc/utils/MPFRWrapper/CMakeLists.txt
M libc/utils/MPFRWrapper/MPCommon.h
M libc/utils/MPFRWrapper/MPFRUtils.h
M utils/bazel/llvm-project-overlay/libc/BUILD.bazel
M utils/bazel/llvm-project-overlay/libc/test/UnitTest/BUILD.bazel
M utils/bazel/llvm-project-overlay/libc/test/libc_test_rules.bzl
Log Message:
-----------
[libc][NFC] Add stdint.h proxy header to fix dependency issue with <stdint.h> includes. (#150303)
https://github.com/llvm/llvm-project/issues/149993
Commit: fd86b2e26c0933c2af61fc50a674f668a7991f66
https://github.com/llvm/llvm-project/commit/fd86b2e26c0933c2af61fc50a674f668a7991f66
Author: Jim Lin <jim at andestech.com>
Date: 2025-07-24 (Thu, 24 Jul 2025)
Changed paths:
A llvm/test/tools/llvm-exegesis/RISCV/set-reg-init-check.s
M llvm/tools/llvm-exegesis/lib/RISCV/Target.cpp
Log Message:
-----------
[RISCV][llvm-exegesis] Add missing operand frm for FCVT_D_W (#149989)
We encountered the index of operand out of bounds crash because FCVT_D_W
lacks frm operand.
Commit: b61695e3ebe66b96172b7f49069c8d2c26e28b23
https://github.com/llvm/llvm-project/commit/b61695e3ebe66b96172b7f49069c8d2c26e28b23
Author: Jordan Rupprecht <rupprecht at google.com>
Date: 2025-07-23 (Wed, 23 Jul 2025)
Changed paths:
M utils/bazel/llvm-project-overlay/llvm/BUILD.bazel
Log Message:
-----------
[bazel] Port #149221 (#150347)
Commit: 22fef005225b129d73ade4ed995fc0ec0c7be044
https://github.com/llvm/llvm-project/commit/22fef005225b129d73ade4ed995fc0ec0c7be044
Author: Samarth Narang <70980689+snarang181 at users.noreply.github.com>
Date: 2025-07-24 (Thu, 24 Jul 2025)
Changed paths:
M clang/lib/Sema/SemaDecl.cpp
M clang/lib/Sema/SemaDeclAttr.cpp
M clang/test/SemaCXX/wreturn-always-throws.cpp
Log Message:
-----------
[clang] Avoid inheriting [[noreturn]] in explicit function template specializations (#150003)
This patch fixes incorrect behavior in Clang where [[noreturn]] (either
spelled or inferred) was being inherited by explicit specializations of
function templates or member function templates, even when those
specializations returned normally.
Follow up on https://github.com/llvm/llvm-project/pull/145166
Commit: 68c8c8ceeba6da96189335236e3ec80a082e4d7b
https://github.com/llvm/llvm-project/commit/68c8c8ceeba6da96189335236e3ec80a082e4d7b
Author: Chelsea Cassanova <chelsea_cassanova at apple.com>
Date: 2025-07-23 (Wed, 23 Jul 2025)
Changed paths:
M lldb/cmake/modules/LLDBConfig.cmake
M lldb/test/CMakeLists.txt
A lldb/test/Shell/RPC/Generator/Inputs/SBDummy.h
A lldb/test/Shell/RPC/Generator/Tests/CheckRPCGenToolByproducts.test
A lldb/test/Shell/RPC/Generator/lit.local.cfg
M lldb/test/Shell/helper/toolchain.py
M lldb/test/Shell/lit.site.cfg.py.in
M lldb/tools/CMakeLists.txt
A lldb/tools/lldb-rpc-gen/CMakeLists.txt
A lldb/tools/lldb-rpc-gen/RPCCommon.cpp
A lldb/tools/lldb-rpc-gen/RPCCommon.h
A lldb/tools/lldb-rpc-gen/lldb-rpc-gen.cpp
A lldb/tools/lldb-rpc-gen/server/RPCServerHeaderEmitter.cpp
A lldb/tools/lldb-rpc-gen/server/RPCServerHeaderEmitter.h
A lldb/tools/lldb-rpc-gen/server/RPCServerSourceEmitter.cpp
A lldb/tools/lldb-rpc-gen/server/RPCServerSourceEmitter.h
A lldb/tools/lldb-rpc/CMakeLists.txt
A lldb/tools/lldb-rpc/LLDBRPCGeneration.cmake
A lldb/tools/lldb-rpc/LLDBRPCHeaders.cmake
R lldb/tools/lldb-rpc/lldb-rpc-gen/lldb-rpc-gen.cpp
R lldb/tools/lldb-rpc/lldb-rpc-gen/server/RPCServerHeaderEmitter.cpp
R lldb/tools/lldb-rpc/lldb-rpc-gen/server/RPCServerHeaderEmitter.h
R lldb/tools/lldb-rpc/lldb-rpc-gen/server/RPCServerSourceEmitter.cpp
R lldb/tools/lldb-rpc/lldb-rpc-gen/server/RPCServerSourceEmitter.h
Log Message:
-----------
Reland "[lldb][RPC] Upstream lldb-rpc-gen tool" (#146969)" Attempt 2 (#148996)
Second attempt at relanding the lldb-rpc-gen tool. This should fix 2
issues:
- An assert that was hitting when building on Linux. The assert would
hit in the server source emitter, specifically when attemping to
determine the storage size for a return type is that is a pointer, but
isn't a const char *, const char ** or void pointer.
The assert would hit when attempting to generate
SBAttachInfo::GetProcessPluginName, which returns a const char *
(meaning it shouldn't have been in the code block for the assert at
all). The reason that it was hitting the assert when generating this
function is that lldb_rpc_gen::TypeIsConstCharPtr was returning false
for this function even though it did return a const char *. This was
happening because when checking the return type for a const char *,
TypeIsConstCharPtr would only check that the underlying type was a
signed char. This failed on Linux (but was fine on Darwin), as the
underlying type also needs to be checked for being an unsigned char.
- Cross compiling support
The build for lldb-rpc-gen had no support for cross compiling and as
such, the sources generated for lldb-rpc-gen would get compiled too
early in phase 2 when cross compiling, before the Clang toolchain was
built and this led to an error when trying to include stdlib files. This
reland splits this build into 2 by building the tool first and then
compiling the sources in the second stage of the cross-compiled build.
Original PR Description:
This commit upstreams the lldb-rpc-gen tool, a ClangTool that generates
the LLDB RPC client and server interfaces. This tool, as well as LLDB
RPC itself is built by default. If it needs to be disabled, put
-DLLDB_BUILD_LLDBRPC=OFF in your CMake invocation.
https://discourse.llvm.org/t/rfc-upstreaming-lldb-rpc/85804
Original PR Link:
github.com/llvm/llvm-project/pull/138031
Commit: 2238365a6589fcdb196c850520585a8ec466e09c
https://github.com/llvm/llvm-project/commit/2238365a6589fcdb196c850520585a8ec466e09c
Author: Aiden Grossman <aidengrossman at google.com>
Date: 2025-07-24 (Thu, 24 Jul 2025)
Changed paths:
M .ci/compute_projects_test.py
M .ci/metrics/metrics.py
Log Message:
-----------
[CI] Minor script cleanups
The metrics script did not have a license header or a docstring. The
compute_projects_test.py file had a placeholder module level docstring
that I edited into something more reasonable.
Commit: f509b0c33aebc264c379fd66c25fa48ee61f7ec1
https://github.com/llvm/llvm-project/commit/f509b0c33aebc264c379fd66c25fa48ee61f7ec1
Author: Jordan Rupprecht <rupprecht at google.com>
Date: 2025-07-23 (Wed, 23 Jul 2025)
Changed paths:
M utils/bazel/llvm-project-overlay/libc/utils/MPCWrapper/BUILD.bazel
Log Message:
-----------
[bazel] Port #150303 (#150351)
Commit: 7f66a83c1224ccef066625f01223d8aa6c0c03c2
https://github.com/llvm/llvm-project/commit/7f66a83c1224ccef066625f01223d8aa6c0c03c2
Author: Jordan Rupprecht <rupprecht at google.com>
Date: 2025-07-23 (Wed, 23 Jul 2025)
Changed paths:
M utils/bazel/llvm_configs/abi-breaking.h.cmake
Log Message:
-----------
[bazel] Port #149198 (#150352)
Commit: dfe9fcc9a6b40dfa01ce5884fdc185912ccda8e3
https://github.com/llvm/llvm-project/commit/dfe9fcc9a6b40dfa01ce5884fdc185912ccda8e3
Author: Chelsea Cassanova <chelsea_cassanova at apple.com>
Date: 2025-07-23 (Wed, 23 Jul 2025)
Changed paths:
M lldb/source/API/CMakeLists.txt
M lldb/tools/lldb-rpc/LLDBRPCHeaders.cmake
Log Message:
-----------
[lldb][headers] Fix header staging target for RPC (#150355)
This commit fixes the target that stages headers in the build dir's
include directory so that the headers are staged correctly so that the
target for liblldbrpc-headers can depend on it properly
Commit: 8e9912a1a264e294ecf48dd8bf7d642d41aa5829
https://github.com/llvm/llvm-project/commit/8e9912a1a264e294ecf48dd8bf7d642d41aa5829
Author: Jordan Rupprecht <rupprecht at google.com>
Date: 2025-07-23 (Wed, 23 Jul 2025)
Changed paths:
M utils/bazel/llvm-project-overlay/libc/BUILD.bazel
M utils/bazel/llvm-project-overlay/libc/test/src/string/BUILD.bazel
M utils/bazel/llvm-project-overlay/libc/utils/MPFRWrapper/BUILD.bazel
Log Message:
-----------
[bazel] Port #150303 some more (#150358)
Commit: 5024fc18b87561af45323db38ee93c1d57565772
https://github.com/llvm/llvm-project/commit/5024fc18b87561af45323db38ee93c1d57565772
Author: Longsheng Mou <longshengmou at gmail.com>
Date: 2025-07-24 (Thu, 24 Jul 2025)
Changed paths:
M mlir/docs/Rationale/RationaleLinalgDialect.md
Log Message:
-----------
[mlir][docs] Fix broken links of LIFT (#150152)
Fixes #150080.
Commit: 3eb49c482c3d14d5e0c192434980aa57fe87c453
https://github.com/llvm/llvm-project/commit/3eb49c482c3d14d5e0c192434980aa57fe87c453
Author: Longsheng Mou <longshengmou at gmail.com>
Date: 2025-07-24 (Thu, 24 Jul 2025)
Changed paths:
M mlir/include/mlir/IR/OpDefinition.h
M mlir/include/mlir/Parser/Parser.h
M mlir/lib/Analysis/SliceAnalysis.cpp
M mlir/lib/Dialect/Affine/IR/AffineOps.cpp
M mlir/lib/Dialect/GPU/Transforms/EliminateBarriers.cpp
M mlir/lib/Dialect/GPU/Transforms/MemoryPromotion.cpp
M mlir/lib/Dialect/Linalg/IR/LinalgInterfaces.cpp
M mlir/lib/Dialect/Linalg/Utils/Utils.cpp
M mlir/lib/Dialect/OpenACC/IR/OpenACC.cpp
M mlir/lib/Dialect/SCF/IR/SCF.cpp
M mlir/lib/Dialect/SCF/TransformOps/SCFTransformOps.cpp
M mlir/lib/Dialect/SCF/Transforms/BufferizableOpInterfaceImpl.cpp
M mlir/lib/Dialect/Shape/Transforms/BufferizableOpInterfaceImpl.cpp
M mlir/lib/IR/SymbolTable.cpp
M mlir/lib/Target/LLVMIR/Dialect/OpenMP/OpenMPToLLVMIRTranslation.cpp
M mlir/lib/Transforms/CSE.cpp
M mlir/lib/Transforms/Utils/RegionUtils.cpp
M mlir/test/lib/Analysis/TestCFGLoopInfo.cpp
M mlir/test/lib/Dialect/Test/TestPatterns.cpp
Log Message:
-----------
[mlir][NFC] Use `hasOneBlock` instead of `llvm::hasSingleElement(region)` (#149809)
Commit: 1b901e956b1fab56f4457c97c4d6cb43d0076abf
https://github.com/llvm/llvm-project/commit/1b901e956b1fab56f4457c97c4d6cb43d0076abf
Author: Fangrui Song <i at maskray.me>
Date: 2025-07-23 (Wed, 23 Jul 2025)
Changed paths:
M llvm/include/llvm/MC/MCSection.h
Log Message:
-----------
MC: Declare MCFragment before MCSection
... so that we can restore `MCFragment DummyFragment;` within
`MCSection` (reverting part of
eedc72b45e953bd21cb5c772b8fd24b414894042).
This is required to remove `allocInitialFragment` from `MCContext`
and postpone initial fragment creation to `changeSection`
to address some design issues.
Pull Request: https://github.com/llvm/llvm-project/pull/150180
Commit: 992118cb4deab139ae384bb85f03225a9a21b008
https://github.com/llvm/llvm-project/commit/992118cb4deab139ae384bb85f03225a9a21b008
Author: Philip Reames <preames at rivosinc.com>
Date: 2025-07-23 (Wed, 23 Jul 2025)
Changed paths:
M llvm/lib/CodeGen/InterleavedAccessPass.cpp
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-interleaved-access.ll
Log Message:
-----------
[IA] Add masked.load/store support for shuffle (de)interleave load/store (#150241)
This completes the basic support for masked.laod and masked.store in
InterleaveAccess. The backend already added via the intrinsic lowering
path and the common code structure (in RISCV at least).
Note that this isn't enough to enable in LV yet. We still need support
for recognizing an interleaved mask via a shufflevector in getMask.
Commit: 5f35f06e5f50f5e2797cebf1e6204e1a15fc83bc
https://github.com/llvm/llvm-project/commit/5f35f06e5f50f5e2797cebf1e6204e1a15fc83bc
Author: Kazu Hirata <kazu at google.com>
Date: 2025-07-23 (Wed, 23 Jul 2025)
Changed paths:
M lldb/tools/lldb-rpc-gen/RPCCommon.cpp
M lldb/tools/lldb-rpc-gen/lldb-rpc-gen.cpp
Log Message:
-----------
[lldb] Fix warnings
This patch fixes:
lldb/tools/lldb-rpc-gen/RPCCommon.cpp:197:13: error: unused variable
'CheckTypeForLLDBPrivate' [-Werror,-Wunused-variable]
lldb/tools/lldb-rpc-gen/lldb-rpc-gen.cpp:105:18: error: unused
variable 'HasCallbackParameter' [-Werror,-Wunused-variable]
Commit: afbf86e719e11aeb9e2b944cd5cf914bdab12426
https://github.com/llvm/llvm-project/commit/afbf86e719e11aeb9e2b944cd5cf914bdab12426
Author: Qi Zhao <zhaoqi01 at loongson.cn>
Date: 2025-07-24 (Thu, 24 Jul 2025)
Changed paths:
M llvm/test/CodeGen/LoongArch/lasx/build-vector.ll
M llvm/test/CodeGen/LoongArch/lsx/build-vector.ll
Log Message:
-----------
[LoongArch] Pre-commit tests for build_vector with undef elements inserting
Commit: 42017c661c131ff85aa70345e100fa486db66bfa
https://github.com/llvm/llvm-project/commit/42017c661c131ff85aa70345e100fa486db66bfa
Author: lntue <lntue at google.com>
Date: 2025-07-24 (Thu, 24 Jul 2025)
Changed paths:
M libc/include/CMakeLists.txt
M libc/src/stdio/printf_core/CMakeLists.txt
Log Message:
-----------
[libc] Add missing libc.include.inttypes for targets including <inttypes.h>. (#150345)
Commit: 3e4be55c6b942fdcf1732b1a537e2477567ece54
https://github.com/llvm/llvm-project/commit/3e4be55c6b942fdcf1732b1a537e2477567ece54
Author: Uday Bondhugula <uday at polymagelabs.com>
Date: 2025-07-24 (Thu, 24 Jul 2025)
Changed paths:
M mlir/lib/Dialect/Affine/Analysis/Utils.cpp
M mlir/lib/Dialect/Affine/Transforms/LoopFusion.cpp
M mlir/test/Dialect/Affine/loop-fusion-4.mlir
Log Message:
-----------
[MLIR][Affine] Improve sibling fusion - handle memrefs from memref defining nodes (#149641)
Improve sibling fusion - handle memrefs from memref defining nodes which
were not being considered.
Remove the unnecessary restriction from MDG memref edge iteration to
restrict to affine.for ops. Nodes in the MDG could be other ops as well.
Fixes: https://github.com/llvm/llvm-project/issues/61825
Commit: 0a2b97931014c34bef02700a9e9f42c304b54390
https://github.com/llvm/llvm-project/commit/0a2b97931014c34bef02700a9e9f42c304b54390
Author: Craig Topper <craig.topper at sifive.com>
Date: 2025-07-23 (Wed, 23 Jul 2025)
Changed paths:
M llvm/lib/Target/RISCV/RISCVFeatures.td
M llvm/test/CodeGen/RISCV/attributes.ll
M llvm/test/MC/RISCV/attribute-arch.s
Log Message:
-----------
[RISCV] Add missing Zvl dependencies for XSfvqmaccdod/XSfvqmaccqoq/XSfvfwmaccqqq. (#150346)
These have an LMUL=1 operand that must have a multiple of 16 or 32
elements in it. This places a lower bound on the VLEN.
Commit: 5bbf01f7cbd98f9bf79eeaeecd43c28e38cb94fa
https://github.com/llvm/llvm-project/commit/5bbf01f7cbd98f9bf79eeaeecd43c28e38cb94fa
Author: Fangrui Song <i at maskray.me>
Date: 2025-07-23 (Wed, 23 Jul 2025)
Changed paths:
M llvm/test/MC/ELF/section-sym-err.s
R llvm/test/MC/ELF/section-sym-err2.s
M llvm/test/MC/ELF/section-sym2.s
Log Message:
-----------
MC,test: Improve section symbol test
Commit: 75e60e745b029a3aaa199e8848e5542fd8a80395
https://github.com/llvm/llvm-project/commit/75e60e745b029a3aaa199e8848e5542fd8a80395
Author: hidekisaito <hidekido at amd.com>
Date: 2025-07-23 (Wed, 23 Jul 2025)
Changed paths:
M offload/test/lit.cfg
Log Message:
-----------
[AMDGPU][Offload][LIT] Run unified_shared_memory tests on gfx950 (#150372)
Enables 9 more tests
Commit: b4edd827e4f71c2a0fcb13f79de7eae4545f0aea
https://github.com/llvm/llvm-project/commit/b4edd827e4f71c2a0fcb13f79de7eae4545f0aea
Author: Amina Chabane <amina.chabane at arm.com>
Date: 2025-07-24 (Thu, 24 Jul 2025)
Changed paths:
M llvm/lib/Target/AArch64/AArch64InstrInfo.td
A llvm/test/CodeGen/AArch64/load-zext-bitcast.ll
Log Message:
-----------
[AArch64] Remove redundant FMOV for zero-extended i32/i16 loads to f64 (#146920)
Previously, a separate load, zext and FMOV instruction was emitted. This
patch adds a new TableGen pattern to avoid the unnecessary FMOV. A test
is included in test/CodeGen/AArch64/load_u64_from_u32.ll
Commit: 31db0f0a7ae43981fdfadc693662c239f921a05b
https://github.com/llvm/llvm-project/commit/31db0f0a7ae43981fdfadc693662c239f921a05b
Author: Shashi Shankar <shashishankar1687 at gmail.com>
Date: 2025-07-24 (Thu, 24 Jul 2025)
Changed paths:
M clang/docs/ReleaseNotes.rst
M clang/lib/Sema/SemaAvailability.cpp
A clang/test/Sema/implicit-special-member-deprecated.cpp
Log Message:
-----------
[Clang] Suppress deprecated field warnings in implicit functions definitions (#147400)
Do not warn on deprecated member used in an implicit definition (such as a defaulted special member function).
Co-authored-by: Corentin Jabot <corentinjabot at gmail.com>
Fixes #147293
Commit: eb43b79765ad8218aa5061fe4e695e8da4b5d849
https://github.com/llvm/llvm-project/commit/eb43b79765ad8218aa5061fe4e695e8da4b5d849
Author: Changpeng Fang <changpeng.fang at amd.com>
Date: 2025-07-24 (Thu, 24 Jul 2025)
Changed paths:
M llvm/lib/Target/AMDGPU/GCNSubtarget.h
M llvm/test/CodeGen/AMDGPU/GlobalISel/mul.ll
M llvm/test/CodeGen/AMDGPU/bf16-conversions.ll
M llvm/test/CodeGen/AMDGPU/branch-relaxation-gfx1250.ll
M llvm/test/CodeGen/AMDGPU/carryout-selection.ll
M llvm/test/CodeGen/AMDGPU/flat-saddr-atomics.ll
M llvm/test/CodeGen/AMDGPU/flat-saddr-load.ll
M llvm/test/CodeGen/AMDGPU/literal64.ll
M llvm/test/CodeGen/AMDGPU/packed-fp32.ll
M llvm/test/CodeGen/AMDGPU/scale-offset-flat.ll
Log Message:
-----------
[AMDGPU] Disable SGPR read hazard mitigation for gfx1250 (#150344)
Co-authored-by: Jay Foad <Jay.Foad at amd.com>
Commit: 07faafe4a4d0a5bd82b648aa9717783f001ddfae
https://github.com/llvm/llvm-project/commit/07faafe4a4d0a5bd82b648aa9717783f001ddfae
Author: Younan Zhang <zyn7109 at gmail.com>
Date: 2025-07-24 (Thu, 24 Jul 2025)
Changed paths:
M clang/lib/Sema/SemaTemplateDeduction.cpp
M clang/test/SemaTemplate/deduction-guide.cpp
Log Message:
-----------
[Clang] Fix a partial ordering bug involving CTAD injected template arguments (#149782)
The synthesized deduction guides use injected template arguments for
distinguishment of explicit and implicit deduction guides.
In partial ordering, we may substitute into these injected types when
checking consistency. Properly substituting them needs the instantiated
class template specializations which isn't the case at that point. So
instead, we check their template specialization types.
No release note because I think we want a backport, after baking it for
a couple of days.
Fixes https://github.com/llvm/llvm-project/issues/134613
Commit: 78ccaf1295b35a62d3d5bcda76d83eae788a6f48
https://github.com/llvm/llvm-project/commit/78ccaf1295b35a62d3d5bcda76d83eae788a6f48
Author: Fabian Ritter <fabian.ritter at amd.com>
Date: 2025-07-24 (Thu, 24 Jul 2025)
Changed paths:
M llvm/lib/CodeGen/MIRPrinter.cpp
M llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-gep-flags.ll
M llvm/utils/update_mir_test_checks.py
Log Message:
-----------
[update_mir_test_checks] Add missing MIFlags (#150012)
If the update_mir_test_checks.py script is aware of MIFlags, it can produce
meaningful identifiers in generated FileCheck lines. A few MIFlags that were
introduced more recently have been missing from the script.
Ideally, the MIFlags would be specified in a single place and automatically
made known to the script to avoid this divergence, but for now adding a comment
pointing to the script at the place where the MIFlags are printed seems like a
reasonable trade-off.
This PR only regenerates check lines for a single test as an example of the
effect; other affected tests are not regenerated for now to avoid unnecessary
test churn.
Commit: 531cf8298b08eacdf670bac8c28db97a5dc8cb01
https://github.com/llvm/llvm-project/commit/531cf8298b08eacdf670bac8c28db97a5dc8cb01
Author: Eric Li <li.zhe.hua at gmail.com>
Date: 2025-07-24 (Thu, 24 Jul 2025)
Changed paths:
M clang/lib/Format/ContinuationIndenter.cpp
M clang/unittests/Format/FormatTest.cpp
Log Message:
-----------
[clang-format] Stop ctor initializer from being inlined (#150361)
The colon in a constructor's initializer list triggers the inlining of a
nested block as if it was a conditional operator expression. This
prevents line breaks under certain circumstances when the initializer
list contains braced initializers, which in turn prevents the line
formatter from finding a solution.
In this commit we exclude colons that are a constructor initializer
colon from consideration of nested block inlining.
Fixes #97242.
Fixes #81822.
Commit: e9de32fd159d30cfd6fcc861b57b7e99ec2742ab
https://github.com/llvm/llvm-project/commit/e9de32fd159d30cfd6fcc861b57b7e99ec2742ab
Author: Antonio Frighetto <me at antoniofrighetto.com>
Date: 2025-07-24 (Thu, 24 Jul 2025)
Changed paths:
M llvm/lib/Transforms/Scalar/SimpleLoopUnswitch.cpp
M llvm/test/Transforms/LICM/PR116813-memoryssa-outdated.ll
M llvm/test/Transforms/PhaseOrdering/AArch64/block_scaling_decompr_8bit.ll
M llvm/test/Transforms/SimpleLoopUnswitch/exponential-nontrivial-unswitch-nested.ll
M llvm/test/Transforms/SimpleLoopUnswitch/exponential-nontrivial-unswitch-nested2.ll
M llvm/test/Transforms/SimpleLoopUnswitch/exponential-nontrivial-unswitch.ll
M llvm/test/Transforms/SimpleLoopUnswitch/exponential-switch-unswitch.ll
M llvm/test/Transforms/SimpleLoopUnswitch/guards.ll
M llvm/test/Transforms/SimpleLoopUnswitch/inject-invariant-conditions.ll
M llvm/test/Transforms/SimpleLoopUnswitch/invalidate-block-and-loop-dispositions.ll
M llvm/test/Transforms/SimpleLoopUnswitch/nontrivial-unswitch-freeze.ll
M llvm/test/Transforms/SimpleLoopUnswitch/nontrivial-unswitch-select.ll
M llvm/test/Transforms/SimpleLoopUnswitch/nontrivial-unswitch.ll
M llvm/test/Transforms/SimpleLoopUnswitch/partial-unswitch-loop-and-block-dispositions.ll
M llvm/test/Transforms/SimpleLoopUnswitch/partial-unswitch.ll
A llvm/test/Transforms/SimpleLoopUnswitch/pr138509.ll
M llvm/test/Transforms/SimpleLoopUnswitch/update-scev-3.ll
Log Message:
-----------
[SimpleLoopUnswitch] Record loops from unswitching non-trivial conditions
Track newly-cloned loops coming from unswitching non-trivial invariant
conditions, so as to prevent conditions in such cloned blocks from
being unswitched again.
Fixes: https://github.com/llvm/llvm-project/issues/138509.
Commit: c049732d7f946492ec3f6f5e7c3b845b7133fca8
https://github.com/llvm/llvm-project/commit/c049732d7f946492ec3f6f5e7c3b845b7133fca8
Author: Benjamin Maxwell <benjamin.maxwell at arm.com>
Date: 2025-07-24 (Thu, 24 Jul 2025)
Changed paths:
M clang/lib/Sema/SemaDeclAttr.cpp
A clang/test/Sema/unsupported-arm-streaming.cpp
Log Message:
-----------
[clang] Fix crash when diagnosing unsupported attributes (#150333)
In #141305, the attribute argument was (unintentionally) removed from
the diagnostic emission.
Fixes #150237
Commit: 98562ffaaa74ebebfcfaf42f6604c736637e0d46
https://github.com/llvm/llvm-project/commit/98562ffaaa74ebebfcfaf42f6604c736637e0d46
Author: Sergei Barannikov <barannikov88 at gmail.com>
Date: 2025-07-24 (Thu, 24 Jul 2025)
Changed paths:
M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
M llvm/lib/Target/AArch64/AArch64InstrInfo.td
M llvm/lib/Target/AArch64/AArch64RegisterInfo.td
M llvm/lib/Target/AArch64/AArch64SelectionDAGInfo.cpp
M llvm/test/CodeGen/AArch64/abds-neg.ll
M llvm/test/CodeGen/AArch64/abds.ll
M llvm/test/CodeGen/AArch64/abdu-neg.ll
Log Message:
-----------
[AArch64] Fix the type of NZCV operands/results (#150313)
Consistently use `FlagsVT` for operands/results of nodes that
consume/produce NZCV flags.
Previously, some of the operands/results had incorrect `MVT::Glue` type
while others had `MVT_CC` type, which is supposed to be used for
condition codes (`AArch64CC::CondCode` enum).
Found by #150125.
Commit: be6bed4dc6e346d316a910ee7cb742ece791d855
https://github.com/llvm/llvm-project/commit/be6bed4dc6e346d316a910ee7cb742ece791d855
Author: Nikita Popov <npopov at redhat.com>
Date: 2025-07-24 (Thu, 24 Jul 2025)
Changed paths:
M llvm/lib/Transforms/InstCombine/InstCombineLoadStoreAlloca.cpp
A llvm/test/Transforms/InstCombine/pr150338.ll
Log Message:
-----------
[InstCombine] Remove instructions before+after unreachable at same time
There is no need to first remove the instructions before and then
the ones after in two different worklist iterations. We don't need
to worry about change reporting here, as the functions do that
themselves.
This avoids the issue in #150338, but not really in a principled
way. It's possible that we will have to allow poison arguments
to lifetime.start/lifetime.end again if this turns out to be a
recurring problem.
Commit: 53dfbe83861cdb2948ac25376ec6524bc68e8c3e
https://github.com/llvm/llvm-project/commit/53dfbe83861cdb2948ac25376ec6524bc68e8c3e
Author: x12301450 <x12301450 at 163.com>
Date: 2025-07-24 (Thu, 24 Jul 2025)
Changed paths:
M mlir/lib/Target/LLVM/CMakeLists.txt
Log Message:
-----------
[CMake]fix CUDAToolkit_LIBRARY_ROOT DEFINED check (#146472)
This PR fixes #146344 by remove the brace of `CUDAToolkit_LIBRARY_ROOT`.
Commit: 3d8db8ef50b7e59d5a1943ddc14597327eff88fd
https://github.com/llvm/llvm-project/commit/3d8db8ef50b7e59d5a1943ddc14597327eff88fd
Author: Tobias Hieta <tobias at hieta.se>
Date: 2025-07-24 (Thu, 24 Jul 2025)
Changed paths:
M clang-tools-extra/docs/ReleaseNotes.rst
M clang/docs/ReleaseNotes.rst
M flang/docs/ReleaseNotes.md
M lld/docs/ReleaseNotes.rst
M llvm/docs/ReleaseNotes.md
Log Message:
-----------
Clear release notes on main for LLVM 22
Commit: a073cbbb1aeaaeac01b12e818fe47e4c04080aac
https://github.com/llvm/llvm-project/commit/a073cbbb1aeaaeac01b12e818fe47e4c04080aac
Author: circuit10 <heath.mitchell27 at gmail.com>
Date: 2025-07-24 (Thu, 24 Jul 2025)
Changed paths:
M llvm/lib/Target/X86/AsmParser/X86AsmParser.cpp
A llvm/test/MC/X86/intel-syntax-parentheses.s
Log Message:
-----------
[X86] Fix misassemble due to not storing registers to state machine on RParen (#150252)
This fixes #116883.
The x86 parser saves any register it encounters to a TmpReg field in its
state machine, then on encountering the next valid token immediately
afterwards saves it to either BaseReg, or IndexReg if BaseReg was
already filled. However, this saving logic was missing on the RParen
token handler, causing the parser to "forget" the register immediately
beforehand. This also would prevent later validation logic from
detecting the addressing mode as invalid, leading to a silent
misassembly rather than an error.
Commit: d52675e0a7daac028612c34530fbcbd6ca62a1fb
https://github.com/llvm/llvm-project/commit/d52675e0a7daac028612c34530fbcbd6ca62a1fb
Author: Mark Murray <mark.murray at arm.com>
Date: 2025-07-24 (Thu, 24 Jul 2025)
Changed paths:
M lld/ELF/InputFiles.cpp
A lld/test/ELF/aarch64-build-attributes-be.s
A lld/test/ELF/aarch64-build-attributes-err.s
A lld/test/ELF/aarch64-build-attributes-invalid.s
A lld/test/ELF/aarch64-build-attributes-malformed.s
A lld/test/ELF/aarch64-build-attributes-mixed.s
M lld/test/ELF/aarch64-build-attributes.s
M llvm/include/llvm/Support/AArch64AttributeParser.h
M llvm/lib/Support/AArch64AttributeParser.cpp
Log Message:
-----------
[lld][AArch64][Build Attributes] Add support for AArch64 Build Attributes (#147970)
This patch enables lld to read AArch64 Build Attributes and convert them
into GNU Properties.
Changes:
- Parses AArch64 Build Attributes from input object files.
- Converts known attributes into corresponding GNU Properties.
- Merges attributes when linking multiple objects.
Spec reference:
https://github.com/ARM-software/abi-aa/pull/230/files#r1030
Co-authored-by: Sivan Shani <sivan.shani at arm.com>
---------
Co-authored-by: Sivan Shani <sivan.shani at arm.com>
Commit: 94aa08a3b0e979e6977619064a27ca74bb15fcf6
https://github.com/llvm/llvm-project/commit/94aa08a3b0e979e6977619064a27ca74bb15fcf6
Author: Paul Walker <paul.walker at arm.com>
Date: 2025-07-24 (Thu, 24 Jul 2025)
Changed paths:
M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
M llvm/test/CodeGen/AArch64/arm64-fold-lshr.ll
M llvm/test/CodeGen/AArch64/sve-ld1-addressing-mode-reg-reg.ll
Log Message:
-----------
[LLVM][CodeGen][SVE] Don't combine shifts at the expense of addressing modes. (#149873)
Fixes https://github.com/llvm/llvm-project/issues/149654
Commit: 1a32bcb4379fb90d2b764ac33b917de1431c6b16
https://github.com/llvm/llvm-project/commit/1a32bcb4379fb90d2b764ac33b917de1431c6b16
Author: cvspvr <csprv at outlook.com>
Date: 2025-07-24 (Thu, 24 Jul 2025)
Changed paths:
M lldb/source/Host/windows/MainLoopWindows.cpp
M lldb/source/Host/windows/PipeWindows.cpp
Log Message:
-----------
[lldb] Allow building using Mingw-w64 on Windows. (#150398)
I wasn't able to build lldb using Mingw-w64 on Windows without changing
these 3 lines. It seems like `std::atomic<bool>` wasn't being found
without `#include <atomic>` and `ceil` was defaulting to `std::ceil`
instead of `std::chrono::ceil`, but I'm not smart enough to know the
root cause. I'm sure I'm not the first people to try and compile lldb
(and clang and lld) with Mingw-w64 and I don't know if something is
wrong with my Mingw-w64, but my changes shouldn't have any affect if
they aren't needed.
Commit: cd1b84caa852bb3f5469ab3da93ccb9dfafa7089
https://github.com/llvm/llvm-project/commit/cd1b84caa852bb3f5469ab3da93ccb9dfafa7089
Author: Pierre van Houtryve <pierre.vanhoutryve at amd.com>
Date: 2025-07-24 (Thu, 24 Jul 2025)
Changed paths:
M clang/lib/CodeGen/TargetBuiltins/AMDGPU.cpp
M clang/test/CodeGenCXX/builtin-amdgcn-fence.cpp
M llvm/docs/AMDGPUUsage.rst
M llvm/lib/Target/AMDGPU/SIMemoryLegalizer.cpp
M llvm/test/CodeGen/AMDGPU/memory-legalizer-fence-mmra-global.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-fence-mmra-local.ll
Log Message:
-----------
[NFC][AMDGPU] Rename "amdgpu-as" to "amdgpu-synchronize-as" (#148627)
"amdgpu-as" is way too vague and doesn't give enough context.
We may want to support it on normal atomics too, to control the synchronized (ordered) AS.
If we do that, the name has to be less vague.
Commit: 9c5f8ec561e059bdaa585e75209cb5c658953e90
https://github.com/llvm/llvm-project/commit/9c5f8ec561e059bdaa585e75209cb5c658953e90
Author: Pierre van Houtryve <pierre.vanhoutryve at amd.com>
Date: 2025-07-24 (Thu, 24 Jul 2025)
Changed paths:
M llvm/lib/Target/AMDGPU/SIMemoryLegalizer.cpp
Log Message:
-----------
[NFC][AMDGPU] Refactor handling of `amdgpu-synchronize-as` MD on fences (#148630)
Directly plug it into the MMO instead, which is much cleaner.
Commit: 04f5198e3ecb5592cec3297a782b8179f95434bf
https://github.com/llvm/llvm-project/commit/04f5198e3ecb5592cec3297a782b8179f95434bf
Author: Andrew Rogers <andrurogerz at gmail.com>
Date: 2025-07-24 (Thu, 24 Jul 2025)
Changed paths:
M libcxxabi/src/demangle/DemangleConfig.h
M libcxxabi/src/demangle/ItaniumDemangle.h
M llvm/include/llvm/Demangle/Demangle.h
M llvm/include/llvm/Demangle/DemangleConfig.h
M llvm/include/llvm/Demangle/ItaniumDemangle.h
M llvm/include/llvm/Demangle/MicrosoftDemangle.h
M llvm/include/llvm/Demangle/MicrosoftDemangleNodes.h
Log Message:
-----------
[llvm] annotate interfaces in Demangle for DLL export (#147564)
## Purpose
This patch is one in a series of code-mods that annotate LLVM’s public
interface for export. This patch annotates the `Demangle` interface with
a new `DEMANGLE_ABI` annotation, which behaves like the `LLVM_ABI`. This
annotation currently has no meaningful impact on the LLVM build;
however, it is a prerequisite to support an LLVM Windows DLL (shared
library) build.
## Overview
1. Add a new `Demangle/Visibility.h` header file that defines a new
`DEMANGLE_ABI` macro. The macro resolves to the proper DLL export/import
annotation on Windows and a "default" visibility annotation elsewhere.
2. Add a new `LLVM_ENABLE_DEMANGLE_EXPORT_ANNOTATIONS ` `#cmakedefine`
that is used to gate the definition of `DEMANGLE_ABI`.
3. Code-mod annotate the public `Demangle` interface using the
[Interface Definition Scanner (IDS)](https://github.com/compnerd/ids)
tool.
4. Manually fix-up `#include` statements for consistency.
5. Format the changes with `clang-format`.
6. Add a "stub" version of `Visibility.h` under `libcxxabi/src/demangle`
that always defines `DEMANGLE_ABI` to nothing.
7. Update the canonical `libcxxabi/src/demangle/ItaniumDemangle.h`
instead of the llvm copy, and run `cp-to-llvm.sh` to ensure the llvm
copy matches. NOTE: we rely on `ccp-to-llvm.sh` not copying
`Visibillity.h` as is already the case for `DemangleConfig.h`.
## Background
This PR follows the pattern established with the `llvm-c` changes made
in #141701.
This effort is tracked in #109483. Additional context is provided in
[this
discourse](https://discourse.llvm.org/t/psa-annotating-llvm-public-interface/85307),
and documentation for `LLVM_ABI` and related annotations is found in the
LLVM repo
[here](https://github.com/llvm/llvm-project/blob/main/llvm/docs/InterfaceExportAnnotations.rst).
## Validation
Local builds and tests to validate cross-platform compatibility. This
included llvm, clang, and lldb on the following configurations:
- Windows with MSVC
- Windows with Clang
- Linux with GCC
- Linux with Clang
- Darwin with Clang
---------
Co-authored-by: Louis Dionne <ldionne.2 at gmail.com>
Commit: db8a389f889c4eeaf024da117102a33aa3f577b7
https://github.com/llvm/llvm-project/commit/db8a389f889c4eeaf024da117102a33aa3f577b7
Author: Aaron Ballman <aaron at aaronballman.com>
Date: 2025-07-24 (Thu, 24 Jul 2025)
Changed paths:
M clang/docs/ReleaseNotes.rst
Log Message:
-----------
[Docs] Add back lost release notes; NFC
When release notes were cleared on ``main``, there were some notes lost
because the changes happened after the branch point for 21.x. This
restores the lost notes.
Commit: bfd73a5161608e6355f7db87dc5f5afee56d7e2f
https://github.com/llvm/llvm-project/commit/bfd73a5161608e6355f7db87dc5f5afee56d7e2f
Author: Qinkun Bao <qinkun at google.com>
Date: 2025-07-24 (Thu, 24 Jul 2025)
Changed paths:
M clang-tools-extra/clangd/refactor/tweaks/CMakeLists.txt
R clang-tools-extra/clangd/refactor/tweaks/OverridePureVirtuals.cpp
M clang-tools-extra/clangd/unittests/CMakeLists.txt
R clang-tools-extra/clangd/unittests/tweaks/OverridePureVirtualsTests.cpp
Log Message:
-----------
Revert "[clangd] Add tweak to override pure virtuals (#139348)" (#150404)
This reverts commit 7355ea3f6b214d1569da43d02f9a166ff15012e6.
Buildbot failures:
UBsan
https://lab.llvm.org/buildbot/#/builders/25/builds/10010
Fast
https://lab.llvm.org/buildbot/#/builders/169/builds/13150
Commit: 633948f5cbb08295fff4704146c42fff524929a4
https://github.com/llvm/llvm-project/commit/633948f5cbb08295fff4704146c42fff524929a4
Author: Baranov Victor <bar.victor.2002 at gmail.com>
Date: 2025-07-24 (Thu, 24 Jul 2025)
Changed paths:
M clang-tools-extra/docs/ReleaseNotes.rst
Log Message:
-----------
[clang-tools-extra][Docs][NFC] Add back lost release notes (#150409)
When release notes were cleared on ``main``, clang-tools-extra project
already cleared release notes and commit
3d8db8ef50b7e59d5a1943ddc14597327eff88fd flushed them. This patch
restores lost release notes.
Commit: d5d8eaf5e05e88c9b5873ad2383de67a7683db1b
https://github.com/llvm/llvm-project/commit/d5d8eaf5e05e88c9b5873ad2383de67a7683db1b
Author: Nathan Gauër <brioche at google.com>
Date: 2025-07-24 (Thu, 24 Jul 2025)
Changed paths:
M llvm/utils/UpdateTestChecks/asm.py
Log Message:
-----------
[utils] Add spirv triple to update_llc_test_checks (#150223)
The 32bit and 64bit flavors of SPIR-V were supported, but the logical
version of the triple was lacking. Adding it.
Commit: 588845defd09359a8b87db339b563af848cf45a7
https://github.com/llvm/llvm-project/commit/588845defd09359a8b87db339b563af848cf45a7
Author: Maksim Levental <maksim.levental at gmail.com>
Date: 2025-07-24 (Thu, 24 Jul 2025)
Changed paths:
M mlir/lib/Dialect/SCF/IR/SCF.cpp
M mlir/lib/Dialect/SCF/TransformOps/SCFTransformOps.cpp
M mlir/lib/Dialect/SCF/Transforms/BufferizableOpInterfaceImpl.cpp
M mlir/lib/Dialect/SCF/Transforms/ForToWhile.cpp
M mlir/lib/Dialect/SCF/Transforms/ForallToParallel.cpp
M mlir/lib/Dialect/SCF/Transforms/LoopPipelining.cpp
M mlir/lib/Dialect/SCF/Transforms/LoopSpecialization.cpp
M mlir/lib/Dialect/SCF/Transforms/ParallelLoopFusion.cpp
M mlir/lib/Dialect/SCF/Transforms/ParallelLoopTiling.cpp
M mlir/lib/Dialect/SCF/Transforms/StructuralTypeConversions.cpp
M mlir/lib/Dialect/SCF/Transforms/TileUsingInterface.cpp
M mlir/lib/Dialect/SCF/Transforms/UpliftWhileToFor.cpp
M mlir/lib/Dialect/SCF/Transforms/WrapInZeroTripCheck.cpp
M mlir/lib/Dialect/SCF/Utils/Utils.cpp
M mlir/lib/Dialect/SMT/IR/SMTDialect.cpp
M mlir/lib/Dialect/SMT/IR/SMTOps.cpp
M mlir/lib/Dialect/Shape/IR/Shape.cpp
M mlir/lib/Dialect/Shape/Transforms/BufferizableOpInterfaceImpl.cpp
M mlir/lib/Dialect/Shape/Transforms/OutlineShapeComputation.cpp
M mlir/lib/Dialect/Shape/Transforms/ShapeToShapeLowering.cpp
Log Message:
-----------
[mlir][NFC] update `mlir/Dialect` create APIs (20/n) (#149927)
See https://github.com/llvm/llvm-project/pull/147168 for more info.
Commit: 8fcbd06b25fd0c1b4bc4a4c8775129f7dab1affd
https://github.com/llvm/llvm-project/commit/8fcbd06b25fd0c1b4bc4a4c8775129f7dab1affd
Author: Krzysztof Parzyszek <Krzysztof.Parzyszek at amd.com>
Date: 2025-07-24 (Thu, 24 Jul 2025)
Changed paths:
M flang/lib/Semantics/check-omp-structure.cpp
A flang/test/Semantics/OpenMP/assumed-size-array.f90
Log Message:
-----------
[flang][OpenMP] Avoid analyzing assumed-size array bases (#150324)
A check for character substrings masquerading as array sections was
using expression analyzer on the array base. When this array happened to
be an assumed-size array, the analyzer emitted a semantic error that did
not correspond to any issue with the source code.
To avoid that, check whether the object is an assumed-size array before
using the expression analyzer on it.
While at it, replace the call to GetShape with a simple check for rank,
since that's the only information needed.
Fixes https://github.com/llvm/llvm-project/issues/150297
Commit: 9df8bc953d72eb4b6401ebe210a347ba3956350a
https://github.com/llvm/llvm-project/commit/9df8bc953d72eb4b6401ebe210a347ba3956350a
Author: Igor Wodiany <igor.wodiany at imgtec.com>
Date: 2025-07-24 (Thu, 24 Jul 2025)
Changed paths:
M mlir/include/mlir/Dialect/SPIRV/IR/SPIRVTypes.h
M mlir/lib/Dialect/SPIRV/IR/SPIRVDialect.cpp
M mlir/lib/Target/SPIRV/Deserialization/Deserializer.cpp
M mlir/lib/Target/SPIRV/Serialization/Serializer.cpp
M mlir/test/Dialect/SPIRV/IR/types.mlir
Log Message:
-----------
[mlir][spirv][nfc] Refactor member decorations in StructType (#150218)
This patch makes `==` and `<` for MemberDecorationInfo a friend function
and removes a `hasValue` field. `decorationValue` is also made an
`mlir::Attribute` so `UnitAttr` can be used to represent no-value. This
is consistent with how OpDecorate is handled in the deserializer. Using
`Attribute` will also enable handling non-integer values, however, there
seem to be no such decorations for struct members now.
Commit: bcca57b1f34475e3db74377a1c00a4683a75cf82
https://github.com/llvm/llvm-project/commit/bcca57b1f34475e3db74377a1c00a4683a75cf82
Author: Luke Lau <luke at igalia.com>
Date: 2025-07-24 (Thu, 24 Jul 2025)
Changed paths:
M llvm/lib/Target/RISCV/RISCVVLOptimizer.cpp
M llvm/test/CodeGen/RISCV/rvv/vxrm.mir
Log Message:
-----------
[RISCV] Simplify mask operand check in VLOptimizer. NFC (#150373)
We don't need to lookup the reg class because the MCInstDesc already
gives us this information.
With that we can remove some helper methods, and tighten the assert in
isCandidate because all pseudos at this stage should be defining virtual
registers.
Commit: a647bb4a7ba23b5a7c7484fd5162fef2d10c7068
https://github.com/llvm/llvm-project/commit/a647bb4a7ba23b5a7c7484fd5162fef2d10c7068
Author: Nikita Popov <npopov at redhat.com>
Date: 2025-07-24 (Thu, 24 Jul 2025)
Changed paths:
M llvm/lib/Transforms/Coroutines/Coroutines.cpp
Log Message:
-----------
[Coroutines] Restore accidentally dropped intrinsic IDs
These were unintentionally dropped in #145518. These intrinsics
are not overloaded, so should be part of this list.
Commit: bbc570eef686cffba6c226d78588d930d619e176
https://github.com/llvm/llvm-project/commit/bbc570eef686cffba6c226d78588d930d619e176
Author: Björn Svensson <bjorn.a.svensson at est.tech>
Date: 2025-07-24 (Thu, 24 Jul 2025)
Changed paths:
M clang-tools-extra/clang-tidy/bugprone/SignedCharMisuseCheck.cpp
M clang-tools-extra/docs/ReleaseNotes.rst
A clang-tools-extra/test/clang-tidy/checkers/bugprone/signed-char-misuse-c23.c
Log Message:
-----------
[clang-tidy] Fix false positives on C23 enums in `bugprone-signed-char-misuse` (#149790)
Ignore false positives on C23 enums which allows setting the fixed
underlying type to signed char.
The AST tree for C enums includes a ImplicitCastExp
(that was matched) but this is not the case for C++ enums.
Fixes #145651
---------
Signed-off-by: Björn Svensson <bjorn.a.svensson at est.tech>
Commit: 7ba948004130610ecb3014ce5eab85d730b5be9b
https://github.com/llvm/llvm-project/commit/7ba948004130610ecb3014ce5eab85d730b5be9b
Author: Michael Kruse <llvm-project at meinersbur.de>
Date: 2025-07-24 (Thu, 24 Jul 2025)
Changed paths:
M flang/unittests/CMakeLists.txt
Log Message:
-----------
[Flang] Assign unittests to flang_compile pool (#150041)
#127364 added the FLANG_PARALLEL_COMPILE_JOBS option to limit the number
of parallel compilations of Flang sources which require an unusal amount
of memory. This patch also adds Flang's unittests to this pool that use
about the same amount of memory due to including the same headers.
Commit: 0e42eaa668bc9d0cfd18b20cdd95917af7ea0d26
https://github.com/llvm/llvm-project/commit/0e42eaa668bc9d0cfd18b20cdd95917af7ea0d26
Author: Luke Lau <luke at igalia.com>
Date: 2025-07-24 (Thu, 24 Jul 2025)
Changed paths:
M llvm/test/Analysis/CostModel/RISCV/rvv-shuffle.ll
Log Message:
-----------
[RISCV] Add type based RUN line for vector intrinsic cost model tests. NFC
Commit: baa19c05a3565c930f47ecdbc7fc6693ec1a7c2e
https://github.com/llvm/llvm-project/commit/baa19c05a3565c930f47ecdbc7fc6693ec1a7c2e
Author: Donát Nagy <donat.nagy at ericsson.com>
Date: 2025-07-24 (Thu, 24 Jul 2025)
Changed paths:
M clang/docs/analyzer/checkers.rst
M clang/include/clang/StaticAnalyzer/Checkers/Checkers.td
Log Message:
-----------
[NFC][analyzer] Document optin.portability.UnixAPI (#150005)
This commit provides a brief documentation for the checker
optin.portability.UnixAPI.
Unfortunately the name of this checker is meaninglessly vague and its
functionality is very closely related to unix.Malloc, so it should be
eventually "rebranded" to a more user-friendly presentation.
Commit: 1c3e4e994b4affc7f0314bb3dbecf467fbfcab3e
https://github.com/llvm/llvm-project/commit/1c3e4e994b4affc7f0314bb3dbecf467fbfcab3e
Author: Alan Li <me at alanli.org>
Date: 2025-07-24 (Thu, 24 Jul 2025)
Changed paths:
M mlir/include/mlir/Dialect/AMDGPU/Transforms/Passes.h
M mlir/include/mlir/Dialect/AMDGPU/Transforms/Passes.td
M mlir/include/mlir/Dialect/MemRef/Utils/MemRefUtils.h
M mlir/lib/Dialect/AMDGPU/Transforms/CMakeLists.txt
A mlir/lib/Dialect/AMDGPU/Transforms/FoldMemRefsOps.cpp
M mlir/lib/Dialect/MemRef/Transforms/FoldMemRefAliasOps.cpp
M mlir/lib/Dialect/MemRef/Utils/MemRefUtils.cpp
A mlir/test/Dialect/AMDGPU/amdgpu-fold-memrefs.mlir
M utils/bazel/llvm-project-overlay/mlir/BUILD.bazel
Log Message:
-----------
Reapply "[AMDGPU] fold `memref.subview/expand_shape/collapse_shape` into `amdgpu.gather_to_lds`" (#150334)
This is a reapply of patch #149851. The reapply also fixes a CMake/Bazel
build issue, which was the reason of the revert. (Thanks @rupprecht )
Original patch (#149851) message:
-----
This PR adds a new optimization pass to fold
`memref.subview/expand_shape/collapse_shape` ops into consumer
`amdgpu.gather_to_lds` operations.
* Implements a new pass `AmdgpuFoldMemRefOpsPass` with pattern
`FoldMemRefOpsIntoGatherToLDSOp`
* Adds corresponding folding tests
Commit: 675d7e19a73143cc624092c7ed12fd5f89416d47
https://github.com/llvm/llvm-project/commit/675d7e19a73143cc624092c7ed12fd5f89416d47
Author: Aiden Grossman <aidengrossman at google.com>
Date: 2025-07-24 (Thu, 24 Jul 2025)
Changed paths:
A .github/workflows/check-ci.yml
Log Message:
-----------
[CI][Github] Add Workflow to Run Python Tests in CI Folder (#148696)
This patch adds a new GHA workflow that runs pytest inside of the .ci
directory to test all of the CI infrastructure. This is to make it more
visible to new contributors that these tests exist and also to ensure
that they are passing before merge. There have been several instances
already where someone neglected to update these tests and we should have
automation to enforce this.
Commit: 690c3ee5be51bf0b6598b1a202ceb7dec6acebbd
https://github.com/llvm/llvm-project/commit/690c3ee5be51bf0b6598b1a202ceb7dec6acebbd
Author: Ross Brunton <ross at codeplay.com>
Date: 2025-07-24 (Thu, 24 Jul 2025)
Changed paths:
M offload/liboffload/API/Event.td
M offload/liboffload/API/Kernel.td
M offload/liboffload/API/Memory.td
M offload/liboffload/src/OffloadImpl.cpp
M offload/unittests/OffloadAPI/CMakeLists.txt
M offload/unittests/OffloadAPI/common/Fixtures.hpp
A offload/unittests/OffloadAPI/event/olCreateEvent.cpp
M offload/unittests/OffloadAPI/event/olDestroyEvent.cpp
M offload/unittests/OffloadAPI/event/olSyncEvent.cpp
M offload/unittests/OffloadAPI/kernel/olLaunchKernel.cpp
M offload/unittests/OffloadAPI/memory/olMemcpy.cpp
Log Message:
-----------
[Offload] Replace "EventOut" parameters with `olCreateEvent` (#150217)
Rather than having every "enqueue"-type function have an output pointer
specifically for an output event, just provide an `olCreateEvent`
entrypoint which pushes an event to the queue.
For example, replace:
```cpp
olMemcpy(Queue, ..., EventOut);
```
with
```cpp
olMemcpy(Queue, ...);
olCreateEvent(Queue, EventOut);
```
Commit: b5c879515350a2cfac3567839f471182333ab4be
https://github.com/llvm/llvm-project/commit/b5c879515350a2cfac3567839f471182333ab4be
Author: Aiden Grossman <aidengrossman at google.com>
Date: 2025-07-24 (Thu, 24 Jul 2025)
Changed paths:
M .ci/compute_projects.py
Log Message:
-----------
[CI] Refactor compute_projects to Introduce Meta Projects
This patch introduces the concept of meta projects into the
compute_projects script. Meta projects are projects like CIR and
GoogleTest where they do not have their own top level project. This
patch adds a little bit of extra code in exchange for making meta
projects a first level concept that can be configured almost entirely by
changing around the mappings at the top of the file. This patch also
refactors the project skipping functionality to use meta projects.
This (arguably) makes the CIR support a little bit cleaner and is
necessary for some future improvements like running all the tests on
Github workflow changes and running tests when third-party changes.
Reviewers: Endilll, andykaylor, lnihlen, gburgessiv, dschuff, Keenuts, cmtice
Reviewed By: andykaylor
Pull Request: https://github.com/llvm/llvm-project/pull/150249
Commit: 08e7c17c7aa923f057d3769457eaa267da37bb96
https://github.com/llvm/llvm-project/commit/08e7c17c7aa923f057d3769457eaa267da37bb96
Author: Aiden Grossman <aidengrossman at google.com>
Date: 2025-07-24 (Thu, 24 Jul 2025)
Changed paths:
M .ci/compute_projects.py
M .ci/compute_projects_test.py
Log Message:
-----------
[CI] Test All Projects On Workflow Changes
This patch makes it so that we actually run all the tests when we touch
the workflow file in .github/workflows/premerge.yaml. Before this we
would not run any tests and it was annoying to have to manually touch a
file to get something to trigger.
Reviewers: Keenuts, lnihlen, cmtice, dschuff, gburgessiv
Reviewed By: gburgessiv
Pull Request: https://github.com/llvm/llvm-project/pull/150250
Commit: 2149d6d1c9a1ad62761dc007ec6c6dedf6eb2fc0
https://github.com/llvm/llvm-project/commit/2149d6d1c9a1ad62761dc007ec6c6dedf6eb2fc0
Author: Aiden Grossman <aidengrossman at google.com>
Date: 2025-07-24 (Thu, 24 Jul 2025)
Changed paths:
M .ci/compute_projects.py
M .ci/compute_projects_test.py
Log Message:
-----------
[CI] Run All Tests When Changing third-party
This patch ensures that we run all the tests when someone touches
third-party. Some of the projects (like SipHash and Benchmark) do not
get used by every project and we could get away with testing less.
However, it takes quite a bit of effort to tease out what actually does
depend on which library, it is liable to becoming out of date, and it
adds complexity. Just testing all the projects is simple. Given the
commit frequency to third-party is pretty low (a couple commits per
month), we should have no capacity problems here.
Fixes #149154
Reviewers: dschuff, gburgessiv, Keenuts, lnihlen, dpaoliello, cmtice
Reviewed By: dpaoliello
Pull Request: https://github.com/llvm/llvm-project/pull/150251
Commit: 889faabe78d2cb182414430601d6da2ed6619be3
https://github.com/llvm/llvm-project/commit/889faabe78d2cb182414430601d6da2ed6619be3
Author: Julian Brown <julian.brown at amd.com>
Date: 2025-07-24 (Thu, 24 Jul 2025)
Changed paths:
M clang/lib/CodeGen/CGOpenMPRuntime.cpp
A clang/test/OpenMP/copy-gaps-1.cpp
A clang/test/OpenMP/copy-gaps-2.cpp
A clang/test/OpenMP/copy-gaps-3.cpp
A clang/test/OpenMP/copy-gaps-4.cpp
A clang/test/OpenMP/copy-gaps-5.cpp
A clang/test/OpenMP/copy-gaps-6.cpp
M clang/test/OpenMP/target_map_codegen_35.cpp
Log Message:
-----------
[OpenMP] Don't emit redundant zero-sized mapping nodes for overlapped structs (#148947)
The handling of overlapped structure mapping in CGOpenMPRuntime.cpp can
lead to redundant zero-sized mapping nodes at runtime. This patch fixes
it using a combination of approaches: trivially adjacent struct members
won't have a mapping node created between them, and for more complicated
cases (inheritance) the physical layout of the struct/class is used to
make sure that elements aren't missed.
I've introduced a new class to track the state whilst iterating over the
struct. This reduces a bit of redundancy in the code (accumulating
CombinedInfo both during and after the loop), which I think is a bit
neater.
Before:
omptarget --> Entry 0: Base=0x00007fff8d483830, Begin=0x00007fff8d483830, Size=48, Type=0x20, Name=unknown
omptarget --> Entry 1: Base=0x00007fff8d483830, Begin=0x00007fff8d483830, Size=0, Type=0x1000000000003, Name=unknown
omptarget --> Entry 2: Base=0x00007fff8d483830, Begin=0x00007fff8d483834, Size=0, Type=0x1000000000003, Name=unknown
omptarget --> Entry 3: Base=0x00007fff8d483830, Begin=0x00007fff8d483838, Size=0, Type=0x1000000000003, Name=unknown
omptarget --> Entry 4: Base=0x00007fff8d483830, Begin=0x00007fff8d48383c, Size=20, Type=0x1000000000003, Name=unknown
omptarget --> Entry 5: Base=0x00007fff8d483830, Begin=0x00007fff8d483854, Size=0, Type=0x1000000000003, Name=unknown
omptarget --> Entry 6: Base=0x00007fff8d483830, Begin=0x00007fff8d483858, Size=0, Type=0x1000000000003, Name=unknown
omptarget --> Entry 7: Base=0x00007fff8d483830, Begin=0x00007fff8d48385c, Size=4, Type=0x1000000000003, Name=unknown
omptarget --> Entry 8: Base=0x00007fff8d483830, Begin=0x00007fff8d483830, Size=4, Type=0x1000000000003, Name=unknown
omptarget --> Entry 9: Base=0x00007fff8d483830, Begin=0x00007fff8d483834, Size=4, Type=0x1000000000003, Name=unknown
omptarget --> Entry 10: Base=0x00007fff8d483830, Begin=0x00007fff8d483838, Size=4, Type=0x1000000000003, Name=unknown
omptarget --> Entry 11: Base=0x00007fff8d483840, Begin=0x00005e7665275130, Size=32, Type=0x1000000000013, Name=unknown
omptarget --> Entry 12: Base=0x00007fff8d483830, Begin=0x00007fff8d483850, Size=4, Type=0x1000000000003, Name=unknown
omptarget --> Entry 13: Base=0x00007fff8d483830, Begin=0x00007fff8d483854, Size=4, Type=0x1000000000003, Name=unknown
omptarget --> Entry 14: Base=0x00007fff8d483830, Begin=0x00007fff8d483858, Size=4, Type=0x1000000000003, Name=unknown
After:
omptarget --> Entry 0: Base=0x00007fffd0f562e0, Begin=0x00007fffd0f562e0, Size=48, Type=0x20, Name=unknown
omptarget --> Entry 1: Base=0x00007fffd0f562e0, Begin=0x00007fffd0f562ec, Size=20, Type=0x1000000000003, Name=unknown
omptarget --> Entry 2: Base=0x00007fffd0f562e0, Begin=0x00007fffd0f5630c, Size=4, Type=0x1000000000003, Name=unknown
omptarget --> Entry 3: Base=0x00007fffd0f562e0, Begin=0x00007fffd0f562e0, Size=4, Type=0x1000000000003, Name=unknown
omptarget --> Entry 4: Base=0x00007fffd0f562e0, Begin=0x00007fffd0f562e4, Size=4, Type=0x1000000000003, Name=unknown
omptarget --> Entry 5: Base=0x00007fffd0f562e0, Begin=0x00007fffd0f562e8, Size=4, Type=0x1000000000003, Name=unknown
omptarget --> Entry 6: Base=0x00007fffd0f562f0, Begin=0x000058b6013fb130, Size=32, Type=0x1000000000013, Name=unknown
omptarget --> Entry 7: Base=0x00007fffd0f562e0, Begin=0x00007fffd0f56300, Size=4, Type=0x1000000000003, Name=unknown
omptarget --> Entry 8: Base=0x00007fffd0f562e0, Begin=0x00007fffd0f56304, Size=4, Type=0x1000000000003, Name=unknown
omptarget --> Entry 9: Base=0x00007fffd0f562e0, Begin=0x00007fffd0f56308, Size=4, Type=0x1000000000003, Name=unknown
For code:
#include <cstdlib>
#include <cstdio>
struct S {
int x;
int y;
int z;
int *p1;
int *p2;
};
struct T : public S {
int a;
int b;
int c;
};
int main() {
T v;
v.p1 = (int*) calloc(8, sizeof(int));
v.p2 = (int*) calloc(8, sizeof(int));
#pragma omp target map(tofrom: v, v.x, v.y, v.z, v.p1[:8], v.a, v.b, v.c)
{
v.x++;
v.y += 2;
v.z += 3;
v.p1[0] += 4;
v.a += 7;
v.b += 5;
v.c += 6;
}
return 0;
}
Commit: 3feb6f971577701713034d3404b6737fe6462d43
https://github.com/llvm/llvm-project/commit/3feb6f971577701713034d3404b6737fe6462d43
Author: Jacques Pienaar <jpienaar at google.com>
Date: 2025-07-24 (Thu, 24 Jul 2025)
Changed paths:
M clang-tools-extra/clang-tidy/llvm/CMakeLists.txt
M clang-tools-extra/clang-tidy/llvm/LLVMTidyModule.cpp
A clang-tools-extra/clang-tidy/llvm/UseNewMLIROpBuilderCheck.cpp
A clang-tools-extra/clang-tidy/llvm/UseNewMLIROpBuilderCheck.h
M clang-tools-extra/docs/ReleaseNotes.rst
M clang-tools-extra/docs/clang-tidy/checks/list.rst
A clang-tools-extra/docs/clang-tidy/checks/llvm/use-new-mlir-op-builder.rst
A clang-tools-extra/test/clang-tidy/checkers/llvm/use-new-mlir-op-builder.cpp
Log Message:
-----------
[clang-tidy] Add MLIR check for old op builder usage. (#149148)
Upstream is moving towards new create method invocation, add check to flag old
usage that will be deprecated.
---------
Co-authored-by: Baranov Victor <bar.victor.2002 at gmail.com>
Co-authored-by: EugeneZelenko <eugene.zelenko at gmail.com>
Commit: 38f82534bbe9e1c9f5edd975a72e07beb7048423
https://github.com/llvm/llvm-project/commit/38f82534bbe9e1c9f5edd975a72e07beb7048423
Author: James Y Knight <jyknight at google.com>
Date: 2025-07-24 (Thu, 24 Jul 2025)
Changed paths:
M clang/include/clang/Basic/Specifiers.h
M llvm/include/llvm/ADT/DenseMapInfo.h
Log Message:
-----------
Reject out-of-bounds enum sentinels in DenseMap/DenseSet. (#150308)
This makes the bug in PR #125556 which was fixed by
dc87a14efb381d960c8fbf988221f31216d7f5fd into a compile-time error.
...and fix a newly-discovered instance of this issue, triggered by a
`llvm::MapVector<AccessSpecifier, ...>` in
clang-tools-extra/clangd/refactor/tweaks/OverridePureVirtuals.cpp.
Commit: 3003e4e8616015cd247ccbede67598ac544825da
https://github.com/llvm/llvm-project/commit/3003e4e8616015cd247ccbede67598ac544825da
Author: Dan Gohman <dev at sunfishcode.online>
Date: 2025-07-24 (Thu, 24 Jul 2025)
Changed paths:
M llvm/Maintainers.md
Log Message:
-----------
Fix formatting in llvm/Maintainers.md. (#147545)
Add a backslash to fix the formatting in llvm/Maintainers.md.
Commit: 1ba3859cdbf263182502b1c00546e985bdb633da
https://github.com/llvm/llvm-project/commit/1ba3859cdbf263182502b1c00546e985bdb633da
Author: Krzysztof Parzyszek <Krzysztof.Parzyszek at amd.com>
Date: 2025-07-24 (Thu, 24 Jul 2025)
Changed paths:
M flang/include/flang/Parser/parse-tree.h
M flang/lib/Lower/OpenMP/OpenMP.cpp
M flang/lib/Parser/openmp-parsers.cpp
M flang/lib/Parser/unparse.cpp
M flang/lib/Semantics/check-omp-structure.cpp
A flang/test/Parser/OpenMP/block-construct.f90
A flang/test/Parser/OpenMP/construct-prefix-conflict.f90
Log Message:
-----------
[flang][OpenMP] Parse strictly- and loosely-structured blocks (#150298)
Block-associated constructs have, as their body, either a strictly- or a
loosely-structured block. In the former case the end-directive is
optional.
The existing parser required the end-directive to be present in all
cases.
Note:
The definitions of these blocks in the OpenMP spec exclude cases where
the block contains more than one construct, and the first one is
BLOCK/ENDBLOCK. For example, the following is invalid:
```
!$omp target
block ! This cannot be a strictly-structured block, but
continue ! a loosely-structured block cannot start with
endblock ! BLOCK/ENDBLOCK
continue !
!$omp end target
```
Commit: 3d5b18af1752ad4b859de6bdba4b25ef040a3dce
https://github.com/llvm/llvm-project/commit/3d5b18af1752ad4b859de6bdba4b25ef040a3dce
Author: Jacques Pienaar <jpienaar at google.com>
Date: 2025-07-24 (Thu, 24 Jul 2025)
Changed paths:
M clang-tools-extra/docs/clang-tidy/checks/llvm/use-new-mlir-op-builder.rst
Log Message:
-----------
[clang-tidy] Fix typo in doc (#150424)
Commit: 61110e0f62ddf9bacb42975fa0a4cdef1a83746b
https://github.com/llvm/llvm-project/commit/61110e0f62ddf9bacb42975fa0a4cdef1a83746b
Author: Luke Lau <luke at igalia.com>
Date: 2025-07-24 (Thu, 24 Jul 2025)
Changed paths:
M llvm/include/llvm/CodeGen/BasicTTIImpl.h
M llvm/test/Analysis/CostModel/AArch64/sve-intrinsics.ll
M llvm/test/Analysis/CostModel/RISCV/rvv-shuffle.ll
M llvm/test/Analysis/CostModel/RISCV/vp-intrinsics.ll
Log Message:
-----------
[TTI] Share value and type based llvm.vector.reverse cost (#150415)
We currently provide a generic cost for llvm.vector.reverse in BasicTTI
by reusing the reverse shuffle cost, but only for the value based cost.
Since the argument values aren't actually used, move this into the type
based costing method so that type based costing can also reuse it.
Commit: 0c4d56a6747b0f9677b47cba82053ac92ba67962
https://github.com/llvm/llvm-project/commit/0c4d56a6747b0f9677b47cba82053ac92ba67962
Author: parabola94 <heavybaby5000 at toki.waseda.jp>
Date: 2025-07-24 (Thu, 24 Jul 2025)
Changed paths:
M clang/include/clang/Driver/Driver.h
M clang/lib/Driver/Driver.cpp
M clang/lib/Driver/ToolChain.cpp
M clang/lib/Driver/ToolChains/MSVC.cpp
M clang/lib/Driver/ToolChains/MinGW.cpp
M clang/lib/Driver/ToolChains/Solaris.cpp
M clang/lib/Driver/ToolChains/UEFI.cpp
Log Message:
-----------
[clang][Driver] Add a new member for CLANG_DEFAULT_LINKER to clang::driver::Driver (NFC) (#149784)
The default linker can be changed by a CMake variable
CLANG_DEFAULT_LINKER, but it is shared in all toolchains. This patch
intends to resolve this.
Commit: deede2b2db262a932f07a386e59c2ca0b1a798d1
https://github.com/llvm/llvm-project/commit/deede2b2db262a932f07a386e59c2ca0b1a798d1
Author: Donát Nagy <donat.nagy at ericsson.com>
Date: 2025-07-24 (Thu, 24 Jul 2025)
Changed paths:
M clang/lib/StaticAnalyzer/Checkers/MallocChecker.cpp
M clang/test/Analysis/malloc.c
Log Message:
-----------
[analyzer] Eliminate unique release point assertion (#150240)
MallocChecker.cpp has a complex heuristic that supresses reports where
the memory release happens during the release of a reference-counted
object (to suppress a significant amount of false positives).
Previously this logic asserted that there is at most one release point
corresponding to a symbol, but it turns out that there is a rare corner
case where the symbol can be released, forgotten and then released
again. This commit removes that assertion to avoid the crash. (As this
issue just affects a bug suppression heuristic, I didn't want to dig
deeper and modify the way the state of the symbol is changed.)
Fixes #149754
Commit: 74505806b6446d1868c1e07cbaebfaa29291beb5
https://github.com/llvm/llvm-project/commit/74505806b6446d1868c1e07cbaebfaa29291beb5
Author: Aiden Grossman <aidengrossman at google.com>
Date: 2025-07-24 (Thu, 24 Jul 2025)
Changed paths:
M .github/workflows/containers/github-action-ci-windows/Dockerfile
M .github/workflows/containers/github-action-ci/Dockerfile
Log Message:
-----------
[CI][Github] Bump runner version in CI containers
v2.327.0 is the latest version. Bump the version in the containers to
keep them up to date.
Commit: 628cfe0e0a491a61ab8e85c371eb73e67d693712
https://github.com/llvm/llvm-project/commit/628cfe0e0a491a61ab8e85c371eb73e67d693712
Author: Julian Brown <julian.brown at amd.com>
Date: 2025-07-24 (Thu, 24 Jul 2025)
Changed paths:
M clang/lib/CodeGen/CGOpenMPRuntime.cpp
Log Message:
-----------
[OpenMP] Fix initialization order for CopyOverlappedEntryGaps (#150431)
NFC.
Commit: 34986003d14704c5e4926859249995d9628f89d8
https://github.com/llvm/llvm-project/commit/34986003d14704c5e4926859249995d9628f89d8
Author: AZero13 <gfunni234 at gmail.com>
Date: 2025-07-24 (Thu, 24 Jul 2025)
Changed paths:
M llvm/lib/Target/AArch64/AArch64InstrInfo.cpp
Log Message:
-----------
[AArch64] Predicate should be NE for CBNZW (#150287)
Unable to reproduce yet, but this definitely seems wrong. Better safe
than sorry.
No effect on codegen as far as I know (because I have not been able to
repro).
Commit: f45e6a2834b4e7a9128b93702821a4ae944ed57b
https://github.com/llvm/llvm-project/commit/f45e6a2834b4e7a9128b93702821a4ae944ed57b
Author: Nathan Gauër <brioche at google.com>
Date: 2025-07-24 (Thu, 24 Jul 2025)
Changed paths:
M llvm/lib/Target/SPIRV/SPIRVEmitIntrinsics.cpp
A llvm/test/CodeGen/SPIRV/pointers/resource-vector-load-store.ll
Log Message:
-----------
[SPIR-V] Fix emit intrinsic for resource type (#150224)
This is a quick fix to make progress to the backend until we get a
proper type scavenging system.
The previous code was only checking the type if the resource was used
once. Slightly changed the code to look to all usages, and get the first
type.
This will certainly break in other cases, but it allows us to move
forward for now until we rewrite the type scavenging to handle untyped
GEP/ptradd correctly.
Related to #145002
Commit: c2c881fcc85e0c2d7a050b0199d4dadf8f556b9e
https://github.com/llvm/llvm-project/commit/c2c881fcc85e0c2d7a050b0199d4dadf8f556b9e
Author: Longsheng Mou <longshengmou at gmail.com>
Date: 2025-07-24 (Thu, 24 Jul 2025)
Changed paths:
M mlir/lib/Dialect/Tosa/IR/TosaCanonicalizations.cpp
M mlir/test/Dialect/Tosa/canonicalize.mlir
Log Message:
-----------
[mlir][tosa] Fix integer-to-boolean cast folder (#150370)
According to the TOSA spec, casting to boolean should produce true if
the input is non-zero, and false otherwise — i.e., `out = (in != 0) ?
true : false`. Previous behavior incorrectly relied on truncation, which
could yield incorrect results for non-zero values whose least
significant bit is zero. Fixes #150302.
Commit: d82d502ae5cec8bb43092869fd4fa9b9e74a3e61
https://github.com/llvm/llvm-project/commit/d82d502ae5cec8bb43092869fd4fa9b9e74a3e61
Author: Jordan Rupprecht <rupprecht at google.com>
Date: 2025-07-24 (Thu, 24 Jul 2025)
Changed paths:
M utils/bazel/llvm-project-overlay/clang-tools-extra/clang-tidy/BUILD.bazel
Log Message:
-----------
[bazel] Port #149148 (#150435)
Commit: 8f8b436c2b914a8abcee12b8a3bf45aec9fa627e
https://github.com/llvm/llvm-project/commit/8f8b436c2b914a8abcee12b8a3bf45aec9fa627e
Author: Krzysztof Parzyszek <Krzysztof.Parzyszek at amd.com>
Date: 2025-07-24 (Thu, 24 Jul 2025)
Changed paths:
M flang/lib/Parser/openmp-parsers.cpp
Log Message:
-----------
[flang][OpenMP] Silence warning in openmp-parsers.cpp
flang/lib/Parser/openmp-parsers.cpp:1655:43: warning
: logical not is only applied to the left hand side of comparison [-Wlogical-not
-parentheses]
1655 | TYPE_PARSER(!StandaloneDirectiveLookahead >=
| ^~
Commit: 3ebe5d661f7829b2ffe1b422ec7d00d3213c9730
https://github.com/llvm/llvm-project/commit/3ebe5d661f7829b2ffe1b422ec7d00d3213c9730
Author: Ian Wood <ianwood2024 at u.northwestern.edu>
Date: 2025-07-24 (Thu, 24 Jul 2025)
Changed paths:
M mlir/include/mlir/Dialect/Linalg/Transforms/Transforms.h
M mlir/lib/Dialect/Linalg/Transforms/DropUnitDims.cpp
Log Message:
-----------
[mlir][linalg] Drop unit dims on IndexingMapOpInterface (#150280)
Generalizes `dropUnitDims` to operate on any op implementing the
`IndexingMapOpInterface`. Operation specific creation is handled by
passing a builder that will construct the new operation based on the
dropped dimensions.
---------
Signed-off-by: Ian Wood <ianwood at u.northwestern.edu>
Co-authored-by: Kunwar Grover <groverkss at gmail.com>
Commit: 3bd34ec924dbba1bde3856fdc31748200ccfd53f
https://github.com/llvm/llvm-project/commit/3bd34ec924dbba1bde3856fdc31748200ccfd53f
Author: erichkeane <ekeane at nvidia.com>
Date: 2025-07-24 (Thu, 24 Jul 2025)
Changed paths:
M clang/include/clang/Basic/DiagnosticSemaKinds.td
M clang/lib/Sema/SemaOpenACCAtomic.cpp
M clang/test/SemaOpenACC/atomic-construct.cpp
Log Message:
-----------
[OpenACC] Fix checking of sub-expressions in cache
Running an external test suite (UDel) showed that our expression
comparison for the 'cache' rule checking was overly strict in the
presence of irrelevant parens/casts/etc. This patch ensures we skip
them when checking.
This also changes the diagnostic to say 'sub-expression' instead of
variable, which is more correct.
Commit: 862b9ea805511774a00348bc4477b09aa78ca711
https://github.com/llvm/llvm-project/commit/862b9ea805511774a00348bc4477b09aa78ca711
Author: Juan Manuel Martinez Caamaño <jmartinezcaamao at gmail.com>
Date: 2025-07-24 (Thu, 24 Jul 2025)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPUAttributor.cpp
M llvm/test/CodeGen/AMDGPU/amdgpu-attributor-accesslist-offsetbins-out-of-sync.ll
M llvm/test/CodeGen/AMDGPU/direct-indirect-call.ll
M llvm/test/CodeGen/AMDGPU/duplicate-attribute-indirect.ll
M llvm/test/CodeGen/AMDGPU/simple-indirect-call-2.ll
M llvm/test/CodeGen/AMDGPU/simple-indirect-call.ll
Log Message:
-----------
[AMDGPU] Remove AAInstanceInfo from the AMDGPUAttributor (#150232)
Related to compile-time issue SWDEV-543240 and functional issue
SWDEV-544256
Commit: 3e9d369c5c8ebc8c1568a288672236195b2e3685
https://github.com/llvm/llvm-project/commit/3e9d369c5c8ebc8c1568a288672236195b2e3685
Author: Morris Hafner <mmha at users.noreply.github.com>
Date: 2025-07-24 (Thu, 24 Jul 2025)
Changed paths:
M clang/include/clang/CIR/Dialect/Builder/CIRBaseBuilder.h
M clang/include/clang/CIR/Dialect/IR/CIROps.td
M clang/include/clang/CIR/Dialect/IR/CIRTypeConstraints.td
M clang/include/clang/CIR/Dialect/Passes.h
M clang/include/clang/CIR/MissingFeatures.h
M clang/lib/CIR/CodeGen/CIRGenClass.cpp
M clang/lib/CIR/CodeGen/CIRGenExpr.cpp
M clang/lib/CIR/CodeGen/CIRGenFunction.cpp
M clang/lib/CIR/CodeGen/CIRGenFunction.h
M clang/lib/CIR/Dialect/Transforms/LoweringPrepare.cpp
M clang/lib/CIR/Lowering/CIRPasses.cpp
A clang/test/CIR/CodeGen/array-ctor.cpp
A clang/test/CIR/IR/array-ctor.cir
Log Message:
-----------
[CIR] Add support for array constructors (#149142)
This patch upstreams support for creating arrays of classes that require
calling a constructor.
* Adds the ArrayCtor operation
* New lowering pass for lowering ArrayCtor to a loop
---------
Co-authored-by: Andy Kaylor <akaylor at nvidia.com>
Co-authored-by: Henrich Lauko <xlauko at mail.muni.cz>
Commit: f79efa986d61700d3fcfd22390bc1aa17d0d454c
https://github.com/llvm/llvm-project/commit/f79efa986d61700d3fcfd22390bc1aa17d0d454c
Author: Jordan Rupprecht <rupprecht at google.com>
Date: 2025-07-24 (Thu, 24 Jul 2025)
Changed paths:
M lld/test/ELF/aarch64-build-attributes-malformed.s
Log Message:
-----------
[lld][test] Fix unintentional write to a non-writeable dir (#150436)
The test added in #147970 fails trying to write `a.out` when run in a
non-writeable directory. I believe the intent was to write to /dev/null
as the output, but `-o` was omitted, so it's actually linking *in*
/dev/null and writing to `a.out`.
Commit: 97c953406d68357dddb8b624cd32c8e435a9fcfb
https://github.com/llvm/llvm-project/commit/97c953406d68357dddb8b624cd32c8e435a9fcfb
Author: Owen Pan <owenpiano at gmail.com>
Date: 2025-07-24 (Thu, 24 Jul 2025)
Changed paths:
M clang/docs/ClangFormatStyleOptions.rst
M clang/include/clang/Format/Format.h
M clang/lib/Format/Format.cpp
M clang/lib/Format/TokenAnnotator.cpp
M clang/unittests/Format/ConfigParseTest.cpp
M clang/unittests/Format/FormatTest.cpp
Log Message:
-----------
[clang-format] Add AfterNot to SpaceBeforeParensOptions (#150367)
Closes #149971
Commit: 29b9bdf81eba6d0445b0fb84ed42e289cd0940eb
https://github.com/llvm/llvm-project/commit/29b9bdf81eba6d0445b0fb84ed42e289cd0940eb
Author: Kazu Hirata <kazu at google.com>
Date: 2025-07-24 (Thu, 24 Jul 2025)
Changed paths:
M lldb/tools/lldb-rpc-gen/RPCCommon.cpp
M lldb/tools/lldb-rpc-gen/RPCCommon.h
Log Message:
-----------
[lldb] Remove HasCallbackParameter (#150366)
Commit: a4d4859dc70c046ad928805ddeaf8fa101793394
https://github.com/llvm/llvm-project/commit/a4d4859dc70c046ad928805ddeaf8fa101793394
Author: Owen Pan <owenpiano at gmail.com>
Date: 2025-07-24 (Thu, 24 Jul 2025)
Changed paths:
M clang/lib/Format/Format.cpp
M clang/unittests/Format/FormatTest.cpp
Log Message:
-----------
[clang-format] Fix a bug in `DerivePointerAlignment: true` (#150387)
Fixes #150327
Commit: 473bc0d188bfb53b16b8ce1f74629d3763d637e0
https://github.com/llvm/llvm-project/commit/473bc0d188bfb53b16b8ce1f74629d3763d637e0
Author: Changpeng Fang <changpeng.fang at amd.com>
Date: 2025-07-24 (Thu, 24 Jul 2025)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPU.td
M llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp
M llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.h
M llvm/lib/Target/AMDGPU/GCNSubtarget.h
M llvm/lib/Target/AMDGPU/SIISelLowering.cpp
M llvm/lib/Target/AMDGPU/SIInstrInfo.td
M llvm/lib/Target/AMDGPU/VOP3PInstructions.td
A llvm/test/CodeGen/AMDGPU/mad-mix-bf16.ll
A llvm/test/CodeGen/AMDGPU/mad-mix-hi-bf16.ll
A llvm/test/CodeGen/AMDGPU/mad-mix-lo-bf16.ll
M llvm/test/MC/AMDGPU/gfx1250_asm_vop3p.s
M llvm/test/MC/Disassembler/AMDGPU/gfx1250_dasm_vop3p.txt
Log Message:
-----------
[AMDGPU] Support V_FMA_MIX*_BF16 instructions on gfx1250 (#150381)
Co-authored-by: Stanislav Mekhanoshin <Stanislav.Mekhanoshin at amd.com>
Commit: f44346dc1f6252716cfc62bb0687e3932a93089f
https://github.com/llvm/llvm-project/commit/f44346dc1f6252716cfc62bb0687e3932a93089f
Author: Anchu Rajendran S <asudhaku at amd.com>
Date: 2025-07-24 (Thu, 24 Jul 2025)
Changed paths:
M clang/include/clang/Driver/Options.td
M flang/include/flang/Frontend/TargetOptions.h
M flang/include/flang/Optimizer/Dialect/Support/FIRContext.h
M flang/lib/Frontend/CompilerInvocation.cpp
M flang/lib/Lower/Bridge.cpp
M flang/lib/Lower/OpenMP/Atomic.cpp
M flang/lib/Optimizer/Dialect/Support/FIRContext.cpp
A flang/test/Lower/OpenMP/atomic-control-options.f90
M mlir/include/mlir/Dialect/OpenMP/OpenMPAttrDefs.td
M mlir/include/mlir/Dialect/OpenMP/OpenMPOps.td
M mlir/test/Dialect/OpenMP/ops.mlir
Log Message:
-----------
[flang][flang-driver][mlir][OpenMP] atomic control support (#143441)
Atomic Control Options are used to specify architectural characteristics
to help lowering of atomic operations. The options used are:
`-f[no-]atomic-remote-memory`, `-f[no-]atomic-fine-grained-memory`,
`-f[no-]atomic-ignore-denormal-mode`.
Legacy option `-m[no-]unsafe-fp-atomics` is aliased to
`-f[no-]ignore-denormal-mode`.
More details can be found in
https://github.com/llvm/llvm-project/pull/102569. This PR implements the
frontend support for these options with OpenMP atomic in flang.
Backend changes are available in the draft PR:
https://github.com/llvm/llvm-project/pull/143769 which will be raised
after this merged.
Commit: 36a19c5bfe2f808365b8ccdacd4c6f2bb25fc3ef
https://github.com/llvm/llvm-project/commit/36a19c5bfe2f808365b8ccdacd4c6f2bb25fc3ef
Author: gulfemsavrun <gulfem at google.com>
Date: 2025-07-24 (Thu, 24 Jul 2025)
Changed paths:
M clang/cmake/caches/Fuchsia.cmake
Log Message:
-----------
[Fuchsia] Add BOOTSTRAP_BOOTSTRAP flags for PGO (#150448)
Commit: c9a8e15494c84730a2a8c0713281b3c8aa5b67c4
https://github.com/llvm/llvm-project/commit/c9a8e15494c84730a2a8c0713281b3c8aa5b67c4
Author: xur-llvm <59886942+xur-llvm at users.noreply.github.com>
Date: 2025-07-24 (Thu, 24 Jul 2025)
Changed paths:
M llvm/lib/Analysis/ProfileSummaryInfo.cpp
M llvm/lib/Transforms/Instrumentation/IndirectCallPromotion.cpp
M llvm/test/ThinLTO/X86/memprof-icp.ll
M llvm/test/Transforms/PGOProfile/icp_mismatch_msg.ll
A llvm/test/Transforms/PGOProfile/indirect_call_promotion2.ll
Log Message:
-----------
[ICP] Add a few tunings to indirect-call-promotion (#149892)
[ICP] Add a few tunings to indirect-call-promtion
Indirect-call promotion (ICP) has been adjusted with the following
tunings:
(1) Candidate functions can be now ICP'd even if only a declaration is
present.
(2) All non-cold candidate functions are now considered by ICP.
Previously, only hot targets were considered.
(3) If one target cannot be ICP'd, proceed with the remaining targets
instead of exiting the callsite.
This update hides all tunings under internal options and disables them
by default. They'll be enabled in a later update. There'll also be
another update to address the "not found" issue with indirect targets.
Commit: 42a081ec516bd4990059aec00d8065fd2bc9f15b
https://github.com/llvm/llvm-project/commit/42a081ec516bd4990059aec00d8065fd2bc9f15b
Author: Daniel Garvey <34486624+dan-garvey at users.noreply.github.com>
Date: 2025-07-24 (Thu, 24 Jul 2025)
Changed paths:
M mlir/lib/Transforms/Utils/GreedyPatternRewriteDriver.cpp
Log Message:
-----------
[mlir] Fix missing import (#150330)
building this file would fail when
MLIR_ENABLE_EXPENSIVE_PATTERN_API_CHECKS = 1
Signed-off-by: dan <danimal197 at gmail.com>
Commit: a23b8dcb293d7c90f80a44c0dfdecf930c0f1c73
https://github.com/llvm/llvm-project/commit/a23b8dcb293d7c90f80a44c0dfdecf930c0f1c73
Author: Han-Chung Wang <hanhan0912 at gmail.com>
Date: 2025-07-24 (Thu, 24 Jul 2025)
Changed paths:
M .ci/compute_projects.py
M .ci/compute_projects_test.py
M .ci/metrics/metrics.py
A .github/workflows/check-ci.yml
M .github/workflows/containers/github-action-ci-windows/Dockerfile
M .github/workflows/containers/github-action-ci/Dockerfile
M .github/workflows/premerge.yaml
M clang-tools-extra/clang-doc/BitcodeReader.cpp
M clang-tools-extra/clang-doc/BitcodeWriter.cpp
M clang-tools-extra/clang-doc/BitcodeWriter.h
M clang-tools-extra/clang-doc/HTMLMustacheGenerator.cpp
M clang-tools-extra/clang-doc/JSONGenerator.cpp
M clang-tools-extra/clang-doc/Representation.cpp
M clang-tools-extra/clang-doc/Representation.h
M clang-tools-extra/clang-doc/Serialize.cpp
M clang-tools-extra/clang-doc/assets/class-template.mustache
M clang-tools-extra/clang-doc/assets/enum-template.mustache
M clang-tools-extra/clang-doc/assets/function-template.mustache
M clang-tools-extra/clang-doc/assets/namespace-template.mustache
M clang-tools-extra/clang-tidy/bugprone/SignedCharMisuseCheck.cpp
M clang-tools-extra/clang-tidy/bugprone/UnhandledSelfAssignmentCheck.cpp
M clang-tools-extra/clang-tidy/llvm/CMakeLists.txt
M clang-tools-extra/clang-tidy/llvm/LLVMTidyModule.cpp
A clang-tools-extra/clang-tidy/llvm/UseNewMLIROpBuilderCheck.cpp
A clang-tools-extra/clang-tidy/llvm/UseNewMLIROpBuilderCheck.h
M clang-tools-extra/clang-tidy/misc/HeaderIncludeCycleCheck.cpp
M clang-tools-extra/clang-tidy/portability/TemplateVirtualMemberFunctionCheck.cpp
M clang-tools-extra/clangd/refactor/tweaks/CMakeLists.txt
R clang-tools-extra/clangd/refactor/tweaks/OverridePureVirtuals.cpp
M clang-tools-extra/clangd/unittests/CMakeLists.txt
R clang-tools-extra/clangd/unittests/tweaks/OverridePureVirtualsTests.cpp
M clang-tools-extra/docs/ReleaseNotes.rst
M clang-tools-extra/docs/clang-tidy/checks/list.rst
A clang-tools-extra/docs/clang-tidy/checks/llvm/use-new-mlir-op-builder.rst
M clang-tools-extra/test/clang-doc/basic-project.mustache.test
M clang-tools-extra/test/clang-doc/json/class-requires.cpp
M clang-tools-extra/test/clang-doc/json/class-template.cpp
M clang-tools-extra/test/clang-doc/json/class.cpp
M clang-tools-extra/test/clang-doc/json/compound-constraints.cpp
M clang-tools-extra/test/clang-doc/json/concept.cpp
M clang-tools-extra/test/clang-doc/json/function-requires.cpp
M clang-tools-extra/test/clang-doc/json/method-template.cpp
M clang-tools-extra/test/clang-doc/json/namespace.cpp
M clang-tools-extra/test/clang-doc/json/nested-namespace.cpp
M clang-tools-extra/test/clang-doc/mustache-index.cpp
M clang-tools-extra/test/clang-doc/mustache-separate-namespace.cpp
A clang-tools-extra/test/clang-tidy/checkers/bugprone/signed-char-misuse-c23.c
M clang-tools-extra/test/clang-tidy/checkers/bugprone/unhandled-self-assignment.cpp
A clang-tools-extra/test/clang-tidy/checkers/llvm/use-new-mlir-op-builder.cpp
M clang-tools-extra/test/clang-tidy/checkers/portability/template-virtual-member-function.cpp
M clang-tools-extra/unittests/clang-doc/HTMLMustacheGeneratorTest.cpp
M clang-tools-extra/unittests/clang-doc/JSONGeneratorTest.cpp
M clang/cmake/caches/Fuchsia.cmake
M clang/docs/ClangFormatStyleOptions.rst
M clang/docs/HIPSupport.rst
M clang/docs/LanguageExtensions.rst
M clang/docs/OpenMPSupport.rst
M clang/docs/ReleaseNotes.rst
M clang/docs/analyzer/checkers.rst
M clang/include/clang/Analysis/Analyses/LifetimeSafety.h
M clang/include/clang/Basic/Builtins.td
M clang/include/clang/Basic/CodeGenOptions.def
M clang/include/clang/Basic/DiagnosticParseKinds.td
M clang/include/clang/Basic/DiagnosticSemaKinds.td
M clang/include/clang/Basic/Specifiers.h
M clang/include/clang/Basic/TargetInfo.h
M clang/include/clang/Basic/arm_neon.td
M clang/include/clang/CIR/Dialect/Builder/CIRBaseBuilder.h
M clang/include/clang/CIR/Dialect/IR/CIROps.td
M clang/include/clang/CIR/Dialect/IR/CIRTypeConstraints.td
M clang/include/clang/CIR/Dialect/Passes.h
M clang/include/clang/CIR/MissingFeatures.h
M clang/include/clang/Driver/Driver.h
M clang/include/clang/Driver/Options.td
M clang/include/clang/Driver/ToolChain.h
M clang/include/clang/Format/Format.h
M clang/include/clang/StaticAnalyzer/Checkers/Checkers.td
M clang/lib/AST/ByteCode/Compiler.cpp
M clang/lib/AST/ByteCode/Compiler.h
M clang/lib/AST/ByteCode/Interp.h
M clang/lib/AST/ByteCode/Opcodes.td
M clang/lib/Analysis/LifetimeSafety.cpp
M clang/lib/Basic/TargetInfo.cpp
M clang/lib/Basic/Targets.cpp
M clang/lib/Basic/Targets/AArch64.cpp
M clang/lib/Basic/Targets/AArch64.h
M clang/lib/Basic/Targets/OSTargets.h
M clang/lib/Basic/Targets/RISCV.cpp
M clang/lib/Basic/Targets/RISCV.h
M clang/lib/Basic/Targets/X86.cpp
M clang/lib/Basic/Targets/X86.h
M clang/lib/CIR/CodeGen/CIRGenClass.cpp
M clang/lib/CIR/CodeGen/CIRGenExpr.cpp
M clang/lib/CIR/CodeGen/CIRGenExprComplex.cpp
M clang/lib/CIR/CodeGen/CIRGenExprScalar.cpp
M clang/lib/CIR/CodeGen/CIRGenFunction.cpp
M clang/lib/CIR/CodeGen/CIRGenFunction.h
M clang/lib/CIR/Dialect/IR/CIRDialect.cpp
M clang/lib/CIR/Dialect/Transforms/LoweringPrepare.cpp
M clang/lib/CIR/Lowering/CIRPasses.cpp
M clang/lib/CodeGen/ABIInfo.cpp
M clang/lib/CodeGen/CGBuiltin.cpp
M clang/lib/CodeGen/CGOpenMPRuntime.cpp
M clang/lib/CodeGen/CodeGenModule.cpp
M clang/lib/CodeGen/TargetBuiltins/AMDGPU.cpp
M clang/lib/CodeGen/TargetBuiltins/ARM.cpp
M clang/lib/Driver/Driver.cpp
M clang/lib/Driver/ToolChain.cpp
M clang/lib/Driver/ToolChains/AMDGPU.cpp
M clang/lib/Driver/ToolChains/AMDGPU.h
M clang/lib/Driver/ToolChains/AMDGPUOpenMP.cpp
M clang/lib/Driver/ToolChains/AMDGPUOpenMP.h
M clang/lib/Driver/ToolChains/Arch/Sparc.cpp
M clang/lib/Driver/ToolChains/HIPAMD.cpp
M clang/lib/Driver/ToolChains/HIPAMD.h
M clang/lib/Driver/ToolChains/HIPSPV.cpp
M clang/lib/Driver/ToolChains/HIPSPV.h
M clang/lib/Driver/ToolChains/MSVC.cpp
M clang/lib/Driver/ToolChains/MinGW.cpp
M clang/lib/Driver/ToolChains/OpenBSD.cpp
M clang/lib/Driver/ToolChains/ROCm.h
M clang/lib/Driver/ToolChains/Solaris.cpp
M clang/lib/Driver/ToolChains/UEFI.cpp
M clang/lib/Format/ContinuationIndenter.cpp
M clang/lib/Format/Format.cpp
M clang/lib/Format/TokenAnnotator.cpp
M clang/lib/Frontend/CompilerInvocation.cpp
M clang/lib/Interpreter/Interpreter.cpp
M clang/lib/Parse/ParseDecl.cpp
M clang/lib/Sema/SemaAvailability.cpp
M clang/lib/Sema/SemaChecking.cpp
M clang/lib/Sema/SemaConcept.cpp
M clang/lib/Sema/SemaDecl.cpp
M clang/lib/Sema/SemaDeclAttr.cpp
M clang/lib/Sema/SemaOpenACCAtomic.cpp
M clang/lib/Sema/SemaOpenMP.cpp
M clang/lib/Sema/SemaTemplateDeduction.cpp
M clang/lib/StaticAnalyzer/Checkers/MallocChecker.cpp
M clang/test/APINotes/Inputs/Headers/SwiftImportAs.apinotes
M clang/test/APINotes/Inputs/Headers/SwiftImportAs.h
M clang/test/APINotes/swift-import-as.cpp
M clang/test/AST/ByteCode/unions.cpp
M clang/test/Analysis/malloc.c
A clang/test/CIR/CodeGen/array-ctor.cpp
M clang/test/CIR/CodeGen/bitfields.c
A clang/test/CIR/CodeGen/complex-cast.cpp
A clang/test/CIR/IR/array-ctor.cir
M clang/test/CodeGen/AArch64/neon-intrinsics.c
A clang/test/CodeGen/builtin-maximumnum-minimumnum.c
M clang/test/CodeGenCXX/builtin-amdgcn-fence.cpp
M clang/test/CodeGenCXX/microsoft-abi-eh-disabled.cpp
M clang/test/CodeGenCXX/microsoft-abi-eh-ip2state.cpp
M clang/test/Driver/hip-phases.hip
M clang/test/Driver/offload-target.c
M clang/test/Driver/openbsd.c
M clang/test/Driver/sparc-target-features.c
M clang/test/Interpreter/fail.cpp
M clang/test/Interpreter/pretty-print.c
M clang/test/Interpreter/pretty-print.cpp
M clang/test/Layout/ms-no-unique-address.cpp
M clang/test/Misc/time-passes.c
A clang/test/OpenMP/copy-gaps-1.cpp
A clang/test/OpenMP/copy-gaps-2.cpp
A clang/test/OpenMP/copy-gaps-3.cpp
A clang/test/OpenMP/copy-gaps-4.cpp
A clang/test/OpenMP/copy-gaps-5.cpp
A clang/test/OpenMP/copy-gaps-6.cpp
M clang/test/OpenMP/declare_variant_clauses_ast_print.cpp
M clang/test/OpenMP/declare_variant_clauses_messages.cpp
A clang/test/OpenMP/target_map_array_section_no_length_codegen.cpp
M clang/test/OpenMP/target_map_codegen_35.cpp
M clang/test/OpenMP/target_map_messages.cpp
M clang/test/Sema/builtins-elementwise-math.c
A clang/test/Sema/implicit-special-member-deprecated.cpp
A clang/test/Sema/unsupported-arm-streaming.cpp
M clang/test/SemaCXX/cxx2a-ms-no-unique-address.cpp
M clang/test/SemaCXX/wreturn-always-throws.cpp
M clang/test/SemaOpenACC/atomic-construct.cpp
M clang/test/SemaTemplate/concepts.cpp
M clang/test/SemaTemplate/deduction-guide.cpp
M clang/tools/driver/cc1_main.cpp
M clang/unittests/Analysis/LifetimeSafetyTest.cpp
M clang/unittests/Format/ConfigParseTest.cpp
M clang/unittests/Format/FormatTest.cpp
M clang/unittests/Interpreter/InterpreterTest.cpp
M compiler-rt/lib/asan/asan_allocator.cpp
M compiler-rt/lib/asan/asan_allocator.h
M compiler-rt/lib/asan/asan_mac.cpp
M compiler-rt/lib/asan/asan_malloc_linux.cpp
M compiler-rt/lib/asan/asan_malloc_mac.cpp
M compiler-rt/lib/asan/asan_malloc_win.cpp
M compiler-rt/lib/asan/asan_new_delete.cpp
M compiler-rt/lib/asan/asan_thread.cpp
M compiler-rt/lib/asan/asan_thread.h
M compiler-rt/lib/asan/tests/asan_mac_test.cpp
M compiler-rt/lib/asan/tests/asan_mac_test.h
M compiler-rt/lib/asan/tests/asan_mac_test_helpers.mm
M compiler-rt/lib/asan/tests/asan_noinst_test.cpp
M compiler-rt/lib/builtins/CMakeLists.txt
M compiler-rt/lib/hwasan/hwasan_thread.cpp
M compiler-rt/lib/hwasan/hwasan_thread.h
M compiler-rt/lib/lsan/lsan_common.cpp
M compiler-rt/lib/lsan/lsan_common.h
M compiler-rt/lib/lsan/lsan_interceptors.cpp
M compiler-rt/lib/lsan/lsan_posix.cpp
M compiler-rt/lib/lsan/lsan_posix.h
M compiler-rt/lib/lsan/lsan_thread.cpp
M compiler-rt/lib/lsan/lsan_thread.h
M compiler-rt/lib/memprof/memprof_thread.cpp
M compiler-rt/lib/memprof/memprof_thread.h
M compiler-rt/lib/sanitizer_common/sanitizer_common.h
M compiler-rt/lib/sanitizer_common/sanitizer_fuchsia.cpp
M compiler-rt/lib/sanitizer_common/sanitizer_haiku.cpp
M compiler-rt/lib/sanitizer_common/sanitizer_internal_defs.h
M compiler-rt/lib/sanitizer_common/sanitizer_linux.cpp
M compiler-rt/lib/sanitizer_common/sanitizer_linux.h
M compiler-rt/lib/sanitizer_common/sanitizer_mac.cpp
M compiler-rt/lib/sanitizer_common/sanitizer_netbsd.cpp
M compiler-rt/lib/sanitizer_common/sanitizer_stoptheworld.h
M compiler-rt/lib/sanitizer_common/sanitizer_stoptheworld_linux_libcdep.cpp
M compiler-rt/lib/sanitizer_common/sanitizer_stoptheworld_mac.cpp
M compiler-rt/lib/sanitizer_common/sanitizer_stoptheworld_netbsd_libcdep.cpp
M compiler-rt/lib/sanitizer_common/sanitizer_stoptheworld_win.cpp
M compiler-rt/lib/sanitizer_common/sanitizer_thread_registry.cpp
M compiler-rt/lib/sanitizer_common/sanitizer_thread_registry.h
M compiler-rt/lib/sanitizer_common/sanitizer_win.cpp
M compiler-rt/lib/sanitizer_common/tests/sanitizer_linux_test.cpp
M compiler-rt/lib/tsan/rtl/tsan_debugging.cpp
M compiler-rt/lib/tsan/rtl/tsan_interceptors_posix.cpp
M compiler-rt/lib/tsan/rtl/tsan_interface.h
M compiler-rt/lib/tsan/rtl/tsan_report.h
M compiler-rt/lib/tsan/rtl/tsan_rtl.h
M compiler-rt/lib/tsan/rtl/tsan_rtl_thread.cpp
M compiler-rt/lib/xray/xray_fdr_controller.h
M compiler-rt/lib/xray/xray_profile_collector.cpp
M compiler-rt/lib/xray/xray_profile_collector.h
A compiler-rt/test/asan/TestCases/Darwin/dispatch_apply_threadno.c
M flang-rt/unittests/Runtime/CUDA/AllocatorCUF.cpp
M flang/docs/ReleaseNotes.md
M flang/include/flang/Frontend/TargetOptions.h
M flang/include/flang/Lower/Support/ReductionProcessor.h
M flang/include/flang/Optimizer/Builder/IntrinsicCall.h
M flang/include/flang/Optimizer/Dialect/Support/FIRContext.h
A flang/include/flang/Parser/openmp-utils.h
M flang/include/flang/Parser/parse-tree.h
M flang/lib/Evaluate/intrinsics.cpp
M flang/lib/Frontend/CompilerInvocation.cpp
M flang/lib/Lower/Bridge.cpp
M flang/lib/Lower/IO.cpp
M flang/lib/Lower/OpenMP/Atomic.cpp
M flang/lib/Lower/OpenMP/ClauseProcessor.cpp
M flang/lib/Lower/OpenMP/DataSharingProcessor.cpp
M flang/lib/Lower/OpenMP/OpenMP.cpp
M flang/lib/Lower/OpenMP/Utils.cpp
M flang/lib/Lower/OpenMP/Utils.h
M flang/lib/Lower/Support/ReductionProcessor.cpp
M flang/lib/Optimizer/Builder/IntrinsicCall.cpp
M flang/lib/Optimizer/Dialect/Support/FIRContext.cpp
M flang/lib/Optimizer/Transforms/ExternalNameConversion.cpp
M flang/lib/Parser/openmp-parsers.cpp
M flang/lib/Parser/unparse.cpp
M flang/lib/Semantics/canonicalize-omp.cpp
M flang/lib/Semantics/check-omp-structure.cpp
A flang/test/Lower/Intrinsics/acospi.f90
A flang/test/Lower/Intrinsics/asinpi.f90
A flang/test/Lower/Intrinsics/sinpi.f90
A flang/test/Lower/Intrinsics/tanpi.f90
A flang/test/Lower/OpenMP/atomic-control-options.f90
A flang/test/Lower/OpenMP/wsloop-reduction-non-intrinsic.f90
A flang/test/Lower/assign-statement.f90
A flang/test/Lower/equivalence-3.f
A flang/test/Parser/OpenMP/block-construct.f90
A flang/test/Parser/OpenMP/construct-prefix-conflict.f90
A flang/test/Semantics/OpenMP/assumed-size-array.f90
A flang/test/Transforms/external-name-interop-symref-array.fir
M flang/unittests/CMakeLists.txt
M libc/benchmarks/gpu/BenchmarkLogger.cpp
M libc/benchmarks/gpu/CMakeLists.txt
M libc/benchmarks/gpu/LibcGpuBenchmark.h
M libc/benchmarks/gpu/src/math/CMakeLists.txt
M libc/benchmarks/gpu/src/math/platform.h
M libc/benchmarks/gpu/timing/amdgpu/CMakeLists.txt
M libc/benchmarks/gpu/timing/amdgpu/timing.h
M libc/benchmarks/gpu/timing/nvptx/CMakeLists.txt
M libc/benchmarks/gpu/timing/nvptx/timing.h
M libc/config/CMakeLists.txt
M libc/config/gpu/app.h
M libc/config/linux/app.h
M libc/config/uefi/app.h
M libc/hdr/CMakeLists.txt
A libc/hdr/stdint_proxy.h
M libc/hdr/types/CMakeLists.txt
M libc/include/CMakeLists.txt
M libc/shared/sign.h
M libc/src/__support/CMakeLists.txt
M libc/src/__support/CPP/CMakeLists.txt
M libc/src/__support/CPP/bit.h
M libc/src/__support/CPP/functional.h
M libc/src/__support/FPUtil/CMakeLists.txt
M libc/src/__support/FPUtil/FPBits.h
M libc/src/__support/FPUtil/NormalFloat.h
M libc/src/__support/FPUtil/aarch64/FEnvImpl.h
M libc/src/__support/FPUtil/aarch64/fenv_darwin_impl.h
M libc/src/__support/FPUtil/arm/FEnvImpl.h
M libc/src/__support/FPUtil/bfloat16.h
M libc/src/__support/FPUtil/riscv/FEnvImpl.h
M libc/src/__support/FPUtil/rounding_mode.h
M libc/src/__support/FPUtil/x86_64/FEnvImpl.h
M libc/src/__support/FPUtil/x86_64/NextAfterLongDouble.h
M libc/src/__support/File/CMakeLists.txt
M libc/src/__support/File/file.h
M libc/src/__support/File/linux/CMakeLists.txt
M libc/src/__support/File/linux/lseekImpl.h
M libc/src/__support/GPU/CMakeLists.txt
M libc/src/__support/GPU/allocator.cpp
M libc/src/__support/GPU/allocator.h
M libc/src/__support/HashTable/CMakeLists.txt
M libc/src/__support/HashTable/bitmask.h
M libc/src/__support/HashTable/table.h
M libc/src/__support/RPC/rpc_server.h
M libc/src/__support/arg_list.h
M libc/src/__support/big_int.h
M libc/src/__support/block.h
M libc/src/__support/blockstore.h
M libc/src/__support/detailed_powers_of_ten.h
M libc/src/__support/endian_internal.h
M libc/src/__support/fixed_point/CMakeLists.txt
M libc/src/__support/fixed_point/fx_rep.h
M libc/src/__support/float_to_string.h
M libc/src/__support/hash.h
M libc/src/__support/high_precision_decimal.h
M libc/src/__support/integer_literals.h
M libc/src/__support/integer_to_string.h
M libc/src/__support/macros/properties/CMakeLists.txt
M libc/src/__support/macros/properties/types.h
M libc/src/__support/math/CMakeLists.txt
M libc/src/__support/math/exp10_float16_constants.h
M libc/src/__support/ryu_constants.h
M libc/src/__support/ryu_long_double_constants.h
M libc/src/__support/str_to_float.h
M libc/src/__support/threads/CMakeLists.txt
M libc/src/__support/threads/CndVar.h
M libc/src/__support/threads/linux/CMakeLists.txt
M libc/src/__support/threads/linux/futex_word.h
M libc/src/__support/threads/linux/thread.cpp
M libc/src/__support/threads/thread.h
M libc/src/__support/wchar/CMakeLists.txt
M libc/src/__support/wchar/mbrtowc.cpp
M libc/src/__support/wchar/mbstate.h
M libc/src/arpa/inet/CMakeLists.txt
M libc/src/arpa/inet/htonl.h
M libc/src/arpa/inet/htons.h
M libc/src/arpa/inet/ntohl.h
M libc/src/arpa/inet/ntohs.h
M libc/src/compiler/generic/CMakeLists.txt
M libc/src/compiler/generic/__stack_chk_fail.cpp
M libc/src/inttypes/CMakeLists.txt
M libc/src/inttypes/strtoimax.h
M libc/src/inttypes/strtoumax.h
M libc/src/link/CMakeLists.txt
M libc/src/math/generic/CMakeLists.txt
M libc/src/math/generic/expxf16.h
M libc/src/pthread/CMakeLists.txt
M libc/src/pthread/pthread_attr_setstack.cpp
M libc/src/sched/linux/CMakeLists.txt
M libc/src/sched/linux/sched_getaffinity.cpp
M libc/src/spawn/CMakeLists.txt
M libc/src/spawn/file_actions.h
M libc/src/stdio/gpu/CMakeLists.txt
M libc/src/stdio/gpu/fgets.cpp
M libc/src/stdio/printf_core/CMakeLists.txt
M libc/src/stdlib/CMakeLists.txt
M libc/src/stdlib/a64l.cpp
M libc/src/stdlib/bsearch.cpp
M libc/src/stdlib/l64a.cpp
M libc/src/stdlib/qsort.cpp
M libc/src/stdlib/qsort_data.h
M libc/src/stdlib/qsort_r.cpp
M libc/src/stdlib/quick_sort.h
M libc/src/string/CMakeLists.txt
M libc/src/string/memory_utils/CMakeLists.txt
M libc/src/string/memory_utils/op_generic.h
M libc/src/string/memory_utils/utils.h
M libc/src/string/memory_utils/x86_64/inline_memcpy.h
M libc/src/string/string_utils.h
M libc/src/sys/stat/linux/CMakeLists.txt
M libc/src/sys/stat/linux/kernel_statx.h
M libc/src/time/CMakeLists.txt
M libc/src/time/linux/CMakeLists.txt
M libc/src/time/linux/nanosleep.cpp
M libc/src/time/strftime_core/CMakeLists.txt
M libc/src/time/strftime_core/core_structs.h
M libc/src/time/time_constants.h
M libc/src/time/time_utils.cpp
M libc/src/time/time_utils.h
M libc/src/unistd/linux/CMakeLists.txt
M libc/src/unistd/linux/ftruncate.cpp
M libc/src/unistd/linux/pread.cpp
M libc/src/unistd/linux/pwrite.cpp
M libc/src/unistd/linux/truncate.cpp
M libc/src/wchar/mbtowc.cpp
M libc/startup/baremetal/CMakeLists.txt
M libc/startup/baremetal/fini.cpp
M libc/startup/baremetal/init.cpp
M libc/startup/linux/CMakeLists.txt
M libc/startup/linux/do_start.cpp
M libc/test/IntegrationTest/CMakeLists.txt
M libc/test/IntegrationTest/test.cpp
M libc/test/UnitTest/CMakeLists.txt
M libc/test/UnitTest/ExecuteFunction.h
M libc/test/UnitTest/HermeticTestUtils.cpp
M libc/test/UnitTest/PrintfMatcher.cpp
M libc/test/UnitTest/RoundingModeUtils.h
M libc/test/UnitTest/ScanfMatcher.cpp
M libc/test/UnitTest/TestLogger.cpp
M libc/test/integration/src/pthread/CMakeLists.txt
M libc/test/integration/src/pthread/pthread_equal_test.cpp
M libc/test/integration/src/pthread/pthread_mutex_test.cpp
M libc/test/integration/src/pthread/pthread_name_test.cpp
M libc/test/integration/src/pthread/pthread_once_test.cpp
M libc/test/integration/src/pthread/pthread_test.cpp
M libc/test/integration/src/spawn/CMakeLists.txt
M libc/test/integration/src/spawn/posix_spawn_test.cpp
M libc/test/src/CMakeLists.txt
M libc/test/src/__support/CMakeLists.txt
M libc/test/src/__support/CPP/CMakeLists.txt
M libc/test/src/__support/CPP/bit_test.cpp
M libc/test/src/__support/HashTable/CMakeLists.txt
M libc/test/src/__support/HashTable/group_test.cpp
M libc/test/src/__support/str_to_float_comparison_test.cpp
M libc/test/src/fenv/feclearexcept_test.cpp
M libc/test/src/math/LdExpTest.h
M libc/test/src/math/acosf_test.cpp
M libc/test/src/math/acoshf16_test.cpp
M libc/test/src/math/acoshf_test.cpp
M libc/test/src/math/asinf_test.cpp
M libc/test/src/math/asinhf_test.cpp
M libc/test/src/math/atanf_test.cpp
M libc/test/src/math/atanhf16_test.cpp
M libc/test/src/math/atanhf_test.cpp
M libc/test/src/math/cosf_test.cpp
M libc/test/src/math/coshf_test.cpp
M libc/test/src/math/erff_test.cpp
M libc/test/src/math/exp10_test.cpp
M libc/test/src/math/exp10f_test.cpp
M libc/test/src/math/exp10m1f_test.cpp
M libc/test/src/math/exp2_test.cpp
M libc/test/src/math/exp2f_test.cpp
M libc/test/src/math/exp2m1f_test.cpp
M libc/test/src/math/exp_test.cpp
M libc/test/src/math/expf_test.cpp
M libc/test/src/math/expm1_test.cpp
M libc/test/src/math/expm1f_test.cpp
M libc/test/src/math/in_float_range_test_helper.h
M libc/test/src/math/log10_test.cpp
M libc/test/src/math/log10f_test.cpp
M libc/test/src/math/log1p_test.cpp
M libc/test/src/math/log1pf_test.cpp
M libc/test/src/math/log2_test.cpp
M libc/test/src/math/log2f_test.cpp
M libc/test/src/math/log_test.cpp
M libc/test/src/math/logf_test.cpp
M libc/test/src/math/performance_testing/Timer.h
M libc/test/src/math/performance_testing/fmodf16_perf.cpp
M libc/test/src/math/powf_test.cpp
M libc/test/src/math/sdcomp26094.h
M libc/test/src/math/sincosf_test.cpp
M libc/test/src/math/sinf_test.cpp
M libc/test/src/math/sinhf_test.cpp
M libc/test/src/math/sinpif_test.cpp
M libc/test/src/math/smoke/LdExpTest.h
M libc/test/src/math/smoke/acosf_test.cpp
M libc/test/src/math/smoke/acoshf_test.cpp
M libc/test/src/math/smoke/asinf_test.cpp
M libc/test/src/math/smoke/asinhf_test.cpp
M libc/test/src/math/smoke/atanf_test.cpp
M libc/test/src/math/smoke/atanhf_test.cpp
M libc/test/src/math/smoke/cosf_test.cpp
M libc/test/src/math/smoke/coshf_test.cpp
M libc/test/src/math/smoke/cospif_test.cpp
M libc/test/src/math/smoke/erff_test.cpp
M libc/test/src/math/smoke/exp10_test.cpp
M libc/test/src/math/smoke/exp10f_test.cpp
M libc/test/src/math/smoke/exp2_test.cpp
M libc/test/src/math/smoke/exp2f_test.cpp
M libc/test/src/math/smoke/exp_test.cpp
M libc/test/src/math/smoke/expf_test.cpp
M libc/test/src/math/smoke/expm1_test.cpp
M libc/test/src/math/smoke/expm1f_test.cpp
M libc/test/src/math/smoke/log10_test.cpp
M libc/test/src/math/smoke/log10f_test.cpp
M libc/test/src/math/smoke/log1pf_test.cpp
M libc/test/src/math/smoke/log2_test.cpp
M libc/test/src/math/smoke/log2f_test.cpp
M libc/test/src/math/smoke/log_test.cpp
M libc/test/src/math/smoke/logf_test.cpp
M libc/test/src/math/smoke/powf_test.cpp
M libc/test/src/math/smoke/sincosf_test.cpp
M libc/test/src/math/smoke/sinf_test.cpp
M libc/test/src/math/smoke/sinhf_test.cpp
M libc/test/src/math/smoke/sinpif_test.cpp
M libc/test/src/math/smoke/tanf_test.cpp
M libc/test/src/math/smoke/tanhf_test.cpp
M libc/test/src/math/tanf_test.cpp
M libc/test/src/math/tanhf_test.cpp
M libc/test/src/signal/CMakeLists.txt
M libc/test/src/signal/sigaltstack_test.cpp
M libc/test/src/spawn/CMakeLists.txt
M libc/test/src/spawn/posix_spawn_file_actions_test.cpp
M libc/test/src/stdlib/CMakeLists.txt
M libc/test/src/stdlib/memalignment_test.cpp
M libc/test/src/stdlib/strtoint32_test.cpp
M libc/test/src/stdlib/strtoint64_test.cpp
M libc/test/src/string/memory_utils/CMakeLists.txt
M libc/test/src/string/memory_utils/memory_check_utils.h
M libc/test/src/string/memory_utils/protected_pages.h
M libc/test/src/wchar/mbrtowc_test.cpp
M libc/utils/MPCWrapper/CMakeLists.txt
M libc/utils/MPCWrapper/MPCUtils.cpp
M libc/utils/MPCWrapper/MPCUtils.h
M libc/utils/MPFRWrapper/CMakeLists.txt
M libc/utils/MPFRWrapper/MPCommon.h
M libc/utils/MPFRWrapper/MPFRUtils.h
M libcxxabi/src/demangle/DemangleConfig.h
M libcxxabi/src/demangle/ItaniumDemangle.h
M libunwind/src/UnwindCursor.hpp
M lld/ELF/Arch/LoongArch.cpp
M lld/ELF/Config.h
M lld/ELF/Driver.cpp
M lld/ELF/InputFiles.cpp
M lld/ELF/Writer.cpp
M lld/docs/ReleaseNotes.rst
A lld/test/ELF/aarch64-build-attributes-be.s
A lld/test/ELF/aarch64-build-attributes-err.s
A lld/test/ELF/aarch64-build-attributes-invalid.s
A lld/test/ELF/aarch64-build-attributes-malformed.s
A lld/test/ELF/aarch64-build-attributes-mixed.s
M lld/test/ELF/aarch64-build-attributes.s
A lld/test/ELF/keep-data-section-prefix.s
M lld/test/ELF/loongarch-relax-tlsdesc.s
M lldb/cmake/modules/LLDBConfig.cmake
M lldb/include/lldb/Core/dwarf.h
M lldb/include/lldb/lldb-enumerations.h
M lldb/source/API/CMakeLists.txt
M lldb/source/Expression/DWARFExpression.cpp
M lldb/source/Host/windows/MainLoopWindows.cpp
M lldb/source/Host/windows/PipeWindows.cpp
M lldb/source/Plugins/Language/CPlusPlus/CMakeLists.txt
M lldb/source/Plugins/Language/CPlusPlus/CPlusPlusLanguage.cpp
M lldb/source/Plugins/Language/CPlusPlus/MsvcStl.h
A lldb/source/Plugins/Language/CPlusPlus/MsvcStlDeque.cpp
A lldb/source/Plugins/Language/CPlusPlus/MsvcStlTree.cpp
M lldb/source/Plugins/SymbolFile/CTF/SymbolFileCTF.cpp
M lldb/source/Plugins/SymbolFile/DWARF/AppleDWARFIndex.cpp
M lldb/source/Plugins/SymbolFile/DWARF/DWARFASTParser.cpp
M lldb/source/Plugins/SymbolFile/DWARF/DWARFASTParserClang.cpp
M lldb/source/Plugins/SymbolFile/DWARF/DWARFAttribute.cpp
M lldb/source/Plugins/SymbolFile/DWARF/DWARFDIE.cpp
M lldb/source/Plugins/SymbolFile/DWARF/DWARFDebugInfo.cpp
M lldb/source/Plugins/SymbolFile/DWARF/DWARFDebugInfoEntry.cpp
M lldb/source/Plugins/SymbolFile/DWARF/DWARFDebugMacro.cpp
M lldb/source/Plugins/SymbolFile/DWARF/DWARFDeclContext.cpp
M lldb/source/Plugins/SymbolFile/DWARF/DWARFFormValue.cpp
M lldb/source/Plugins/SymbolFile/DWARF/DWARFUnit.cpp
M lldb/source/Plugins/SymbolFile/DWARF/DebugNamesDWARFIndex.cpp
M lldb/source/Plugins/SymbolFile/DWARF/ManualDWARFIndex.cpp
M lldb/source/Plugins/SymbolFile/DWARF/SymbolFileDWARF.cpp
M lldb/source/Plugins/SymbolFile/DWARF/UniqueDWARFASTType.cpp
M lldb/source/Plugins/SymbolFile/PDB/PDBLocationToDWARFExpression.cpp
M lldb/source/Plugins/TypeSystem/Clang/TypeSystemClang.cpp
M lldb/source/Symbol/CompilerType.cpp
M lldb/source/Symbol/DWARFCallFrameInfo.cpp
M lldb/source/Symbol/PostfixExpression.cpp
M lldb/source/Target/Language.cpp
M lldb/source/ValueObject/ValueObject.cpp
M lldb/test/API/functionalities/data-formatter/data-formatter-stl/generic/deque/TestDataFormatterGenericDeque.py
M lldb/test/API/functionalities/data-formatter/data-formatter-stl/generic/map/TestDataFormatterStdMap.py
M lldb/test/API/functionalities/data-formatter/data-formatter-stl/generic/map/main.cpp
M lldb/test/API/functionalities/data-formatter/data-formatter-stl/generic/multimap/TestDataFormatterGenericMultiMap.py
M lldb/test/API/functionalities/data-formatter/data-formatter-stl/generic/multiset/TestDataFormatterGenericMultiSet.py
M lldb/test/API/functionalities/data-formatter/data-formatter-stl/generic/set/TestDataFormatterGenericSet.py
M lldb/test/API/functionalities/data-formatter/data-formatter-stl/generic/set/main.cpp
A lldb/test/API/python_api/sbtype_basic_type/Makefile
A lldb/test/API/python_api/sbtype_basic_type/TestSBTypeBasicType.py
A lldb/test/API/python_api/sbtype_basic_type/main.cpp
M lldb/test/CMakeLists.txt
A lldb/test/Shell/RPC/Generator/Inputs/SBDummy.h
A lldb/test/Shell/RPC/Generator/Tests/CheckRPCGenToolByproducts.test
A lldb/test/Shell/RPC/Generator/lit.local.cfg
M lldb/test/Shell/helper/toolchain.py
M lldb/test/Shell/lit.site.cfg.py.in
M lldb/tools/CMakeLists.txt
A lldb/tools/lldb-rpc-gen/CMakeLists.txt
A lldb/tools/lldb-rpc-gen/RPCCommon.cpp
A lldb/tools/lldb-rpc-gen/RPCCommon.h
A lldb/tools/lldb-rpc-gen/lldb-rpc-gen.cpp
A lldb/tools/lldb-rpc-gen/server/RPCServerHeaderEmitter.cpp
A lldb/tools/lldb-rpc-gen/server/RPCServerHeaderEmitter.h
A lldb/tools/lldb-rpc-gen/server/RPCServerSourceEmitter.cpp
A lldb/tools/lldb-rpc-gen/server/RPCServerSourceEmitter.h
A lldb/tools/lldb-rpc/CMakeLists.txt
A lldb/tools/lldb-rpc/LLDBRPCGeneration.cmake
A lldb/tools/lldb-rpc/LLDBRPCHeaders.cmake
R lldb/tools/lldb-rpc/lldb-rpc-gen/lldb-rpc-gen.cpp
R lldb/tools/lldb-rpc/lldb-rpc-gen/server/RPCServerHeaderEmitter.cpp
R lldb/tools/lldb-rpc/lldb-rpc-gen/server/RPCServerHeaderEmitter.h
R lldb/tools/lldb-rpc/lldb-rpc-gen/server/RPCServerSourceEmitter.cpp
R lldb/tools/lldb-rpc/lldb-rpc-gen/server/RPCServerSourceEmitter.h
M lldb/unittests/Expression/DWARFExpressionTest.cpp
M lldb/unittests/Symbol/TestTypeSystemClang.cpp
M lldb/unittests/SymbolFile/DWARF/DWARF64UnitTest.cpp
M lldb/unittests/SymbolFile/DWARF/DWARFASTParserClangTests.cpp
M lldb/unittests/SymbolFile/DWARF/DWARFDIETest.cpp
M lldb/unittests/SymbolFile/DWARF/DWARFDebugNamesIndexTest.cpp
M lldb/unittests/SymbolFile/DWARF/SymbolFileDWARFTests.cpp
M llvm/Maintainers.md
M llvm/docs/AMDGPUUsage.rst
A llvm/docs/DirectX/RootSignatures.rst
M llvm/docs/DirectXUsage.rst
M llvm/docs/LangRef.rst
M llvm/docs/ReleaseNotes.md
M llvm/include/llvm/ADT/DenseMapInfo.h
M llvm/include/llvm/Analysis/TargetTransformInfo.h
M llvm/include/llvm/Analysis/TargetTransformInfoImpl.h
M llvm/include/llvm/CodeGen/BasicTTIImpl.h
M llvm/include/llvm/CodeGen/LinkAllAsmWriterComponents.h
M llvm/include/llvm/CodeGen/LinkAllCodegenComponents.h
M llvm/include/llvm/CodeGen/MachineInstrBundle.h
M llvm/include/llvm/CodeGen/Passes.h
M llvm/include/llvm/CodeGen/TargetLowering.h
M llvm/include/llvm/Config/abi-breaking.h.cmake
M llvm/include/llvm/Demangle/Demangle.h
M llvm/include/llvm/Demangle/DemangleConfig.h
M llvm/include/llvm/Demangle/ItaniumDemangle.h
M llvm/include/llvm/Demangle/MicrosoftDemangle.h
M llvm/include/llvm/Demangle/MicrosoftDemangleNodes.h
M llvm/include/llvm/ExecutionEngine/MCJIT.h
M llvm/include/llvm/Frontend/HLSL/RootSignatureMetadata.h
M llvm/include/llvm/IR/PatternMatch.h
M llvm/include/llvm/InitializePasses.h
M llvm/include/llvm/LinkAllIR.h
M llvm/include/llvm/LinkAllPasses.h
M llvm/include/llvm/MC/DXContainerRootSignature.h
M llvm/include/llvm/MC/MCSection.h
M llvm/include/llvm/Passes/MachinePassRegistry.def
M llvm/include/llvm/Support/AArch64AttributeParser.h
A llvm/include/llvm/Support/AlwaysTrue.h
M llvm/include/llvm/TargetParser/AArch64TargetParser.h
M llvm/include/llvm/Transforms/Utils/MemoryTaggingSupport.h
A llvm/include/llvm/Transforms/Utils/ProfileVerify.h
M llvm/lib/Analysis/ConstantFolding.cpp
M llvm/lib/Analysis/ProfileSummaryInfo.cpp
M llvm/lib/Analysis/ScalarEvolution.cpp
M llvm/lib/Analysis/StackLifetime.cpp
M llvm/lib/Analysis/TargetTransformInfo.cpp
M llvm/lib/Bitcode/Reader/BitcodeReader.cpp
M llvm/lib/CodeGen/AsmPrinter/DwarfCompileUnit.cpp
M llvm/lib/CodeGen/CodeGen.cpp
M llvm/lib/CodeGen/InterleavedAccessPass.cpp
M llvm/lib/CodeGen/MIRPrinter.cpp
M llvm/lib/CodeGen/MachineInstrBundle.cpp
M llvm/lib/CodeGen/MachineLICM.cpp
M llvm/lib/CodeGen/TargetLoweringObjectFileImpl.cpp
M llvm/lib/DebugInfo/DWARF/DWARFCFIPrinter.cpp
M llvm/lib/DebugInfo/DWARF/LowLevel/DWARFExpression.cpp
M llvm/lib/FileCheck/FileCheck.cpp
M llvm/lib/Frontend/HLSL/RootSignatureMetadata.cpp
M llvm/lib/IR/Type.cpp
M llvm/lib/IR/Value.cpp
M llvm/lib/MC/MCAssembler.cpp
M llvm/lib/MC/MCMachOStreamer.cpp
M llvm/lib/MC/MCObjectStreamer.cpp
M llvm/lib/Passes/PassBuilder.cpp
M llvm/lib/Passes/PassRegistry.def
M llvm/lib/Support/AArch64AttributeParser.cpp
M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
M llvm/lib/Target/AArch64/AArch64ISelLowering.h
M llvm/lib/Target/AArch64/AArch64InstrInfo.cpp
M llvm/lib/Target/AArch64/AArch64InstrInfo.td
M llvm/lib/Target/AArch64/AArch64RegisterInfo.td
M llvm/lib/Target/AArch64/AArch64SelectionDAGInfo.cpp
M llvm/lib/Target/AArch64/AArch64StackTagging.cpp
M llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp
M llvm/lib/Target/AArch64/AArch64TargetTransformInfo.h
M llvm/lib/Target/AArch64/MCTargetDesc/AArch64MCExpr.cpp
M llvm/lib/Target/AMDGPU/AMDGPU.td
M llvm/lib/Target/AMDGPU/AMDGPUAttributor.cpp
M llvm/lib/Target/AMDGPU/AMDGPUGlobalISelUtils.cpp
M llvm/lib/Target/AMDGPU/AMDGPUGlobalISelUtils.h
M llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp
M llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.h
M llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
M llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.h
M llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
M llvm/lib/Target/AMDGPU/AMDGPURegBankLegalize.cpp
M llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeHelper.cpp
M llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeHelper.h
M llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp
M llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.h
M llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp
M llvm/lib/Target/AMDGPU/AMDGPUSubtarget.h
M llvm/lib/Target/AMDGPU/FLATInstructions.td
M llvm/lib/Target/AMDGPU/GCNSubtarget.h
M llvm/lib/Target/AMDGPU/R600ExpandSpecialInstrs.cpp
M llvm/lib/Target/AMDGPU/R600TargetMachine.cpp
M llvm/lib/Target/AMDGPU/SIISelLowering.cpp
M llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
M llvm/lib/Target/AMDGPU/SIInstrInfo.td
M llvm/lib/Target/AMDGPU/SIMemoryLegalizer.cpp
M llvm/lib/Target/AMDGPU/VOP2Instructions.td
M llvm/lib/Target/AMDGPU/VOP3Instructions.td
M llvm/lib/Target/AMDGPU/VOP3PInstructions.td
M llvm/lib/Target/ARM/ARMISelLowering.cpp
M llvm/lib/Target/ARM/ARMISelLowering.h
M llvm/lib/Target/AVR/MCTargetDesc/AVRMCExpr.cpp
M llvm/lib/Target/BPF/BPF.h
M llvm/lib/Target/BPF/MCTargetDesc/BPFInstPrinter.cpp
M llvm/lib/Target/DirectX/DXILDataScalarization.cpp
M llvm/lib/Target/DirectX/DXILRootSignature.cpp
M llvm/lib/Target/DirectX/DXILRootSignature.h
M llvm/lib/Target/DirectX/DXILShaderFlags.cpp
M llvm/lib/Target/DirectX/DXILWriter/DXILWriterPass.cpp
M llvm/lib/Target/Hexagon/HexagonInstrFormats.td
R llvm/lib/Target/Hexagon/HexagonInstrFormatsV60.td
M llvm/lib/Target/Hexagon/HexagonInstrFormatsV65.td
R llvm/lib/Target/Hexagon/HexagonIntrinsicsV5.td
R llvm/lib/Target/Hexagon/HexagonIntrinsicsV60.td
M llvm/lib/Target/Hexagon/HexagonLoopIdiomRecognition.cpp
R llvm/lib/Target/Hexagon/HexagonMapAsm2IntrinV62.gen.td
M llvm/lib/Target/NVPTX/NVPTXISelLowering.cpp
M llvm/lib/Target/NVPTX/NVPTXISelLowering.h
M llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCExpr.cpp
M llvm/lib/Target/RISCV/RISCVFeatures.td
M llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
M llvm/lib/Target/RISCV/RISCVISelLowering.h
M llvm/lib/Target/RISCV/RISCVInstrInfoP.td
M llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
M llvm/lib/Target/RISCV/RISCVInstrInfoXAndes.td
M llvm/lib/Target/RISCV/RISCVInstrInfoXRivos.td
M llvm/lib/Target/RISCV/RISCVInstrInfoXSf.td
M llvm/lib/Target/RISCV/RISCVInstrInfoZvk.td
M llvm/lib/Target/RISCV/RISCVInterleavedAccess.cpp
M llvm/lib/Target/RISCV/RISCVSelectionDAGInfo.cpp
M llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
M llvm/lib/Target/RISCV/RISCVVLOptimizer.cpp
M llvm/lib/Target/SPIRV/SPIRVEmitIntrinsics.cpp
M llvm/lib/Target/Sparc/MCTargetDesc/SparcELFObjectWriter.cpp
M llvm/lib/Target/Sparc/MCTargetDesc/SparcMCExpr.cpp
M llvm/lib/Target/WebAssembly/WebAssemblyExplicitLocals.cpp
M llvm/lib/Target/WebAssembly/WebAssemblyISelDAGToDAG.cpp
M llvm/lib/Target/X86/AsmParser/X86AsmParser.cpp
M llvm/lib/Target/X86/MCTargetDesc/X86MCAsmInfo.cpp
M llvm/lib/Target/X86/X86ISelLowering.cpp
M llvm/lib/Target/X86/X86ISelLowering.h
M llvm/lib/Target/X86/X86InterleavedAccess.cpp
M llvm/lib/TargetParser/AArch64TargetParser.cpp
M llvm/lib/TargetParser/Triple.cpp
M llvm/lib/Transforms/AggressiveInstCombine/AggressiveInstCombine.cpp
M llvm/lib/Transforms/Coroutines/Coroutines.cpp
M llvm/lib/Transforms/HipStdPar/HipStdPar.cpp
M llvm/lib/Transforms/IPO/GlobalOpt.cpp
M llvm/lib/Transforms/InstCombine/InstCombineAddSub.cpp
M llvm/lib/Transforms/InstCombine/InstCombineAndOrXor.cpp
M llvm/lib/Transforms/InstCombine/InstCombineCompares.cpp
M llvm/lib/Transforms/InstCombine/InstCombineInternal.h
M llvm/lib/Transforms/InstCombine/InstCombineLoadStoreAlloca.cpp
M llvm/lib/Transforms/Instrumentation/AddressSanitizer.cpp
M llvm/lib/Transforms/Instrumentation/HWAddressSanitizer.cpp
M llvm/lib/Transforms/Instrumentation/IndirectCallPromotion.cpp
M llvm/lib/Transforms/Instrumentation/MemorySanitizer.cpp
M llvm/lib/Transforms/ObjCARC/ARCRuntimeEntryPoints.h
M llvm/lib/Transforms/ObjCARC/ObjCARCOpts.cpp
M llvm/lib/Transforms/Scalar/LoopIdiomRecognize.cpp
M llvm/lib/Transforms/Scalar/SimpleLoopUnswitch.cpp
M llvm/lib/Transforms/Scalar/TailRecursionElimination.cpp
M llvm/lib/Transforms/Utils/CMakeLists.txt
M llvm/lib/Transforms/Utils/Debugify.cpp
M llvm/lib/Transforms/Utils/LCSSA.cpp
M llvm/lib/Transforms/Utils/Local.cpp
M llvm/lib/Transforms/Utils/MemoryTaggingSupport.cpp
M llvm/lib/Transforms/Utils/PredicateInfo.cpp
A llvm/lib/Transforms/Utils/ProfileVerify.cpp
M llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
M llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
M llvm/lib/Transforms/Vectorize/VPlan.h
M llvm/lib/Transforms/Vectorize/VPlanRecipes.cpp
M llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp
M llvm/test/Analysis/CostModel/AArch64/sve-intrinsics.ll
M llvm/test/Analysis/CostModel/ARM/arith.ll
M llvm/test/Analysis/CostModel/RISCV/cast-sat.ll
M llvm/test/Analysis/CostModel/RISCV/rvv-shuffle.ll
M llvm/test/Analysis/CostModel/RISCV/vp-intrinsics.ll
M llvm/test/Analysis/LoopAccessAnalysis/different-strides-safe-dep-due-to-backedge-taken-count.ll
M llvm/test/Analysis/LoopAccessAnalysis/positive-dependence-distance-different-access-sizes.ll
M llvm/test/Analysis/MemorySSA/pr39197.ll
M llvm/test/Analysis/MemorySSA/pr43044.ll
M llvm/test/Analysis/MemorySSA/renamephis.ll
M llvm/test/Analysis/ScalarEvolution/add-expr-pointer-operand-sorting.ll
M llvm/test/Analysis/ScalarEvolution/sdiv.ll
M llvm/test/Analysis/ScalarEvolution/srem.ll
M llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-gep-flags.ll
M llvm/test/CodeGen/AArch64/abds-neg.ll
M llvm/test/CodeGen/AArch64/abds.ll
M llvm/test/CodeGen/AArch64/abdu-neg.ll
M llvm/test/CodeGen/AArch64/arm64-fold-lshr.ll
A llvm/test/CodeGen/AArch64/load-zext-bitcast.ll
M llvm/test/CodeGen/AArch64/sve-ld1-addressing-mode-reg-reg.ll
M llvm/test/CodeGen/AArch64/urem-lkk.ll
M llvm/test/CodeGen/AMDGPU/32-bit-local-address-space.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/add_shl.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/addo.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/addsubu64.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/artifact-combiner-asserts.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/assert-align.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/atomic_load_local.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/atomic_optimizations_mul_one.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/atomic_store_local.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/atomicrmw_udec_wrap.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/atomicrmw_uinc_wrap.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/bitcast_38_i16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/bool-legalization.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/buffer-atomic-fadd.f32-no-rtn.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/buffer-atomic-fadd.f32-rtn.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/buffer-atomic-fadd.f64.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/buffer-atomic-fadd.v2f16-no-rtn.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/buffer-atomic-fadd.v2f16-rtn.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/buffer-load-store-pointers.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/buffer-schedule.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/call-outgoing-stack-args.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/clamp-fmed3-const-combine.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/clamp-minmax-const-combine.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/combine-rsq.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/combine-shift-imm-chain.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/combine-shift-of-shifted-logic.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/combine-short-clamp.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/constant-bus-restriction.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/cvt_f32_ubyte.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/divergence-divergent-i1-phis-no-lane-mask-merging.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/divergence-divergent-i1-used-outside-loop.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/divergence-structurizer.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/divergence-temporal-divergent-i1.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/divergence-temporal-divergent-reg.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/divergent-control-flow.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/dynamic-alloca-uniform.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/extractelement-stack-lower.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/extractelement.i128.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/extractelement.i16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/extractelement.i8.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/extractelement.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/fdiv.f16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/fdiv.f32.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/fdiv.f64.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/flat-atomic-fadd.f32.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/flat-atomic-fadd.v2f16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/flat-scratch.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/fmed3-min-max-const-combine.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/fp64-atomics-gfx90a.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/frem.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/function-returns.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/hip.extern.shared.array.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/image-waterfall-loop-O0.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/inline-asm-mismatched-size.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/inline-asm.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/insertelement-stack-lower.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/insertelement.i16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/insertelement.i8.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/insertelement.large.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-amdgcn-cs-chain.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-amdgcn-sendmsg.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-amdgpu_kernel.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-assert-align.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-call-abi-attribute-hints.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-call-implicit-args.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-call-non-fixed.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-call-return-values.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-call-sret.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-call.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-constantexpr.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-constrained-fp.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-fence.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-function-args.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-indirect-call.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-inline-asm.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-invariant.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-memory-intrinsics.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-prefetch.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-ptrmask.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-sibling-call.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-tail-call.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-zext-vec-index.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/is-safe-to-sink-bug.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/lds-global-value.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/lds-misaligned-bug.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/lds-relocs.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/lds-zero-initializer.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-llvm.amdgcn.image.atomic.dim.a16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.abs.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.ballot.i32.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.ballot.i64.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.dispatch.ptr.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.div.scale.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.end.cf.i32.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.end.cf.i64.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.fdot2.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.fmul.legacy.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.global.atomic.csub.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.if.break.i32.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.if.break.i64.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.getresinfo.a16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.getresinfo.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.load.1d.d16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.load.1d.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.load.2d.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.load.2darraymsaa.a16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.load.2darraymsaa.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.load.3d.a16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.load.3d.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.sample.cd.g16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.sample.g16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.implicit.ptr.buffer.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.interp.inreg.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.interp.p1.f16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.intersect_ray.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.kernarg.segment.ptr.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.make.buffer.rsrc.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.mfma.gfx90a.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.mov.dpp.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.queue.ptr.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.buffer.atomic.add.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.buffer.atomic.cmpswap.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.buffer.atomic.fadd-with-ret.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.buffer.atomic.fadd.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.buffer.load.format.f16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.buffer.load.format.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.buffer.load.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.buffer.load.tfe.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.buffer.store.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.ptr.buffer.atomic.add.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.ptr.buffer.atomic.cmpswap.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.ptr.buffer.atomic.fadd-with-ret.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.ptr.buffer.atomic.fadd.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.ptr.buffer.load.format.f16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.ptr.buffer.load.format.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.ptr.buffer.load.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.ptr.buffer.store.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.ptr.tbuffer.load.f16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.ptr.tbuffer.load.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.ptr.tbuffer.store.f16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.ptr.tbuffer.store.i8.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.ptr.tbuffer.store.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.tbuffer.load.f16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.tbuffer.load.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.tbuffer.store.f16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.tbuffer.store.i8.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.tbuffer.store.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.rsq.clamp.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.s.buffer.load.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.s.setreg.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.s.sleep.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.sbfe.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.sdot2.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.sdot4.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.sdot8.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.set.inactive.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.softwqm.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.buffer.atomic.add.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.buffer.atomic.cmpswap.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.buffer.atomic.fadd-with-ret.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.buffer.atomic.fadd.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.buffer.load.format.f16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.buffer.load.format.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.buffer.load.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.buffer.load.tfe.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.buffer.store.format.f16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.buffer.store.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.ptr.buffer.atomic.add.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.ptr.buffer.atomic.cmpswap.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.ptr.buffer.atomic.fadd-with-ret.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.ptr.buffer.atomic.fadd.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.ptr.buffer.load.format.f16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.ptr.buffer.load.format.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.ptr.buffer.load.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.ptr.buffer.store.format.f16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.ptr.buffer.store.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.ptr.tbuffer.load.f16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.ptr.tbuffer.load.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.tbuffer.load.f16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.tbuffer.load.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.sudot4.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.sudot8.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.ubfe.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.udot2.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.udot4.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.udot8.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.update.dpp.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.wmma_32.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.wmma_64.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.workitem.id.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.wqm.demote.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.wqm.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.writelane.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.wwm.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.memcpy.inline.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.memcpy.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.memmove.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.memset.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/load-local.128.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/load-local.96.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/load-unaligned.ll
A llvm/test/CodeGen/AMDGPU/GlobalISel/load-uniform-in-vgpr.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/merge-buffer-stores.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/mul-known-bits.i64.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/mul.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/non-entry-alloca.ll
A llvm/test/CodeGen/AMDGPU/GlobalISel/readanylane-combines.ll
A llvm/test/CodeGen/AMDGPU/GlobalISel/readanylane-combines.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.raw.buffer.load.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.raw.ptr.buffer.load.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.struct.buffer.load.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.struct.ptr.buffer.load.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-and-s1.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-anyext.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-trunc.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/sdivrem.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/select-to-fmin-fmax.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/shader-epilogs.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/shl-ext-reduce.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/shlN_add.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/shufflevector.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/smed3.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/smrd.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/store-local.128.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/store-local.96.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/subo.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/trunc.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/udivrem.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/umed3.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/v_bfe_i32.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/widen-i8-i16-scalar-loads.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/wmma-gfx12-w32-f16-f32-matrix-modifiers.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/wmma-gfx12-w32-imm.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/wmma-gfx12-w32-iu-modifiers.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/wmma-gfx12-w32-swmmac-index_key.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/wmma-gfx12-w32.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/wmma-gfx12-w64-f16-f32-matrix-modifiers.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/wmma-gfx12-w64-imm.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/wmma-gfx12-w64-iu-modifiers.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/wmma-gfx12-w64-swmmac-index_key.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/wmma-gfx12-w64.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/xnor.ll
M llvm/test/CodeGen/AMDGPU/InlineAsmCrash.ll
M llvm/test/CodeGen/AMDGPU/acc-ldst.ll
A llvm/test/CodeGen/AMDGPU/add-max.ll
M llvm/test/CodeGen/AMDGPU/add.i16.ll
M llvm/test/CodeGen/AMDGPU/add.ll
M llvm/test/CodeGen/AMDGPU/add.v2i16.ll
M llvm/test/CodeGen/AMDGPU/add3.ll
M llvm/test/CodeGen/AMDGPU/add_i1.ll
M llvm/test/CodeGen/AMDGPU/add_i128.ll
M llvm/test/CodeGen/AMDGPU/add_i64.ll
M llvm/test/CodeGen/AMDGPU/add_shl.ll
A llvm/test/CodeGen/AMDGPU/add_u64.ll
M llvm/test/CodeGen/AMDGPU/addrspacecast-initializer-unsupported.ll
M llvm/test/CodeGen/AMDGPU/addrspacecast-initializer.ll
M llvm/test/CodeGen/AMDGPU/adjust-writemask-invalid-copy.ll
M llvm/test/CodeGen/AMDGPU/adjust-writemask-vectorized.ll
M llvm/test/CodeGen/AMDGPU/agpr-csr.ll
M llvm/test/CodeGen/AMDGPU/agpr-register-count.ll
M llvm/test/CodeGen/AMDGPU/agpr-remat.ll
M llvm/test/CodeGen/AMDGPU/alignbit-pat.ll
M llvm/test/CodeGen/AMDGPU/always-uniform.ll
M llvm/test/CodeGen/AMDGPU/amd.endpgm.ll
M llvm/test/CodeGen/AMDGPU/amdgcn-ieee.ll
M llvm/test/CodeGen/AMDGPU/amdgcn-load-offset-from-reg.ll
M llvm/test/CodeGen/AMDGPU/amdgcn.private-memory.ll
M llvm/test/CodeGen/AMDGPU/amdgpu-attributor-accesslist-offsetbins-out-of-sync.ll
M llvm/test/CodeGen/AMDGPU/amdgpu-cs-chain-cc.ll
M llvm/test/CodeGen/AMDGPU/amdgpu-cs-chain-preserve-cc.ll
M llvm/test/CodeGen/AMDGPU/amdgpu-mul24-knownbits.ll
M llvm/test/CodeGen/AMDGPU/amdgpu-nsa-threshold.ll
M llvm/test/CodeGen/AMDGPU/amdgpu-reloc-const.ll
M llvm/test/CodeGen/AMDGPU/amdgpu-shader-calling-convention.ll
M llvm/test/CodeGen/AMDGPU/amdgpu.private-memory.ll
M llvm/test/CodeGen/AMDGPU/amdgpu.work-item-intrinsics.deprecated.ll
M llvm/test/CodeGen/AMDGPU/amdpal-callable.ll
M llvm/test/CodeGen/AMDGPU/amdpal-cs.ll
M llvm/test/CodeGen/AMDGPU/amdpal-es.ll
M llvm/test/CodeGen/AMDGPU/amdpal-gs.ll
M llvm/test/CodeGen/AMDGPU/amdpal-hs.ll
M llvm/test/CodeGen/AMDGPU/amdpal-ls.ll
M llvm/test/CodeGen/AMDGPU/amdpal-msgpack-cs.ll
M llvm/test/CodeGen/AMDGPU/amdpal-msgpack-default.ll
M llvm/test/CodeGen/AMDGPU/amdpal-msgpack-denormal.ll
M llvm/test/CodeGen/AMDGPU/amdpal-msgpack-dx10-clamp.ll
M llvm/test/CodeGen/AMDGPU/amdpal-msgpack-es.ll
M llvm/test/CodeGen/AMDGPU/amdpal-msgpack-gs.ll
M llvm/test/CodeGen/AMDGPU/amdpal-msgpack-hs.ll
M llvm/test/CodeGen/AMDGPU/amdpal-msgpack-ieee.ll
M llvm/test/CodeGen/AMDGPU/amdpal-msgpack-ls.ll
M llvm/test/CodeGen/AMDGPU/amdpal-msgpack-ps.ll
M llvm/test/CodeGen/AMDGPU/amdpal-msgpack-psenable.ll
M llvm/test/CodeGen/AMDGPU/amdpal-msgpack-vs.ll
M llvm/test/CodeGen/AMDGPU/amdpal-ps.ll
M llvm/test/CodeGen/AMDGPU/amdpal-psenable.ll
M llvm/test/CodeGen/AMDGPU/amdpal-usersgpr-init.ll
M llvm/test/CodeGen/AMDGPU/amdpal-vs.ll
M llvm/test/CodeGen/AMDGPU/amdpal_scratch_mergedshader.ll
M llvm/test/CodeGen/AMDGPU/and-gcn.ll
M llvm/test/CodeGen/AMDGPU/and.ll
M llvm/test/CodeGen/AMDGPU/and_or.ll
M llvm/test/CodeGen/AMDGPU/andorbitset.ll
M llvm/test/CodeGen/AMDGPU/andorn2.ll
M llvm/test/CodeGen/AMDGPU/andorxorinvimm.ll
M llvm/test/CodeGen/AMDGPU/any_extend_vector_inreg.ll
M llvm/test/CodeGen/AMDGPU/anyext.ll
M llvm/test/CodeGen/AMDGPU/are-loads-from-same-base-ptr.ll
M llvm/test/CodeGen/AMDGPU/array-ptr-calc-i32.ll
M llvm/test/CodeGen/AMDGPU/array-ptr-calc-i64.ll
M llvm/test/CodeGen/AMDGPU/ashr.v2i16.ll
M llvm/test/CodeGen/AMDGPU/atomic_cmp_swap_local.ll
M llvm/test/CodeGen/AMDGPU/atomic_load_add.ll
M llvm/test/CodeGen/AMDGPU/atomic_load_local.ll
M llvm/test/CodeGen/AMDGPU/atomic_load_sub.ll
M llvm/test/CodeGen/AMDGPU/atomic_optimizations_buffer.ll
M llvm/test/CodeGen/AMDGPU/atomic_optimizations_global_pointer.ll
M llvm/test/CodeGen/AMDGPU/atomic_optimizations_pixelshader.ll
M llvm/test/CodeGen/AMDGPU/atomic_optimizations_raw_buffer.ll
M llvm/test/CodeGen/AMDGPU/atomic_optimizations_struct_buffer.ll
M llvm/test/CodeGen/AMDGPU/atomic_store_local.ll
M llvm/test/CodeGen/AMDGPU/atomicrmw-expand.ll
M llvm/test/CodeGen/AMDGPU/atomicrmw-nand.ll
M llvm/test/CodeGen/AMDGPU/atomics-cas-remarks-gfx90a.ll
M llvm/test/CodeGen/AMDGPU/atomics-hw-remarks-gfx90a.ll
M llvm/test/CodeGen/AMDGPU/atomics_cond_sub.ll
M llvm/test/CodeGen/AMDGPU/attr-amdgpu-flat-work-group-size-vgpr-limit.ll
M llvm/test/CodeGen/AMDGPU/attr-amdgpu-flat-work-group-size.ll
M llvm/test/CodeGen/AMDGPU/attr-amdgpu-num-sgpr.ll
M llvm/test/CodeGen/AMDGPU/attr-amdgpu-num-vgpr.ll
M llvm/test/CodeGen/AMDGPU/attr-amdgpu-waves-per-eu.ll
M llvm/test/CodeGen/AMDGPU/attr-unparseable.ll
M llvm/test/CodeGen/AMDGPU/attributor-flatscratchinit.ll
M llvm/test/CodeGen/AMDGPU/back-off-barrier-subtarget-feature.ll
M llvm/test/CodeGen/AMDGPU/basic-branch.ll
M llvm/test/CodeGen/AMDGPU/basic-call-return.ll
M llvm/test/CodeGen/AMDGPU/basic-loop.ll
M llvm/test/CodeGen/AMDGPU/bb-prolog-spill-during-regalloc.ll
M llvm/test/CodeGen/AMDGPU/bf16-conversions.ll
M llvm/test/CodeGen/AMDGPU/bf16-math.ll
M llvm/test/CodeGen/AMDGPU/bfe-patterns.ll
M llvm/test/CodeGen/AMDGPU/bfi_int.ll
M llvm/test/CodeGen/AMDGPU/bfi_nested.ll
M llvm/test/CodeGen/AMDGPU/bfm.ll
M llvm/test/CodeGen/AMDGPU/bitcast-constant-to-vector.ll
M llvm/test/CodeGen/AMDGPU/bitcast-v4f16-v4i16.ll
M llvm/test/CodeGen/AMDGPU/bitcast-vector-extract.ll
M llvm/test/CodeGen/AMDGPU/bitreverse-inline-immediates.ll
M llvm/test/CodeGen/AMDGPU/bitreverse.ll
M llvm/test/CodeGen/AMDGPU/br_cc.f16.ll
M llvm/test/CodeGen/AMDGPU/branch-relax-bundle.ll
M llvm/test/CodeGen/AMDGPU/branch-relax-spill.ll
M llvm/test/CodeGen/AMDGPU/branch-relaxation-gfx10-branch-offset-bug.ll
M llvm/test/CodeGen/AMDGPU/branch-relaxation-gfx1250.ll
M llvm/test/CodeGen/AMDGPU/branch-relaxation-inst-size-gfx10.ll
M llvm/test/CodeGen/AMDGPU/branch-relaxation.ll
M llvm/test/CodeGen/AMDGPU/branch-uniformity.ll
M llvm/test/CodeGen/AMDGPU/bswap.ll
M llvm/test/CodeGen/AMDGPU/buffer-atomic-fadd.f32-no-rtn.ll
M llvm/test/CodeGen/AMDGPU/buffer-atomic-fadd.f32-rtn.ll
M llvm/test/CodeGen/AMDGPU/buffer-atomic-fadd.f64.ll
M llvm/test/CodeGen/AMDGPU/buffer-atomic-fadd.v2f16-no-rtn.ll
M llvm/test/CodeGen/AMDGPU/buffer-atomic-fadd.v2f16-rtn.ll
M llvm/test/CodeGen/AMDGPU/buffer-intrinsics-mmo-offsets.ll
M llvm/test/CodeGen/AMDGPU/buffer-rsrc-ptr-ops.ll
M llvm/test/CodeGen/AMDGPU/buffer-schedule.ll
M llvm/test/CodeGen/AMDGPU/bug-deadlanes.ll
M llvm/test/CodeGen/AMDGPU/bug-sdag-scheduler-cycle.ll
M llvm/test/CodeGen/AMDGPU/bug-v4f64-subvector.ll
M llvm/test/CodeGen/AMDGPU/build-vector-insert-elt-infloop.ll
M llvm/test/CodeGen/AMDGPU/build-vector-packed-partial-undef.ll
M llvm/test/CodeGen/AMDGPU/byval-frame-setup.ll
M llvm/test/CodeGen/AMDGPU/call-argument-types.ll
M llvm/test/CodeGen/AMDGPU/call-c-function.ll
M llvm/test/CodeGen/AMDGPU/call-constexpr.ll
M llvm/test/CodeGen/AMDGPU/call-encoding.ll
M llvm/test/CodeGen/AMDGPU/call-graph-register-usage.ll
M llvm/test/CodeGen/AMDGPU/call-preserved-registers.ll
M llvm/test/CodeGen/AMDGPU/call-return-types.ll
M llvm/test/CodeGen/AMDGPU/callee-frame-setup.ll
M llvm/test/CodeGen/AMDGPU/calling-conventions.ll
M llvm/test/CodeGen/AMDGPU/captured-frame-index.ll
M llvm/test/CodeGen/AMDGPU/carryout-selection.ll
M llvm/test/CodeGen/AMDGPU/cc-sgpr-limit.ll
M llvm/test/CodeGen/AMDGPU/cc-sgpr-over-limit.ll
M llvm/test/CodeGen/AMDGPU/cf-loop-on-constant.ll
M llvm/test/CodeGen/AMDGPU/cgp-bitfield-extract.ll
M llvm/test/CodeGen/AMDGPU/chain-hi-to-lo.ll
M llvm/test/CodeGen/AMDGPU/clamp-modifier.ll
M llvm/test/CodeGen/AMDGPU/clamp.ll
M llvm/test/CodeGen/AMDGPU/cluster_stores.ll
M llvm/test/CodeGen/AMDGPU/cndmask-no-def-vcc.ll
M llvm/test/CodeGen/AMDGPU/coalesce-vgpr-alignment.ll
M llvm/test/CodeGen/AMDGPU/coalescer_remat.ll
M llvm/test/CodeGen/AMDGPU/code-size-estimate.ll
M llvm/test/CodeGen/AMDGPU/codegen-prepare-addrmode-sext.ll
M llvm/test/CodeGen/AMDGPU/collapse-endcf.ll
M llvm/test/CodeGen/AMDGPU/combine-add-zext-xor.ll
M llvm/test/CodeGen/AMDGPU/combine-and-sext-bool.ll
M llvm/test/CodeGen/AMDGPU/combine-cond-add-sub.ll
M llvm/test/CodeGen/AMDGPU/combine-ftrunc.ll
M llvm/test/CodeGen/AMDGPU/combine-vload-extract.ll
M llvm/test/CodeGen/AMDGPU/combine_andor_with_cmps.ll
M llvm/test/CodeGen/AMDGPU/commute-compares-scalar-float.ll
M llvm/test/CodeGen/AMDGPU/commute-compares.ll
M llvm/test/CodeGen/AMDGPU/commute-shifts.ll
M llvm/test/CodeGen/AMDGPU/commute_modifiers.ll
M llvm/test/CodeGen/AMDGPU/computeKnownBits-scalar-to-vector-crash.ll
M llvm/test/CodeGen/AMDGPU/concat_vectors.ll
M llvm/test/CodeGen/AMDGPU/constant-fold-mi-operands.ll
M llvm/test/CodeGen/AMDGPU/control-flow-fastregalloc.ll
M llvm/test/CodeGen/AMDGPU/control-flow-optnone.ll
M llvm/test/CodeGen/AMDGPU/convergence-tokens.ll
M llvm/test/CodeGen/AMDGPU/convergent-inlineasm.ll
M llvm/test/CodeGen/AMDGPU/copy_to_scc.ll
M llvm/test/CodeGen/AMDGPU/cross-block-use-is-not-abi-copy.ll
M llvm/test/CodeGen/AMDGPU/cse-convergent.ll
M llvm/test/CodeGen/AMDGPU/cse-phi-incoming-val.ll
M llvm/test/CodeGen/AMDGPU/ctlz.ll
M llvm/test/CodeGen/AMDGPU/ctlz_zero_undef.ll
M llvm/test/CodeGen/AMDGPU/ctpop.ll
M llvm/test/CodeGen/AMDGPU/ctpop16.ll
M llvm/test/CodeGen/AMDGPU/ctpop64.ll
M llvm/test/CodeGen/AMDGPU/cttz.ll
M llvm/test/CodeGen/AMDGPU/cttz_zero_undef.ll
M llvm/test/CodeGen/AMDGPU/cube.ll
M llvm/test/CodeGen/AMDGPU/cvt_f32_ubyte.ll
M llvm/test/CodeGen/AMDGPU/cvt_flr_i32_f32.ll
M llvm/test/CodeGen/AMDGPU/cvt_rpi_i32_f32.ll
M llvm/test/CodeGen/AMDGPU/dag-divergence.ll
M llvm/test/CodeGen/AMDGPU/dagcomb-shuffle-vecextend-non2.ll
M llvm/test/CodeGen/AMDGPU/dagcombine-fma-fmad.ll
M llvm/test/CodeGen/AMDGPU/dagcombine-lshr-and-cmp.ll
M llvm/test/CodeGen/AMDGPU/dagcombine-reassociate-bug.ll
M llvm/test/CodeGen/AMDGPU/dagcombine-select.ll
M llvm/test/CodeGen/AMDGPU/dagcombine-setcc-select.ll
M llvm/test/CodeGen/AMDGPU/debug-value.ll
M llvm/test/CodeGen/AMDGPU/debug-value2.ll
M llvm/test/CodeGen/AMDGPU/debug.ll
M llvm/test/CodeGen/AMDGPU/default-fp-mode.ll
M llvm/test/CodeGen/AMDGPU/direct-indirect-call.ll
M llvm/test/CodeGen/AMDGPU/disable_form_clauses.ll
M llvm/test/CodeGen/AMDGPU/div_v2i128.ll
M llvm/test/CodeGen/AMDGPU/diverge-extra-formal-args.ll
M llvm/test/CodeGen/AMDGPU/diverge-interp-mov-lower.ll
M llvm/test/CodeGen/AMDGPU/divergence-driven-bfe-isel.ll
M llvm/test/CodeGen/AMDGPU/divergent-branch-uniform-condition.ll
M llvm/test/CodeGen/AMDGPU/dpp64_combine.ll
M llvm/test/CodeGen/AMDGPU/dpp_combine.ll
M llvm/test/CodeGen/AMDGPU/drop-mem-operand-move-smrd.ll
M llvm/test/CodeGen/AMDGPU/ds-combine-large-stride.ll
M llvm/test/CodeGen/AMDGPU/ds-combine-with-dependence.ll
M llvm/test/CodeGen/AMDGPU/ds-negative-offset-addressing-mode-loop.ll
M llvm/test/CodeGen/AMDGPU/ds-sub-offset.ll
M llvm/test/CodeGen/AMDGPU/ds-vectorization-alignment.ll
M llvm/test/CodeGen/AMDGPU/ds_gws_align.ll
M llvm/test/CodeGen/AMDGPU/ds_read2.ll
M llvm/test/CodeGen/AMDGPU/ds_read2_offset_order.ll
M llvm/test/CodeGen/AMDGPU/ds_read2_superreg.ll
M llvm/test/CodeGen/AMDGPU/ds_read2st64.ll
M llvm/test/CodeGen/AMDGPU/ds_write2.ll
M llvm/test/CodeGen/AMDGPU/ds_write2st64.ll
M llvm/test/CodeGen/AMDGPU/dual-source-blend-export.ll
M llvm/test/CodeGen/AMDGPU/duplicate-attribute-indirect.ll
M llvm/test/CodeGen/AMDGPU/early-if-convert-cost.ll
M llvm/test/CodeGen/AMDGPU/early-if-convert.ll
M llvm/test/CodeGen/AMDGPU/elf.ll
M llvm/test/CodeGen/AMDGPU/else.ll
M llvm/test/CodeGen/AMDGPU/empty-function.ll
M llvm/test/CodeGen/AMDGPU/endcf-loop-header.ll
M llvm/test/CodeGen/AMDGPU/exceed-max-sgprs.ll
M llvm/test/CodeGen/AMDGPU/expand-atomicrmw-syncscope.ll
M llvm/test/CodeGen/AMDGPU/extend-bit-ops-i16.ll
M llvm/test/CodeGen/AMDGPU/extload-align.ll
M llvm/test/CodeGen/AMDGPU/extload-private.ll
M llvm/test/CodeGen/AMDGPU/extload.ll
M llvm/test/CodeGen/AMDGPU/extract-lowbits.ll
M llvm/test/CodeGen/AMDGPU/extract-subvector-16bit.ll
M llvm/test/CodeGen/AMDGPU/extract-subvector-equal-length.ll
M llvm/test/CodeGen/AMDGPU/extract-subvector.ll
M llvm/test/CodeGen/AMDGPU/extract-vector-elt-build-vector-combine.ll
M llvm/test/CodeGen/AMDGPU/extract_vector_elt-f16.ll
M llvm/test/CodeGen/AMDGPU/extract_vector_elt-f64.ll
M llvm/test/CodeGen/AMDGPU/extract_vector_elt-i16.ll
M llvm/test/CodeGen/AMDGPU/extract_vector_elt-i64.ll
M llvm/test/CodeGen/AMDGPU/extractelt-to-trunc.ll
M llvm/test/CodeGen/AMDGPU/fabs.f16.ll
M llvm/test/CodeGen/AMDGPU/fabs.f64.ll
M llvm/test/CodeGen/AMDGPU/fadd-fma-fmul-combine.ll
M llvm/test/CodeGen/AMDGPU/fadd.f16.ll
M llvm/test/CodeGen/AMDGPU/fadd.ll
M llvm/test/CodeGen/AMDGPU/fadd64.ll
A llvm/test/CodeGen/AMDGPU/fcanonicalize-elimination.bf16.ll
M llvm/test/CodeGen/AMDGPU/fcanonicalize-elimination.ll
M llvm/test/CodeGen/AMDGPU/fcanonicalize.f16.ll
M llvm/test/CodeGen/AMDGPU/fcanonicalize.ll
M llvm/test/CodeGen/AMDGPU/fceil.ll
M llvm/test/CodeGen/AMDGPU/fceil64.ll
M llvm/test/CodeGen/AMDGPU/fcmp.f16.ll
M llvm/test/CodeGen/AMDGPU/fcmp64.ll
M llvm/test/CodeGen/AMDGPU/fconst64.ll
M llvm/test/CodeGen/AMDGPU/fdiv.f16.ll
M llvm/test/CodeGen/AMDGPU/fdiv.f64.ll
M llvm/test/CodeGen/AMDGPU/fdot2.ll
M llvm/test/CodeGen/AMDGPU/fence-barrier.ll
M llvm/test/CodeGen/AMDGPU/fence-lds-read2-write2.ll
M llvm/test/CodeGen/AMDGPU/ffloor.f64.ll
M llvm/test/CodeGen/AMDGPU/ffloor.ll
A llvm/test/CodeGen/AMDGPU/finalizebundle.mir
M llvm/test/CodeGen/AMDGPU/fix-frame-ptr-reg-copy-livein.ll
M llvm/test/CodeGen/AMDGPU/fix-frame-reg-in-custom-csr-spills.ll
M llvm/test/CodeGen/AMDGPU/fix-wwm-vgpr-copy.ll
M llvm/test/CodeGen/AMDGPU/flat-atomic-fadd.f32.ll
M llvm/test/CodeGen/AMDGPU/flat-atomic-fadd.f64.ll
M llvm/test/CodeGen/AMDGPU/flat-offset-bug.ll
M llvm/test/CodeGen/AMDGPU/flat-saddr-atomics.ll
M llvm/test/CodeGen/AMDGPU/flat-saddr-load.ll
M llvm/test/CodeGen/AMDGPU/flat-scratch-i8-i16.ll
M llvm/test/CodeGen/AMDGPU/flat-scratch-svs.ll
M llvm/test/CodeGen/AMDGPU/fma-combine.ll
M llvm/test/CodeGen/AMDGPU/fma.f16.ll
M llvm/test/CodeGen/AMDGPU/fma.f64.ll
M llvm/test/CodeGen/AMDGPU/fma.ll
M llvm/test/CodeGen/AMDGPU/fmac.sdwa.ll
M llvm/test/CodeGen/AMDGPU/fmax3.f64.ll
M llvm/test/CodeGen/AMDGPU/fmax3.ll
M llvm/test/CodeGen/AMDGPU/fmax_legacy.f16.ll
M llvm/test/CodeGen/AMDGPU/fmax_legacy.ll
A llvm/test/CodeGen/AMDGPU/fmaximum3.v2f16.ll
M llvm/test/CodeGen/AMDGPU/fmed3.ll
M llvm/test/CodeGen/AMDGPU/fmin3.ll
M llvm/test/CodeGen/AMDGPU/fmin_legacy.f16.ll
M llvm/test/CodeGen/AMDGPU/fmin_legacy.ll
A llvm/test/CodeGen/AMDGPU/fminimum3.v2f16.ll
M llvm/test/CodeGen/AMDGPU/fmul-2-combine-multi-use.ll
M llvm/test/CodeGen/AMDGPU/fmul.f16.ll
M llvm/test/CodeGen/AMDGPU/fmul64.ll
M llvm/test/CodeGen/AMDGPU/fmuladd.f16.ll
M llvm/test/CodeGen/AMDGPU/fmuladd.f32.ll
M llvm/test/CodeGen/AMDGPU/fmuladd.f64.ll
M llvm/test/CodeGen/AMDGPU/fmuladd.v2f16.ll
M llvm/test/CodeGen/AMDGPU/fnearbyint.ll
M llvm/test/CodeGen/AMDGPU/fneg-combines-gfx1200.ll
M llvm/test/CodeGen/AMDGPU/fneg-combines.si.ll
M llvm/test/CodeGen/AMDGPU/fneg-fabs.f16.ll
M llvm/test/CodeGen/AMDGPU/fneg.f16.ll
M llvm/test/CodeGen/AMDGPU/fneg.f64.ll
M llvm/test/CodeGen/AMDGPU/fold-fabs.ll
M llvm/test/CodeGen/AMDGPU/fold-fmaak-bug.ll
M llvm/test/CodeGen/AMDGPU/fold-fmul-to-neg-abs.ll
M llvm/test/CodeGen/AMDGPU/fold-int-pow2-with-fmul-or-fdiv.ll
M llvm/test/CodeGen/AMDGPU/fp-classify.ll
M llvm/test/CodeGen/AMDGPU/fp-min-max-buffer-atomics.ll
M llvm/test/CodeGen/AMDGPU/fp-min-max-buffer-ptr-atomics.ll
M llvm/test/CodeGen/AMDGPU/fp-min-max-image-atomics.ll
M llvm/test/CodeGen/AMDGPU/fp-min-max-num-flat-atomics.ll
M llvm/test/CodeGen/AMDGPU/fp-min-max-num-global-atomics.ll
M llvm/test/CodeGen/AMDGPU/fp16_to_fp32.ll
M llvm/test/CodeGen/AMDGPU/fp16_to_fp64.ll
M llvm/test/CodeGen/AMDGPU/fp32_to_fp16.ll
M llvm/test/CodeGen/AMDGPU/fp64-min-max-buffer-atomics.ll
M llvm/test/CodeGen/AMDGPU/fp64-min-max-buffer-ptr-atomics.ll
M llvm/test/CodeGen/AMDGPU/fp_to_sint.f64.ll
M llvm/test/CodeGen/AMDGPU/fp_to_sint.ll
M llvm/test/CodeGen/AMDGPU/fp_to_uint.f64.ll
M llvm/test/CodeGen/AMDGPU/fp_to_uint.ll
M llvm/test/CodeGen/AMDGPU/fpext-free.ll
M llvm/test/CodeGen/AMDGPU/fpext.f16.ll
M llvm/test/CodeGen/AMDGPU/fpext.ll
M llvm/test/CodeGen/AMDGPU/fptosi.f16.ll
M llvm/test/CodeGen/AMDGPU/fptoui.f16.ll
M llvm/test/CodeGen/AMDGPU/fptrunc.f16.ll
M llvm/test/CodeGen/AMDGPU/fptrunc.ll
M llvm/test/CodeGen/AMDGPU/fract.f64.ll
M llvm/test/CodeGen/AMDGPU/fract.ll
M llvm/test/CodeGen/AMDGPU/frame-index-elimination.ll
M llvm/test/CodeGen/AMDGPU/frame-setup-without-sgpr-to-vgpr-spills.ll
M llvm/test/CodeGen/AMDGPU/frem.ll
M llvm/test/CodeGen/AMDGPU/fshl.ll
M llvm/test/CodeGen/AMDGPU/fshr.ll
M llvm/test/CodeGen/AMDGPU/fsqrt.f64.ll
M llvm/test/CodeGen/AMDGPU/fsub.f16.ll
M llvm/test/CodeGen/AMDGPU/fsub.ll
M llvm/test/CodeGen/AMDGPU/fsub64.ll
M llvm/test/CodeGen/AMDGPU/function-args.ll
M llvm/test/CodeGen/AMDGPU/function-returns.ll
M llvm/test/CodeGen/AMDGPU/fused-bitlogic.ll
M llvm/test/CodeGen/AMDGPU/gds-allocation.ll
M llvm/test/CodeGen/AMDGPU/gds-atomic.ll
M llvm/test/CodeGen/AMDGPU/gep-address-space.ll
M llvm/test/CodeGen/AMDGPU/gfx-call-non-gfx-func.ll
M llvm/test/CodeGen/AMDGPU/gfx-callable-argument-types.ll
M llvm/test/CodeGen/AMDGPU/gfx-callable-preserved-registers.ll
M llvm/test/CodeGen/AMDGPU/gfx-callable-return-types.ll
M llvm/test/CodeGen/AMDGPU/gfx10-vop-literal.ll
M llvm/test/CodeGen/AMDGPU/gfx12_scalar_subword_loads.ll
M llvm/test/CodeGen/AMDGPU/gfx90a-enc.ll
M llvm/test/CodeGen/AMDGPU/global-address.ll
M llvm/test/CodeGen/AMDGPU/global-atomic-fadd.f32-no-rtn.ll
M llvm/test/CodeGen/AMDGPU/global-atomic-fadd.f32-rtn.ll
M llvm/test/CodeGen/AMDGPU/global-constant.ll
M llvm/test/CodeGen/AMDGPU/global-directive.ll
M llvm/test/CodeGen/AMDGPU/global-extload-i16.ll
M llvm/test/CodeGen/AMDGPU/global-i16-load-store.ll
M llvm/test/CodeGen/AMDGPU/global-load-saddr-to-vaddr.ll
M llvm/test/CodeGen/AMDGPU/global-load-xcnt.ll
M llvm/test/CodeGen/AMDGPU/global_atomics.ll
M llvm/test/CodeGen/AMDGPU/global_atomics_i32_system.ll
M llvm/test/CodeGen/AMDGPU/global_atomics_i64.ll
M llvm/test/CodeGen/AMDGPU/global_atomics_i64_system.ll
M llvm/test/CodeGen/AMDGPU/global_atomics_scan_fmax.ll
M llvm/test/CodeGen/AMDGPU/global_atomics_scan_fmin.ll
M llvm/test/CodeGen/AMDGPU/global_atomics_scan_fsub.ll
M llvm/test/CodeGen/AMDGPU/global_smrd.ll
M llvm/test/CodeGen/AMDGPU/global_smrd_cfg.ll
M llvm/test/CodeGen/AMDGPU/gv-const-addrspace.ll
M llvm/test/CodeGen/AMDGPU/half.ll
M llvm/test/CodeGen/AMDGPU/hip.extern.shared.array.ll
M llvm/test/CodeGen/AMDGPU/hoist-cond.ll
M llvm/test/CodeGen/AMDGPU/hsa-fp-mode.ll
M llvm/test/CodeGen/AMDGPU/hsa-metadata-agpr-register-count.ll
M llvm/test/CodeGen/AMDGPU/huge-private-buffer.ll
M llvm/test/CodeGen/AMDGPU/i1-copy-from-loop.ll
M llvm/test/CodeGen/AMDGPU/i1-copy-implicit-def.ll
M llvm/test/CodeGen/AMDGPU/i1-copy-phi-uniform-branch.ll
M llvm/test/CodeGen/AMDGPU/i1-copy-phi.ll
M llvm/test/CodeGen/AMDGPU/icmp.i16.ll
M llvm/test/CodeGen/AMDGPU/icmp64.ll
M llvm/test/CodeGen/AMDGPU/idemponent-atomics.ll
M llvm/test/CodeGen/AMDGPU/idiv-licm.ll
M llvm/test/CodeGen/AMDGPU/image-load-d16-tfe.ll
M llvm/test/CodeGen/AMDGPU/image-sample-waterfall.ll
M llvm/test/CodeGen/AMDGPU/image-schedule.ll
M llvm/test/CodeGen/AMDGPU/img-nouse-adjust.ll
M llvm/test/CodeGen/AMDGPU/imm.ll
M llvm/test/CodeGen/AMDGPU/imm16.ll
M llvm/test/CodeGen/AMDGPU/immv216.ll
M llvm/test/CodeGen/AMDGPU/implicit-def-muse.ll
M llvm/test/CodeGen/AMDGPU/indirect-addressing-si-gfx9.ll
M llvm/test/CodeGen/AMDGPU/indirect-addressing-term.ll
M llvm/test/CodeGen/AMDGPU/indirect-call.ll
M llvm/test/CodeGen/AMDGPU/indirect-private-64.ll
M llvm/test/CodeGen/AMDGPU/infinite-loop.ll
M llvm/test/CodeGen/AMDGPU/inline-asm-reserved-regs.ll
M llvm/test/CodeGen/AMDGPU/inline-asm.ll
M llvm/test/CodeGen/AMDGPU/inline-calls.ll
M llvm/test/CodeGen/AMDGPU/inline-constraints.ll
M llvm/test/CodeGen/AMDGPU/inlineasm-16.ll
M llvm/test/CodeGen/AMDGPU/inlineasm-illegal-type.ll
M llvm/test/CodeGen/AMDGPU/inlineasm-packed.ll
M llvm/test/CodeGen/AMDGPU/inlineasm-v16.ll
M llvm/test/CodeGen/AMDGPU/insert-delay-alu-bug.ll
M llvm/test/CodeGen/AMDGPU/insert-subvector-unused-scratch.ll
M llvm/test/CodeGen/AMDGPU/insert-waitcnts-crash.ll
M llvm/test/CodeGen/AMDGPU/insert_subreg.ll
M llvm/test/CodeGen/AMDGPU/insert_vector_elt.v2bf16.ll
M llvm/test/CodeGen/AMDGPU/insert_vector_elt.v2i16.ll
M llvm/test/CodeGen/AMDGPU/insert_vector_elt.v2i16.subtest-nosaddr.ll
M llvm/test/CodeGen/AMDGPU/insert_vector_elt.v2i16.subtest-saddr.ll
M llvm/test/CodeGen/AMDGPU/invariant-load-no-alias-store.ll
M llvm/test/CodeGen/AMDGPU/ipra-return-address-save-restore.ll
M llvm/test/CodeGen/AMDGPU/ipra.ll
M llvm/test/CodeGen/AMDGPU/irtranslator-whole-wave-functions.ll
M llvm/test/CodeGen/AMDGPU/isel-amdgcn-cs-chain-intrinsic-w32.ll
M llvm/test/CodeGen/AMDGPU/isel-amdgcn-cs-chain-intrinsic-w64.ll
M llvm/test/CodeGen/AMDGPU/isel-amdgpu-cs-chain-cc.ll
M llvm/test/CodeGen/AMDGPU/isel-amdgpu-cs-chain-intrinsic-dyn-vgpr-w32.ll
M llvm/test/CodeGen/AMDGPU/isel-amdgpu-cs-chain-preserve-cc.ll
M llvm/test/CodeGen/AMDGPU/issue92561-restore-undef-scc-verifier-error.ll
M llvm/test/CodeGen/AMDGPU/issue98474-need-live-out-undef-subregister-def.ll
M llvm/test/CodeGen/AMDGPU/kernarg-stack-alignment.ll
M llvm/test/CodeGen/AMDGPU/kernel-args.ll
M llvm/test/CodeGen/AMDGPU/kernel-argument-dag-lowering.ll
M llvm/test/CodeGen/AMDGPU/kernel-vgpr-spill-mubuf-with-voffset.ll
M llvm/test/CodeGen/AMDGPU/kill-infinite-loop.ll
M llvm/test/CodeGen/AMDGPU/known-never-nan.ll
M llvm/test/CodeGen/AMDGPU/known-never-snan.ll
M llvm/test/CodeGen/AMDGPU/lds-bounds.ll
M llvm/test/CodeGen/AMDGPU/lds-frame-extern.ll
M llvm/test/CodeGen/AMDGPU/lds-global-non-entry-func.ll
M llvm/test/CodeGen/AMDGPU/lds-m0-init-in-loop.ll
M llvm/test/CodeGen/AMDGPU/lds-misaligned-bug.ll
M llvm/test/CodeGen/AMDGPU/lds-oqap-crash.ll
M llvm/test/CodeGen/AMDGPU/lds-output-queue.ll
M llvm/test/CodeGen/AMDGPU/lds-relocs.ll
M llvm/test/CodeGen/AMDGPU/lds-size-hsa-gfx950.ll
M llvm/test/CodeGen/AMDGPU/lds-size-pal-gfx950.ll
M llvm/test/CodeGen/AMDGPU/lds-zero-initializer.ll
M llvm/test/CodeGen/AMDGPU/legalize-amdgcn.raw.buffer.load.format.f16.ll
M llvm/test/CodeGen/AMDGPU/legalize-amdgcn.raw.buffer.load.format.ll
M llvm/test/CodeGen/AMDGPU/legalize-amdgcn.raw.buffer.load.ll
M llvm/test/CodeGen/AMDGPU/legalize-amdgcn.raw.buffer.store.format.f16.ll
M llvm/test/CodeGen/AMDGPU/legalize-amdgcn.raw.buffer.store.format.f32.ll
M llvm/test/CodeGen/AMDGPU/legalize-amdgcn.raw.buffer.store.ll
M llvm/test/CodeGen/AMDGPU/legalize-amdgcn.raw.ptr.buffer.load.format.f16.ll
M llvm/test/CodeGen/AMDGPU/legalize-amdgcn.raw.ptr.buffer.load.format.ll
M llvm/test/CodeGen/AMDGPU/legalize-amdgcn.raw.ptr.buffer.load.ll
M llvm/test/CodeGen/AMDGPU/legalize-amdgcn.raw.ptr.buffer.store.format.f16.ll
M llvm/test/CodeGen/AMDGPU/legalize-amdgcn.raw.ptr.buffer.store.format.f32.ll
M llvm/test/CodeGen/AMDGPU/legalize-amdgcn.raw.ptr.buffer.store.ll
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M llvm/test/CodeGen/AMDGPU/legalize-amdgcn.raw.ptr.tbuffer.load.ll
M llvm/test/CodeGen/AMDGPU/legalize-amdgcn.raw.ptr.tbuffer.store.f16.ll
M llvm/test/CodeGen/AMDGPU/legalize-amdgcn.raw.ptr.tbuffer.store.ll
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M llvm/test/CodeGen/AMDGPU/legalize-amdgcn.raw.tbuffer.load.ll
M llvm/test/CodeGen/AMDGPU/legalize-amdgcn.raw.tbuffer.store.f16.ll
M llvm/test/CodeGen/AMDGPU/legalize-amdgcn.raw.tbuffer.store.ll
M llvm/test/CodeGen/AMDGPU/legalize-fp-load-invariant.ll
M llvm/test/CodeGen/AMDGPU/legalize-soffset-mbuf.ll
M llvm/test/CodeGen/AMDGPU/literal-constant-like-operand-instruction-size.ll
M llvm/test/CodeGen/AMDGPU/literal64.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.alignbyte.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.atomic.cond.sub.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.atomic.dec.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.atomic.inc.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.bitop3.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.bitreplicate.ll
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M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.buffer.load.dwordx3.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.buffer.store.dwordx3.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.class.f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.class.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cos.f16.ll
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M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.pknorm.u16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.pkrtz.ll
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M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.scalef32.sr.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.scalef32.sr.pk.gfx950.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.scalef32.sr.pk.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.dispatch.ptr.ll
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M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.div.fixup.ll
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M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.div.scale.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.dot4.f32.ll
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M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.ds.bpermute.fi.b32.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.ds.bpermute.ll
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M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.ds.consume.ll
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M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.ds.gws.barrier.ll
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M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.ds.gws.sema.p.ll
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M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.ds.ordered.add.gfx10.ll
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M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.ds.ordered.add.ll
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M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.ds.swizzle.ll
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M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.fdot2.f16.f16.ll
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M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.global.load.lds.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.global.load.tr-w32.ll
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M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.groupstaticsize.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.icmp.w32.ll
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M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.iglp.opt.ll
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M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.ptr.buffer.load.format.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.ptr.buffer.load.lds.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.ptr.buffer.load.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.ptr.buffer.store.format.d16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.ptr.buffer.store.format.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.ptr.buffer.store.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.ptr.tbuffer.load.d16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.ptr.tbuffer.load.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.ptr.tbuffer.store.d16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.ptr.tbuffer.store.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.tbuffer.load.d16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.tbuffer.load.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.tbuffer.store.d16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.tbuffer.store.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.rcp.f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.rcp.legacy.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.rcp.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.readfirstlane.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.readfirstlane.m0.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.readfirstlane.ptr.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.readlane.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.readlane.ptr.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.rsq.clamp.ll
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M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.rsq.legacy.ll
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M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.s.barrier.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.s.buffer.load.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.s.decperflevel.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.s.get.waveid.in.workgroup.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.s.getpc.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.s.getreg.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.s.incperflevel.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.s.memrealtime.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.s.memtime.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.s.nop.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.s.sethalt.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.s.setprio.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.s.setreg.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.s.sleep.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.s.sleep.var.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.s.ttracedata.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.s.wait.event.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.s.wait.gfx12.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.s.waitcnt.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.sad.hi.u8.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.sad.u16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.sad.u8.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.sbfe.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.sched.barrier.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.sched.group.barrier.gfx11.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.sched.group.barrier.iterative.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.sched.group.barrier.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.sdot2.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.sdot4.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.sdot8.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.sendmsg.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.sendmsg.rtn.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.set.inactive.chain.arg.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.set.inactive.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.sffbh.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.sin.f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.sin.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.softwqm.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.atomic.buffer.load.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.buffer.atomic.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.buffer.load.format.d16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.buffer.load.format.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.buffer.load.format.v3f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.buffer.load.lds.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.buffer.load.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.buffer.load.tfe.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.buffer.store.format.d16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.buffer.store.format.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.buffer.store.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.atomic.buffer.load.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.buffer.atomic.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.buffer.load.format.d16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.buffer.load.format.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.buffer.load.format.v3f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.buffer.load.lds.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.buffer.load.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.buffer.store.format.d16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.buffer.store.format.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.buffer.store.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.tbuffer.load.d16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.tbuffer.load.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.tbuffer.store.d16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.tbuffer.store.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.tbuffer.load.d16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.tbuffer.load.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.tbuffer.store.d16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.tbuffer.store.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.sudot4.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.sudot8.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.tbuffer.load.dwordx3.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.tbuffer.store.dwordx3.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.trig.preop.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.ubfe.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.udot2.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.udot4.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.udot8.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.update.dpp.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.waitcnt.out.order.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.wave.barrier.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.wave.id.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.wavefrontsize.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.wmma_32.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.wmma_64.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.wqm.demote.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.wqm.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.wqm.vote.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.writelane.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.writelane.ptr.ll
M llvm/test/CodeGen/AMDGPU/llvm.ceil.f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.cos.bf16.ll
M llvm/test/CodeGen/AMDGPU/llvm.cos.f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.dbg.value.ll
M llvm/test/CodeGen/AMDGPU/llvm.floor.f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.fma.f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.fmuladd.f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.is.fpclass.ll
M llvm/test/CodeGen/AMDGPU/llvm.maxnum.f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.memcpy.ll
M llvm/test/CodeGen/AMDGPU/llvm.minnum.f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.mulo.ll
M llvm/test/CodeGen/AMDGPU/llvm.prefetch.ll
M llvm/test/CodeGen/AMDGPU/llvm.r600.dot4.ll
M llvm/test/CodeGen/AMDGPU/llvm.r600.recipsqrt.clamped.ll
M llvm/test/CodeGen/AMDGPU/llvm.r600.recipsqrt.ieee.ll
M llvm/test/CodeGen/AMDGPU/llvm.rint.f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.rint.f64.ll
M llvm/test/CodeGen/AMDGPU/llvm.rint.ll
M llvm/test/CodeGen/AMDGPU/llvm.sin.bf16.ll
M llvm/test/CodeGen/AMDGPU/llvm.sin.f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.sin.ll
M llvm/test/CodeGen/AMDGPU/llvm.sqrt.f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.trunc.f16.ll
M llvm/test/CodeGen/AMDGPU/load-constant-f32.ll
M llvm/test/CodeGen/AMDGPU/load-constant-f64.ll
M llvm/test/CodeGen/AMDGPU/load-constant-i1.ll
M llvm/test/CodeGen/AMDGPU/load-constant-i16.ll
M llvm/test/CodeGen/AMDGPU/load-constant-i32.ll
M llvm/test/CodeGen/AMDGPU/load-constant-i64.ll
M llvm/test/CodeGen/AMDGPU/load-constant-i8.ll
M llvm/test/CodeGen/AMDGPU/load-hi16.ll
M llvm/test/CodeGen/AMDGPU/load-lo16.ll
M llvm/test/CodeGen/AMDGPU/load-local-f32.ll
M llvm/test/CodeGen/AMDGPU/load-local-f64.ll
M llvm/test/CodeGen/AMDGPU/load-local-i1.ll
M llvm/test/CodeGen/AMDGPU/load-local-i16.ll
M llvm/test/CodeGen/AMDGPU/load-local-i32.ll
M llvm/test/CodeGen/AMDGPU/load-local-i64.ll
M llvm/test/CodeGen/AMDGPU/load-local-i8.ll
M llvm/test/CodeGen/AMDGPU/load-local-redundant-copies.ll
M llvm/test/CodeGen/AMDGPU/load-local.128.ll
M llvm/test/CodeGen/AMDGPU/load-local.96.ll
M llvm/test/CodeGen/AMDGPU/load-range-metadata-assert.ll
M llvm/test/CodeGen/AMDGPU/load-select-ptr.ll
M llvm/test/CodeGen/AMDGPU/load-weird-sizes.ll
M llvm/test/CodeGen/AMDGPU/local-64.ll
M llvm/test/CodeGen/AMDGPU/local-atomics.ll
M llvm/test/CodeGen/AMDGPU/local-atomics64.ll
M llvm/test/CodeGen/AMDGPU/local-memory.amdgcn.ll
M llvm/test/CodeGen/AMDGPU/local-memory.ll
M llvm/test/CodeGen/AMDGPU/local-stack-slot-offset.ll
M llvm/test/CodeGen/AMDGPU/long-branch-reserve-register.ll
M llvm/test/CodeGen/AMDGPU/loop-idiom.ll
M llvm/test/CodeGen/AMDGPU/loop-live-out-copy-undef-subrange.ll
M llvm/test/CodeGen/AMDGPU/loop-prefetch.ll
M llvm/test/CodeGen/AMDGPU/loop_break.ll
M llvm/test/CodeGen/AMDGPU/loop_exit_with_xor.ll
M llvm/test/CodeGen/AMDGPU/lower-buffer-fat-pointers-nontemporal-metadata.ll
M llvm/test/CodeGen/AMDGPU/lower-module-lds-offsets.ll
M llvm/test/CodeGen/AMDGPU/lower-module-lds-via-hybrid.ll
M llvm/test/CodeGen/AMDGPU/lower-module-lds-via-table.ll
M llvm/test/CodeGen/AMDGPU/lower-work-group-id-intrinsics-hsa.ll
M llvm/test/CodeGen/AMDGPU/lower-work-group-id-intrinsics-pal.ll
M llvm/test/CodeGen/AMDGPU/lshl-add-u64.ll
M llvm/test/CodeGen/AMDGPU/lshl64-to-32.ll
M llvm/test/CodeGen/AMDGPU/lshr.v2i16.ll
M llvm/test/CodeGen/AMDGPU/mad-combine.ll
A llvm/test/CodeGen/AMDGPU/mad-mix-bf16.ll
A llvm/test/CodeGen/AMDGPU/mad-mix-hi-bf16.ll
M llvm/test/CodeGen/AMDGPU/mad-mix-hi.ll
A llvm/test/CodeGen/AMDGPU/mad-mix-lo-bf16.ll
M llvm/test/CodeGen/AMDGPU/mad-mix-lo.ll
M llvm/test/CodeGen/AMDGPU/mad-mix.ll
M llvm/test/CodeGen/AMDGPU/mad.u16.ll
M llvm/test/CodeGen/AMDGPU/mad24-get-global-id.ll
M llvm/test/CodeGen/AMDGPU/mad_64_32.ll
M llvm/test/CodeGen/AMDGPU/mad_int24.ll
M llvm/test/CodeGen/AMDGPU/mad_u64_u32.ll
M llvm/test/CodeGen/AMDGPU/mad_uint24.ll
M llvm/test/CodeGen/AMDGPU/madak.ll
M llvm/test/CodeGen/AMDGPU/madmk.ll
M llvm/test/CodeGen/AMDGPU/mai-inline.ll
M llvm/test/CodeGen/AMDGPU/match-perm-extract-vector-elt-bug.ll
M llvm/test/CodeGen/AMDGPU/max-sgprs.ll
M llvm/test/CodeGen/AMDGPU/max.i16.ll
M llvm/test/CodeGen/AMDGPU/max.ll
M llvm/test/CodeGen/AMDGPU/max3.ll
M llvm/test/CodeGen/AMDGPU/med3-no-simplify.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-atomic-insert-end.mir
M llvm/test/CodeGen/AMDGPU/memory-legalizer-fence-mmra-global.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-fence-mmra-local.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-multiple-mem-operands-atomics.mir
M llvm/test/CodeGen/AMDGPU/memory_clause.ll
M llvm/test/CodeGen/AMDGPU/merge-out-of-order-ldst.ll
M llvm/test/CodeGen/AMDGPU/merge-store-crash.ll
M llvm/test/CodeGen/AMDGPU/merge-store-usedef.ll
M llvm/test/CodeGen/AMDGPU/merge-stores.ll
M llvm/test/CodeGen/AMDGPU/mesa3d.ll
M llvm/test/CodeGen/AMDGPU/mesa_regression.ll
M llvm/test/CodeGen/AMDGPU/mfma-bf16-vgpr-cd-select.ll
M llvm/test/CodeGen/AMDGPU/mfma-cd-select.ll
M llvm/test/CodeGen/AMDGPU/mfma-loop.ll
M llvm/test/CodeGen/AMDGPU/mfma-no-register-aliasing.ll
M llvm/test/CodeGen/AMDGPU/mfma-vgpr-cd-select-gfx942.ll
M llvm/test/CodeGen/AMDGPU/mfma-vgpr-cd-select.ll
M llvm/test/CodeGen/AMDGPU/min-waves-per-eu-not-respected.ll
M llvm/test/CodeGen/AMDGPU/min.ll
M llvm/test/CodeGen/AMDGPU/min3.ll
M llvm/test/CodeGen/AMDGPU/minimummaximum.ll
M llvm/test/CodeGen/AMDGPU/minmax.ll
M llvm/test/CodeGen/AMDGPU/missing-store.ll
M llvm/test/CodeGen/AMDGPU/mixed-vmem-types.ll
M llvm/test/CodeGen/AMDGPU/mixed-wave32-wave64.ll
M llvm/test/CodeGen/AMDGPU/mixed_wave32_wave64.ll
M llvm/test/CodeGen/AMDGPU/module-lds-false-sharing.ll
M llvm/test/CodeGen/AMDGPU/move-to-valu-addsubu64.ll
M llvm/test/CodeGen/AMDGPU/move-to-valu-atomicrmw-system.ll
M llvm/test/CodeGen/AMDGPU/move-to-valu-atomicrmw.ll
M llvm/test/CodeGen/AMDGPU/move-to-valu-ctlz-cttz.ll
M llvm/test/CodeGen/AMDGPU/move-to-valu-pseudo-scalar-trans-f16-fake16.ll
M llvm/test/CodeGen/AMDGPU/move-to-valu-pseudo-scalar-trans-f16-true16.ll
M llvm/test/CodeGen/AMDGPU/move-to-valu-pseudo-scalar-trans.ll
M llvm/test/CodeGen/AMDGPU/move-to-valu-vimage-vsample.ll
M llvm/test/CodeGen/AMDGPU/move-to-valu-worklist.ll
M llvm/test/CodeGen/AMDGPU/movreld-bug.ll
M llvm/test/CodeGen/AMDGPU/mubuf-legalize-operands-non-ptr-intrinsics.ll
M llvm/test/CodeGen/AMDGPU/mubuf-legalize-operands.ll
M llvm/test/CodeGen/AMDGPU/mubuf-shader-vgpr-non-ptr-intrinsics.ll
M llvm/test/CodeGen/AMDGPU/mubuf-shader-vgpr.ll
M llvm/test/CodeGen/AMDGPU/mubuf.ll
M llvm/test/CodeGen/AMDGPU/mul.i16.ll
M llvm/test/CodeGen/AMDGPU/mul.ll
M llvm/test/CodeGen/AMDGPU/mul24-pass-ordering.ll
M llvm/test/CodeGen/AMDGPU/mul_int24.ll
M llvm/test/CodeGen/AMDGPU/mul_uint24-amdgcn.ll
M llvm/test/CodeGen/AMDGPU/multi-divergent-exit-region.ll
M llvm/test/CodeGen/AMDGPU/multilevel-break.ll
M llvm/test/CodeGen/AMDGPU/nand.ll
M llvm/test/CodeGen/AMDGPU/need-fp-from-vgpr-spills.ll
M llvm/test/CodeGen/AMDGPU/nested-calls.ll
M llvm/test/CodeGen/AMDGPU/nested-loop-conditions.ll
M llvm/test/CodeGen/AMDGPU/no-dup-inst-prefetch.ll
M llvm/test/CodeGen/AMDGPU/no-shrink-extloads.ll
M llvm/test/CodeGen/AMDGPU/no-source-locations-in-prologue.ll
M llvm/test/CodeGen/AMDGPU/noclobber-barrier.ll
M llvm/test/CodeGen/AMDGPU/non-entry-alloca.ll
M llvm/test/CodeGen/AMDGPU/noop-shader-O0.ll
M llvm/test/CodeGen/AMDGPU/nor.ll
M llvm/test/CodeGen/AMDGPU/nsa-reassign.ll
M llvm/test/CodeGen/AMDGPU/nullptr.ll
M llvm/test/CodeGen/AMDGPU/offset-split-flat.ll
M llvm/test/CodeGen/AMDGPU/offset-split-global.ll
M llvm/test/CodeGen/AMDGPU/omod.ll
M llvm/test/CodeGen/AMDGPU/opencl-image-metadata.ll
M llvm/test/CodeGen/AMDGPU/operand-folding.ll
M llvm/test/CodeGen/AMDGPU/operand-spacing.ll
M llvm/test/CodeGen/AMDGPU/optimize-compare.ll
M llvm/test/CodeGen/AMDGPU/optimize-negated-cond.ll
M llvm/test/CodeGen/AMDGPU/or.ll
M llvm/test/CodeGen/AMDGPU/or3.ll
M llvm/test/CodeGen/AMDGPU/overlapping-tuple-copy-implicit-op-failure.ll
M llvm/test/CodeGen/AMDGPU/pack.v2f16.ll
M llvm/test/CodeGen/AMDGPU/pack.v2i16.ll
M llvm/test/CodeGen/AMDGPU/packed-fp32.ll
M llvm/test/CodeGen/AMDGPU/pal-metadata-3.0-callable-dvgpr.ll
M llvm/test/CodeGen/AMDGPU/pal-metadata-3.0-callable.ll
M llvm/test/CodeGen/AMDGPU/parallelandifcollapse.ll
M llvm/test/CodeGen/AMDGPU/partial-regcopy-and-spill-missed-at-regalloc.ll
M llvm/test/CodeGen/AMDGPU/partial-sgpr-to-vgpr-spills.ll
M llvm/test/CodeGen/AMDGPU/partial-shift-shrink.ll
M llvm/test/CodeGen/AMDGPU/partially-dead-super-register-immediate.ll
M llvm/test/CodeGen/AMDGPU/permlane16_opsel.ll
M llvm/test/CodeGen/AMDGPU/permute.ll
M llvm/test/CodeGen/AMDGPU/permute_i8.ll
M llvm/test/CodeGen/AMDGPU/pk_max_f16_literal.ll
M llvm/test/CodeGen/AMDGPU/post-ra-soft-clause-dbg-info.ll
M llvm/test/CodeGen/AMDGPU/preload-kernargs.ll
M llvm/test/CodeGen/AMDGPU/preserve-hi16.ll
M llvm/test/CodeGen/AMDGPU/preserve-user-waitcnt.ll
M llvm/test/CodeGen/AMDGPU/preserve-wwm-copy-dst-reg.ll
M llvm/test/CodeGen/AMDGPU/private-access-no-objects.ll
M llvm/test/CodeGen/AMDGPU/prologue-epilogue-markers.ll
M llvm/test/CodeGen/AMDGPU/promote-alloca-stored-pointer-value.ll
M llvm/test/CodeGen/AMDGPU/promote-alloca-vector-to-vector.ll
M llvm/test/CodeGen/AMDGPU/promote-constOffset-to-imm.ll
M llvm/test/CodeGen/AMDGPU/promote-vect3-load.ll
M llvm/test/CodeGen/AMDGPU/propagate-attributes-bitcast-function.ll
M llvm/test/CodeGen/AMDGPU/ps-shader-arg-count.ll
M llvm/test/CodeGen/AMDGPU/ptr-buffer-alias-scheduling.ll
M llvm/test/CodeGen/AMDGPU/r600-constant-array-fixup.ll
M llvm/test/CodeGen/AMDGPU/r600.bitcast.ll
M llvm/test/CodeGen/AMDGPU/r600.extract-lowbits.ll
M llvm/test/CodeGen/AMDGPU/r600.global_atomics.ll
M llvm/test/CodeGen/AMDGPU/r600.sub.ll
M llvm/test/CodeGen/AMDGPU/r600.work-item-intrinsics.ll
M llvm/test/CodeGen/AMDGPU/ran-out-of-registers-error-all-regs-reserved.ll
M llvm/test/CodeGen/AMDGPU/rcp_iflag.ll
M llvm/test/CodeGen/AMDGPU/read-register-invalid-subtarget.ll
M llvm/test/CodeGen/AMDGPU/read-register-invalid-type-i32.ll
M llvm/test/CodeGen/AMDGPU/read-register-invalid-type-i64.ll
M llvm/test/CodeGen/AMDGPU/read_register.ll
M llvm/test/CodeGen/AMDGPU/readcyclecounter.ll
M llvm/test/CodeGen/AMDGPU/readsteadycounter.ll
M llvm/test/CodeGen/AMDGPU/reassoc-scalar.ll
M llvm/test/CodeGen/AMDGPU/recursion.ll
M llvm/test/CodeGen/AMDGPU/reduce-build-vec-ext-to-ext-build-vec.ll
M llvm/test/CodeGen/AMDGPU/reduce-load-width-alignment.ll
M llvm/test/CodeGen/AMDGPU/reduce-store-width-alignment.ll
M llvm/test/CodeGen/AMDGPU/reduction.ll
M llvm/test/CodeGen/AMDGPU/regalloc-illegal-eviction-assert.ll
M llvm/test/CodeGen/AMDGPU/register-count-comments.ll
M llvm/test/CodeGen/AMDGPU/register-killed-error-after-alloc-failure1.ll
M llvm/test/CodeGen/AMDGPU/reject-agpr-usage-before-gfx908.ll
M llvm/test/CodeGen/AMDGPU/rel32.ll
M llvm/test/CodeGen/AMDGPU/remaining-virtual-register-operands.ll
M llvm/test/CodeGen/AMDGPU/remat-fp64-constants.ll
M llvm/test/CodeGen/AMDGPU/remove-incompatible-extended-image-insts.ll
M llvm/test/CodeGen/AMDGPU/remove-incompatible-functions.ll
M llvm/test/CodeGen/AMDGPU/remove-incompatible-gws.ll
M llvm/test/CodeGen/AMDGPU/remove-incompatible-s-time.ll
M llvm/test/CodeGen/AMDGPU/remove-incompatible-wave32-feature.ll
M llvm/test/CodeGen/AMDGPU/rename-disconnected-bug.ll
M llvm/test/CodeGen/AMDGPU/resource-usage-pal.ll
M llvm/test/CodeGen/AMDGPU/ret.ll
M llvm/test/CodeGen/AMDGPU/ret_jump.ll
M llvm/test/CodeGen/AMDGPU/returnaddress.ll
M llvm/test/CodeGen/AMDGPU/rotate-add.ll
M llvm/test/CodeGen/AMDGPU/rotl.i64.ll
M llvm/test/CodeGen/AMDGPU/rotl.ll
M llvm/test/CodeGen/AMDGPU/rotr.i64.ll
M llvm/test/CodeGen/AMDGPU/rotr.ll
M llvm/test/CodeGen/AMDGPU/s-getpc-b64-remat.ll
M llvm/test/CodeGen/AMDGPU/s_addk_i32.ll
M llvm/test/CodeGen/AMDGPU/s_movk_i32.ll
M llvm/test/CodeGen/AMDGPU/s_mulk_i32.ll
M llvm/test/CodeGen/AMDGPU/sad.ll
M llvm/test/CodeGen/AMDGPU/saddo.ll
M llvm/test/CodeGen/AMDGPU/salu-to-valu.ll
M llvm/test/CodeGen/AMDGPU/save-fp.ll
M llvm/test/CodeGen/AMDGPU/scalar-branch-missing-and-exec.ll
M llvm/test/CodeGen/AMDGPU/scalar-float-sop1.ll
M llvm/test/CodeGen/AMDGPU/scalar-float-sop2.ll
M llvm/test/CodeGen/AMDGPU/scalar-float-sopc.ll
M llvm/test/CodeGen/AMDGPU/scalar_to_vector.ll
M llvm/test/CodeGen/AMDGPU/scalar_to_vector.v8i16.ll
M llvm/test/CodeGen/AMDGPU/scalar_to_vector_v2x16.ll
A llvm/test/CodeGen/AMDGPU/scale-offset-flat.ll
A llvm/test/CodeGen/AMDGPU/scale-offset-global.ll
A llvm/test/CodeGen/AMDGPU/scale-offset-scratch.ll
M llvm/test/CodeGen/AMDGPU/scc-clobbered-sgpr-to-vmem-spill.ll
M llvm/test/CodeGen/AMDGPU/sched-setprio.ll
M llvm/test/CodeGen/AMDGPU/schedule-avoid-spills.ll
M llvm/test/CodeGen/AMDGPU/schedule-fs-loop-nested-if.ll
M llvm/test/CodeGen/AMDGPU/schedule-fs-loop-nested.ll
M llvm/test/CodeGen/AMDGPU/schedule-fs-loop.ll
M llvm/test/CodeGen/AMDGPU/schedule-global-loads.ll
M llvm/test/CodeGen/AMDGPU/schedule-if-2.ll
M llvm/test/CodeGen/AMDGPU/schedule-if.ll
M llvm/test/CodeGen/AMDGPU/schedule-ilp.ll
M llvm/test/CodeGen/AMDGPU/schedule-kernel-arg-loads.ll
M llvm/test/CodeGen/AMDGPU/schedule-regpressure-lds.ll
M llvm/test/CodeGen/AMDGPU/schedule-regpressure-limit-clustering.ll
M llvm/test/CodeGen/AMDGPU/schedule-regpressure-limit.ll
M llvm/test/CodeGen/AMDGPU/schedule-regpressure-limit2.ll
M llvm/test/CodeGen/AMDGPU/schedule-regpressure-limit3.ll
M llvm/test/CodeGen/AMDGPU/schedule-regpressure-misched-max-waves.ll
M llvm/test/CodeGen/AMDGPU/schedule-relaxed-occupancy.ll
M llvm/test/CodeGen/AMDGPU/schedule-vs-if-nested-loop-failure.ll
M llvm/test/CodeGen/AMDGPU/schedule-xdl-resource.ll
M llvm/test/CodeGen/AMDGPU/scratch-buffer.ll
M llvm/test/CodeGen/AMDGPU/scratch-pointer-sink.ll
M llvm/test/CodeGen/AMDGPU/scratch-simple.ll
M llvm/test/CodeGen/AMDGPU/sdag-print-divergence.ll
M llvm/test/CodeGen/AMDGPU/sdiv64.ll
M llvm/test/CodeGen/AMDGPU/sdwa-op64-test.ll
M llvm/test/CodeGen/AMDGPU/sdwa-peephole.ll
M llvm/test/CodeGen/AMDGPU/select-constant-cttz.ll
M llvm/test/CodeGen/AMDGPU/select-fabs-fneg-extract-legacy.ll
M llvm/test/CodeGen/AMDGPU/select-fabs-fneg-extract.ll
M llvm/test/CodeGen/AMDGPU/select-i1.ll
M llvm/test/CodeGen/AMDGPU/select-opt.ll
M llvm/test/CodeGen/AMDGPU/select-vectors.ll
M llvm/test/CodeGen/AMDGPU/select.f16.ll
M llvm/test/CodeGen/AMDGPU/select64.ll
M llvm/test/CodeGen/AMDGPU/selectcc.ll
M llvm/test/CodeGen/AMDGPU/set-inactive-wwm-overwrite.ll
M llvm/test/CodeGen/AMDGPU/set_kill_i1_for_floation_point_comparison.ll
M llvm/test/CodeGen/AMDGPU/setcc-fneg-constant.ll
M llvm/test/CodeGen/AMDGPU/setcc-limit-load-shrink.ll
M llvm/test/CodeGen/AMDGPU/setcc-opt.ll
M llvm/test/CodeGen/AMDGPU/setcc-sext.ll
M llvm/test/CodeGen/AMDGPU/setcc.ll
M llvm/test/CodeGen/AMDGPU/setcc64.ll
M llvm/test/CodeGen/AMDGPU/seto.ll
M llvm/test/CodeGen/AMDGPU/setuo.ll
M llvm/test/CodeGen/AMDGPU/sext-divergence-driven-isel.ll
M llvm/test/CodeGen/AMDGPU/sext-eliminate.ll
M llvm/test/CodeGen/AMDGPU/sext-in-reg-failure-r600.ll
M llvm/test/CodeGen/AMDGPU/sext-in-reg.ll
M llvm/test/CodeGen/AMDGPU/sgpr-control-flow.ll
M llvm/test/CodeGen/AMDGPU/sgpr-copy-duplicate-operand.ll
M llvm/test/CodeGen/AMDGPU/sgpr-copy-local-cse.ll
M llvm/test/CodeGen/AMDGPU/sgpr-copy.ll
M llvm/test/CodeGen/AMDGPU/sgpr-spill-incorrect-fi-bookkeeping-bug.ll
M llvm/test/CodeGen/AMDGPU/sgpr-spill-no-vgprs.ll
M llvm/test/CodeGen/AMDGPU/sgpr-spill-update-only-slot-indexes.ll
M llvm/test/CodeGen/AMDGPU/sgpr-spills-split-regalloc.ll
M llvm/test/CodeGen/AMDGPU/sgprcopies.ll
M llvm/test/CodeGen/AMDGPU/shader-addr64-nonuniform.ll
M llvm/test/CodeGen/AMDGPU/shift-and-i128-ubfe.ll
M llvm/test/CodeGen/AMDGPU/shift-and-i64-ubfe.ll
M llvm/test/CodeGen/AMDGPU/shift-i128.ll
M llvm/test/CodeGen/AMDGPU/shift-select.ll
M llvm/test/CodeGen/AMDGPU/shl.ll
M llvm/test/CodeGen/AMDGPU/shl.v2i16.ll
M llvm/test/CodeGen/AMDGPU/shl_add.ll
M llvm/test/CodeGen/AMDGPU/shl_add_constant.ll
M llvm/test/CodeGen/AMDGPU/shl_add_ptr.ll
M llvm/test/CodeGen/AMDGPU/shl_add_ptr_csub.ll
M llvm/test/CodeGen/AMDGPU/shl_add_ptr_global.ll
M llvm/test/CodeGen/AMDGPU/shl_or.ll
M llvm/test/CodeGen/AMDGPU/should-not-hoist-set-inactive.ll
M llvm/test/CodeGen/AMDGPU/si-annotate-cf-kill.ll
M llvm/test/CodeGen/AMDGPU/si-annotate-cf-noloop.ll
M llvm/test/CodeGen/AMDGPU/si-annotate-cf-unreachable.ll
M llvm/test/CodeGen/AMDGPU/si-annotate-cf.ll
M llvm/test/CodeGen/AMDGPU/si-annotate-cfg-loop-assert.ll
M llvm/test/CodeGen/AMDGPU/si-instr-info-correct-implicit-operands.ll
M llvm/test/CodeGen/AMDGPU/si-lower-control-flow-kill.ll
M llvm/test/CodeGen/AMDGPU/si-lower-control-flow-unreachable-block.ll
M llvm/test/CodeGen/AMDGPU/si-sgpr-spill.ll
M llvm/test/CodeGen/AMDGPU/si-spill-cf.ll
M llvm/test/CodeGen/AMDGPU/si-triv-disjoint-mem-access.ll
M llvm/test/CodeGen/AMDGPU/si-unify-exit-multiple-unreachables.ll
M llvm/test/CodeGen/AMDGPU/si-unify-exit-return-unreachable.ll
M llvm/test/CodeGen/AMDGPU/si-vector-hang.ll
M llvm/test/CodeGen/AMDGPU/sibling-call.ll
M llvm/test/CodeGen/AMDGPU/sign_extend.ll
M llvm/test/CodeGen/AMDGPU/simple-indirect-call-2.ll
M llvm/test/CodeGen/AMDGPU/simple-indirect-call.ll
M llvm/test/CodeGen/AMDGPU/sink-image-sample.ll
M llvm/test/CodeGen/AMDGPU/sint_to_fp.f64.ll
M llvm/test/CodeGen/AMDGPU/sint_to_fp.i64.ll
M llvm/test/CodeGen/AMDGPU/sint_to_fp.ll
M llvm/test/CodeGen/AMDGPU/sitofp.f16.ll
M llvm/test/CodeGen/AMDGPU/skip-branch-trap.ll
M llvm/test/CodeGen/AMDGPU/skip-if-dead.ll
M llvm/test/CodeGen/AMDGPU/smed3.ll
M llvm/test/CodeGen/AMDGPU/smfmac_no_agprs.ll
M llvm/test/CodeGen/AMDGPU/sminmax.ll
M llvm/test/CodeGen/AMDGPU/smrd-gfx10.ll
M llvm/test/CodeGen/AMDGPU/smrd-vccz-bug.ll
M llvm/test/CodeGen/AMDGPU/smrd.ll
M llvm/test/CodeGen/AMDGPU/smrd_vmem_war.ll
M llvm/test/CodeGen/AMDGPU/sopk-compares.ll
M llvm/test/CodeGen/AMDGPU/sopk-no-literal.ll
M llvm/test/CodeGen/AMDGPU/spill-agpr.ll
M llvm/test/CodeGen/AMDGPU/spill-alloc-sgpr-init-bug.ll
M llvm/test/CodeGen/AMDGPU/spill-cfg-position.ll
M llvm/test/CodeGen/AMDGPU/spill-csr-frame-ptr-reg-copy.ll
M llvm/test/CodeGen/AMDGPU/spill-m0.ll
M llvm/test/CodeGen/AMDGPU/spill-vector-superclass.ll
M llvm/test/CodeGen/AMDGPU/spill-vgpr-to-agpr-update-regscavenger.ll
M llvm/test/CodeGen/AMDGPU/spill-vgpr-to-agpr.ll
M llvm/test/CodeGen/AMDGPU/spill-vgpr.ll
M llvm/test/CodeGen/AMDGPU/spill-wide-sgpr.ll
M llvm/test/CodeGen/AMDGPU/spill-writelane-vgprs.ll
M llvm/test/CodeGen/AMDGPU/spill_more_than_wavesize_csr_sgprs.ll
M llvm/test/CodeGen/AMDGPU/split-scalar-i64-add.ll
M llvm/test/CodeGen/AMDGPU/split-smrd.ll
M llvm/test/CodeGen/AMDGPU/split-vector-memoperand-offsets.ll
M llvm/test/CodeGen/AMDGPU/sra.ll
M llvm/test/CodeGen/AMDGPU/srem.ll
M llvm/test/CodeGen/AMDGPU/srem64.ll
M llvm/test/CodeGen/AMDGPU/srl.ll
M llvm/test/CodeGen/AMDGPU/ssubo.ll
M llvm/test/CodeGen/AMDGPU/stack-pointer-offset-relative-frameindex.ll
M llvm/test/CodeGen/AMDGPU/stack-realign.ll
M llvm/test/CodeGen/AMDGPU/store-barrier.ll
M llvm/test/CodeGen/AMDGPU/store-global.ll
M llvm/test/CodeGen/AMDGPU/store-hi16.ll
M llvm/test/CodeGen/AMDGPU/store-local.128.ll
M llvm/test/CodeGen/AMDGPU/store-local.96.ll
M llvm/test/CodeGen/AMDGPU/store-local.ll
M llvm/test/CodeGen/AMDGPU/store-private.ll
M llvm/test/CodeGen/AMDGPU/store-v3i64.ll
M llvm/test/CodeGen/AMDGPU/store-vector-ptrs.ll
M llvm/test/CodeGen/AMDGPU/store-weird-sizes.ll
M llvm/test/CodeGen/AMDGPU/sub-zext-cc-zext-cc.ll
M llvm/test/CodeGen/AMDGPU/sub.i16.ll
M llvm/test/CodeGen/AMDGPU/sub.ll
M llvm/test/CodeGen/AMDGPU/sub.v2i16.ll
M llvm/test/CodeGen/AMDGPU/sub_i1.ll
A llvm/test/CodeGen/AMDGPU/sub_u64.ll
M llvm/test/CodeGen/AMDGPU/swdev373493.ll
M llvm/test/CodeGen/AMDGPU/switch-default-block-unreachable.ll
M llvm/test/CodeGen/AMDGPU/switch-unreachable.ll
M llvm/test/CodeGen/AMDGPU/swizzle.bit.extract.ll
M llvm/test/CodeGen/AMDGPU/tail-call-amdgpu-gfx.ll
M llvm/test/CodeGen/AMDGPU/tail-call-inreg-arguments.ll
M llvm/test/CodeGen/AMDGPU/tail-call-uniform-target-in-vgprs-issue110930.ll
M llvm/test/CodeGen/AMDGPU/target-cpu.ll
M llvm/test/CodeGen/AMDGPU/token-factor-inline-limit-test.ll
M llvm/test/CodeGen/AMDGPU/transform-block-with-return-to-epilog.ll
M llvm/test/CodeGen/AMDGPU/trap-abis.ll
M llvm/test/CodeGen/AMDGPU/trap.ll
M llvm/test/CodeGen/AMDGPU/trunc-bitcast-vector.ll
M llvm/test/CodeGen/AMDGPU/trunc-cmp-constant.ll
M llvm/test/CodeGen/AMDGPU/trunc-combine.ll
M llvm/test/CodeGen/AMDGPU/trunc-store-f64-to-f16.ll
M llvm/test/CodeGen/AMDGPU/trunc-store-i1.ll
M llvm/test/CodeGen/AMDGPU/trunc-store-i64.ll
M llvm/test/CodeGen/AMDGPU/trunc-store-vec-i16-to-i8.ll
M llvm/test/CodeGen/AMDGPU/trunc.ll
M llvm/test/CodeGen/AMDGPU/twoaddr-constrain.ll
M llvm/test/CodeGen/AMDGPU/uaddo.ll
M llvm/test/CodeGen/AMDGPU/udiv.ll
M llvm/test/CodeGen/AMDGPU/udiv64.ll
M llvm/test/CodeGen/AMDGPU/udivrem.ll
M llvm/test/CodeGen/AMDGPU/udivrem24.ll
M llvm/test/CodeGen/AMDGPU/uint_to_fp.f64.ll
M llvm/test/CodeGen/AMDGPU/uint_to_fp.i64.ll
M llvm/test/CodeGen/AMDGPU/uint_to_fp.ll
M llvm/test/CodeGen/AMDGPU/uitofp.f16.ll
M llvm/test/CodeGen/AMDGPU/umed3.ll
M llvm/test/CodeGen/AMDGPU/unaligned-load-store.ll
M llvm/test/CodeGen/AMDGPU/undefined-subreg-liverange.ll
M llvm/test/CodeGen/AMDGPU/unhandled-loop-condition-assertion.ll
M llvm/test/CodeGen/AMDGPU/uniform-branch-intrinsic-cond.ll
M llvm/test/CodeGen/AMDGPU/uniform-cfg.ll
M llvm/test/CodeGen/AMDGPU/uniform-crash.ll
M llvm/test/CodeGen/AMDGPU/uniform-load-from-tid.ll
M llvm/test/CodeGen/AMDGPU/uniform-phi-with-undef.ll
M llvm/test/CodeGen/AMDGPU/unigine-liveness-crash.ll
M llvm/test/CodeGen/AMDGPU/unknown-processor.ll
M llvm/test/CodeGen/AMDGPU/unpack-half.ll
M llvm/test/CodeGen/AMDGPU/unstructured-cfg-def-use-issue.ll
M llvm/test/CodeGen/AMDGPU/unsupported-calls.ll
M llvm/test/CodeGen/AMDGPU/unsupported-cs-chain.ll
M llvm/test/CodeGen/AMDGPU/unsupported-image-a16.ll
M llvm/test/CodeGen/AMDGPU/unsupported-image-g16.ll
M llvm/test/CodeGen/AMDGPU/unsupported-image-sample.ll
M llvm/test/CodeGen/AMDGPU/urem.ll
M llvm/test/CodeGen/AMDGPU/urem64.ll
M llvm/test/CodeGen/AMDGPU/use-sgpr-multiple-times.ll
M llvm/test/CodeGen/AMDGPU/usubo.ll
M llvm/test/CodeGen/AMDGPU/v1024.ll
M llvm/test/CodeGen/AMDGPU/v_add_u64_pseudo_sdwa.ll
M llvm/test/CodeGen/AMDGPU/v_ashr_pk.ll
M llvm/test/CodeGen/AMDGPU/v_cmp_gfx11.ll
M llvm/test/CodeGen/AMDGPU/v_cndmask.ll
M llvm/test/CodeGen/AMDGPU/v_cvt_pk_u8_f32.ll
M llvm/test/CodeGen/AMDGPU/v_mac.ll
M llvm/test/CodeGen/AMDGPU/v_mac_f16.ll
M llvm/test/CodeGen/AMDGPU/v_madak_f16.ll
M llvm/test/CodeGen/AMDGPU/v_pack.ll
M llvm/test/CodeGen/AMDGPU/v_sat_pk_u8_i16.ll
M llvm/test/CodeGen/AMDGPU/v_sub_u64_pseudo_sdwa.ll
M llvm/test/CodeGen/AMDGPU/v_swap_b16.ll
M llvm/test/CodeGen/AMDGPU/valu-i1.ll
M llvm/test/CodeGen/AMDGPU/vcmp-saveexec-to-vcmpx.ll
M llvm/test/CodeGen/AMDGPU/vector-alloca-bitcast.ll
M llvm/test/CodeGen/AMDGPU/vector-alloca.ll
M llvm/test/CodeGen/AMDGPU/vector-extract-insert.ll
M llvm/test/CodeGen/AMDGPU/vector_shuffle.packed.ll
M llvm/test/CodeGen/AMDGPU/vectorize-global-local.ll
M llvm/test/CodeGen/AMDGPU/vectorize-loads.ll
M llvm/test/CodeGen/AMDGPU/vgpr-large-tuple-alloc-error.ll
M llvm/test/CodeGen/AMDGPU/vgpr-liverange-ir.ll
M llvm/test/CodeGen/AMDGPU/vgpr-liverange.ll
M llvm/test/CodeGen/AMDGPU/vgpr-spill-emergency-stack-slot-compute.ll
M llvm/test/CodeGen/AMDGPU/vgpr-spill-emergency-stack-slot.ll
M llvm/test/CodeGen/AMDGPU/vgpr-tuple-allocation.ll
M llvm/test/CodeGen/AMDGPU/vop-shrink.ll
M llvm/test/CodeGen/AMDGPU/vopc_dpp.ll
M llvm/test/CodeGen/AMDGPU/vselect.ll
M llvm/test/CodeGen/AMDGPU/wait-before-stores-with-scope_sys.ll
M llvm/test/CodeGen/AMDGPU/wait-xcnt.mir
M llvm/test/CodeGen/AMDGPU/wait.ll
M llvm/test/CodeGen/AMDGPU/waitcnt-vscnt.ll
M llvm/test/CodeGen/AMDGPU/waterfall_kills_scc.ll
M llvm/test/CodeGen/AMDGPU/wave32.ll
M llvm/test/CodeGen/AMDGPU/wave_dispatch_regs.ll
M llvm/test/CodeGen/AMDGPU/while-break.ll
M llvm/test/CodeGen/AMDGPU/whole-wave-functions.ll
M llvm/test/CodeGen/AMDGPU/whole-wave-register-copy.ll
M llvm/test/CodeGen/AMDGPU/whole-wave-register-spill.ll
M llvm/test/CodeGen/AMDGPU/widen-smrd-loads.ll
M llvm/test/CodeGen/AMDGPU/widen-vselect-and-mask.ll
M llvm/test/CodeGen/AMDGPU/wmma-gfx12-w32-f16-f32-matrix-modifiers.ll
M llvm/test/CodeGen/AMDGPU/wmma-gfx12-w32-imm.ll
M llvm/test/CodeGen/AMDGPU/wmma-gfx12-w32-iu-modifiers.ll
M llvm/test/CodeGen/AMDGPU/wmma-gfx12-w32-swmmac-index_key.ll
M llvm/test/CodeGen/AMDGPU/wmma-gfx12-w32.ll
M llvm/test/CodeGen/AMDGPU/wmma-gfx12-w64-f16-f32-matrix-modifiers.ll
M llvm/test/CodeGen/AMDGPU/wmma-gfx12-w64-imm.ll
M llvm/test/CodeGen/AMDGPU/wmma-gfx12-w64-iu-modifiers.ll
M llvm/test/CodeGen/AMDGPU/wmma-gfx12-w64-swmmac-index_key.ll
M llvm/test/CodeGen/AMDGPU/wmma-gfx12-w64.ll
M llvm/test/CodeGen/AMDGPU/wmma_modifiers.ll
M llvm/test/CodeGen/AMDGPU/wmma_multiple_32.ll
M llvm/test/CodeGen/AMDGPU/wmma_multiple_64.ll
M llvm/test/CodeGen/AMDGPU/workgroup-id-in-arch-sgprs.ll
M llvm/test/CodeGen/AMDGPU/wqm-gfx11.ll
M llvm/test/CodeGen/AMDGPU/wqm.ll
M llvm/test/CodeGen/AMDGPU/write-register-vgpr-into-sgpr.ll
M llvm/test/CodeGen/AMDGPU/write_register.ll
M llvm/test/CodeGen/AMDGPU/wwm-reserved-spill.ll
M llvm/test/CodeGen/AMDGPU/wwm-reserved.ll
M llvm/test/CodeGen/AMDGPU/xnor.ll
M llvm/test/CodeGen/AMDGPU/xor3-i1-const.ll
M llvm/test/CodeGen/AMDGPU/xor3.ll
M llvm/test/CodeGen/AMDGPU/xor_add.ll
M llvm/test/CodeGen/AMDGPU/zero_extend.ll
M llvm/test/CodeGen/AMDGPU/zext-divergence-driven-isel.ll
M llvm/test/CodeGen/AMDGPU/zext-i64-bit-operand.ll
A llvm/test/CodeGen/DirectX/ShaderFlags/lifetimes-noint64op.ll
A llvm/test/CodeGen/DirectX/bugfix_150050_data_scalarize_const_gep.ll
M llvm/test/CodeGen/DirectX/legalize-lifetimes-valver-1.6.ll
M llvm/test/CodeGen/LoongArch/lasx/build-vector.ll
M llvm/test/CodeGen/LoongArch/lsx/build-vector.ll
M llvm/test/CodeGen/NVPTX/LoadStoreVectorizer.ll
M llvm/test/CodeGen/NVPTX/extractelement.ll
M llvm/test/CodeGen/NVPTX/i8x4-instructions.ll
M llvm/test/CodeGen/NVPTX/pr126337.ll
M llvm/test/CodeGen/RISCV/attributes.ll
A llvm/test/CodeGen/RISCV/pr148084.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-interleaved-access.ll
M llvm/test/CodeGen/RISCV/rvv/vxrm.mir
M llvm/test/CodeGen/RISCV/xqcisls.ll
M llvm/test/CodeGen/RISCV/xtheadmemidx.ll
A llvm/test/CodeGen/SPIRV/pointers/resource-vector-load-store.ll
M llvm/test/CodeGen/WebAssembly/ref-test-func.ll
A llvm/test/CodeGen/WebAssembly/removed-terminator.ll
M llvm/test/CodeGen/X86/vec_extract.ll
A llvm/test/FileCheck/long-check.txt
M llvm/test/MC/AMDGPU/gfx1250_asm_vop2.s
M llvm/test/MC/AMDGPU/gfx1250_asm_vop2_err.s
M llvm/test/MC/AMDGPU/gfx1250_asm_vop3-fake16.s
M llvm/test/MC/AMDGPU/gfx1250_asm_vop3.s
A llvm/test/MC/AMDGPU/gfx1250_asm_vop3_dpp16-fake16.s
A llvm/test/MC/AMDGPU/gfx1250_asm_vop3_dpp16.s
A llvm/test/MC/AMDGPU/gfx1250_asm_vop3_dpp8-fake16.s
A llvm/test/MC/AMDGPU/gfx1250_asm_vop3_dpp8.s
A llvm/test/MC/AMDGPU/gfx1250_asm_vop3p.s
M llvm/test/MC/AMDGPU/gfx1250_err.s
M llvm/test/MC/Disassembler/AMDGPU/gfx1250_dasm_vop2.txt
M llvm/test/MC/Disassembler/AMDGPU/gfx1250_dasm_vop3.txt
A llvm/test/MC/Disassembler/AMDGPU/gfx1250_dasm_vop3_dpp16.txt
A llvm/test/MC/Disassembler/AMDGPU/gfx1250_dasm_vop3_dpp8.txt
A llvm/test/MC/Disassembler/AMDGPU/gfx1250_dasm_vop3p.txt
M llvm/test/MC/ELF/section-sym-err.s
R llvm/test/MC/ELF/section-sym-err2.s
M llvm/test/MC/ELF/section-sym2.s
M llvm/test/MC/RISCV/attribute-arch.s
M llvm/test/MC/RISCV/rv32p-valid.s
M llvm/test/MC/RISCV/rv64p-valid.s
A llvm/test/MC/X86/intel-syntax-parentheses.s
A llvm/test/TableGen/SDNodeInfoEmitter/advanced.td
A llvm/test/TableGen/SDNodeInfoEmitter/ambiguous-constraints-1.td
A llvm/test/TableGen/SDNodeInfoEmitter/ambiguous-constraints-2.td
R llvm/test/TableGen/SDNodeInfoEmitter/ambiguous-constraints.td
R llvm/test/TableGen/SDNodeInfoEmitter/basic.td
A llvm/test/TableGen/SDNodeInfoEmitter/no-nodes.td
A llvm/test/TableGen/SDNodeInfoEmitter/trivial-node.td
M llvm/test/ThinLTO/X86/memprof-icp.ll
M llvm/test/Transforms/AggressiveInstCombine/X86/store-merge.ll
M llvm/test/Transforms/Attributor/memory_locations.ll
M llvm/test/Transforms/GVN/lifetime-simple.ll
A llvm/test/Transforms/HipStdPar/global-var-indirection-wrong-table-member-0.ll
A llvm/test/Transforms/HipStdPar/global-var-indirection-wrong-table-member-1.ll
A llvm/test/Transforms/HipStdPar/global-var-indirection-wrong-table-member-2.ll
A llvm/test/Transforms/HipStdPar/global-var-indirection-wrong-table-member-count.ll
A llvm/test/Transforms/HipStdPar/global-var-indirection-wrong-table-type.ll
A llvm/test/Transforms/HipStdPar/global-var-indirection.ll
M llvm/test/Transforms/HipStdPar/global-var.ll
M llvm/test/Transforms/InferAddressSpaces/AMDGPU/lifetime.ll
M llvm/test/Transforms/InferAddressSpaces/NVPTX/lifetime.ll
M llvm/test/Transforms/Inline/inlined-mustprogress-loop-metadata.ll
M llvm/test/Transforms/InstCombine/icmp-gep.ll
A llvm/test/Transforms/InstCombine/pr150338.ll
M llvm/test/Transforms/InstCombine/sub-gep.ll
M llvm/test/Transforms/LICM/PR116813-memoryssa-outdated.ll
M llvm/test/Transforms/LoopVectorize/AArch64/interleave-with-gaps.ll
M llvm/test/Transforms/LoopVectorize/AArch64/partial-reduce-dot-product.ll
M llvm/test/Transforms/LoopVectorize/RISCV/vplan-vp-call-intrinsics.ll
M llvm/test/Transforms/LoopVectorize/RISCV/vplan-vp-cast-intrinsics.ll
M llvm/test/Transforms/LoopVectorize/RISCV/vplan-vp-intrinsics-fixed-order-recurrence.ll
M llvm/test/Transforms/LoopVectorize/RISCV/vplan-vp-intrinsics-reduction.ll
M llvm/test/Transforms/LoopVectorize/RISCV/vplan-vp-intrinsics.ll
M llvm/test/Transforms/Mem2Reg/alloca_addrspace.ll
M llvm/test/Transforms/Mem2Reg/ignore-droppable.ll
M llvm/test/Transforms/Mem2Reg/ignore-lifetime.ll
M llvm/test/Transforms/NewGVN/verify-memoryphi.ll
A llvm/test/Transforms/ObjCARC/test_autorelease_pool.ll
M llvm/test/Transforms/PGOProfile/icp_mismatch_msg.ll
A llvm/test/Transforms/PGOProfile/indirect_call_promotion2.ll
A llvm/test/Transforms/PGOProfile/prof-verify-as-needed.ll
A llvm/test/Transforms/PGOProfile/prof-verify-existing.ll
A llvm/test/Transforms/PGOProfile/prof-verify.ll
M llvm/test/Transforms/PhaseOrdering/AArch64/block_scaling_decompr_8bit.ll
M llvm/test/Transforms/SLPVectorizer/X86/buildvector-schedule-for-subvector.ll
M llvm/test/Transforms/SLPVectorizer/X86/extract-scalar-from-undef.ll
M llvm/test/Transforms/SLPVectorizer/X86/full-match-with-poison-scalar.ll
M llvm/test/Transforms/SLPVectorizer/X86/node-outside-used-only.ll
M llvm/test/Transforms/SLPVectorizer/X86/non-schedulable-instructions-become-schedulable.ll
M llvm/test/Transforms/SLPVectorizer/X86/pr47642.ll
M llvm/test/Transforms/SLPVectorizer/X86/revec-reduced-value-vectorized-later.ll
M llvm/test/Transforms/SLPVectorizer/alternate-non-profitable.ll
M llvm/test/Transforms/SROA/alloca-address-space.ll
M llvm/test/Transforms/SROA/basictest.ll
M llvm/test/Transforms/SROA/ignore-droppable.ll
M llvm/test/Transforms/SimpleLoopUnswitch/exponential-nontrivial-unswitch-nested.ll
M llvm/test/Transforms/SimpleLoopUnswitch/exponential-nontrivial-unswitch-nested2.ll
M llvm/test/Transforms/SimpleLoopUnswitch/exponential-nontrivial-unswitch.ll
M llvm/test/Transforms/SimpleLoopUnswitch/exponential-switch-unswitch.ll
M llvm/test/Transforms/SimpleLoopUnswitch/guards.ll
M llvm/test/Transforms/SimpleLoopUnswitch/inject-invariant-conditions.ll
M llvm/test/Transforms/SimpleLoopUnswitch/invalidate-block-and-loop-dispositions.ll
M llvm/test/Transforms/SimpleLoopUnswitch/nontrivial-unswitch-freeze.ll
M llvm/test/Transforms/SimpleLoopUnswitch/nontrivial-unswitch-select.ll
M llvm/test/Transforms/SimpleLoopUnswitch/nontrivial-unswitch.ll
M llvm/test/Transforms/SimpleLoopUnswitch/partial-unswitch-loop-and-block-dispositions.ll
M llvm/test/Transforms/SimpleLoopUnswitch/partial-unswitch.ll
A llvm/test/Transforms/SimpleLoopUnswitch/pr138509.ll
M llvm/test/Transforms/SimpleLoopUnswitch/update-scev-3.ll
M llvm/test/Transforms/SimplifyCFG/X86/empty-cleanuppad.ll
M llvm/test/Transforms/SimplifyCFG/invoke_unwind_lifetime.ll
A llvm/test/tools/dxil-dis/lifetimes.ll
A llvm/test/tools/llvm-exegesis/RISCV/set-reg-init-check.s
M llvm/tools/bugpoint/bugpoint.cpp
M llvm/tools/llvm-exegesis/lib/RISCV/Target.cpp
M llvm/utils/UpdateTestChecks/asm.py
M llvm/utils/gn/secondary/lldb/source/Plugins/Language/CPlusPlus/BUILD.gn
M llvm/utils/gn/secondary/llvm/lib/Transforms/Utils/BUILD.gn
M llvm/utils/update_mir_test_checks.py
M mlir/docs/Rationale/RationaleLinalgDialect.md
M mlir/include/mlir-c/IR.h
M mlir/include/mlir/Conversion/ArithToAMDGPU/ArithToAMDGPU.h
M mlir/include/mlir/Dialect/AMDGPU/Transforms/Passes.h
M mlir/include/mlir/Dialect/AMDGPU/Transforms/Passes.td
M mlir/include/mlir/Dialect/ArmNeon/TransformOps/ArmNeonVectorTransformOps.td
M mlir/include/mlir/Dialect/ArmNeon/Transforms.h
M mlir/include/mlir/Dialect/ArmSVE/Transforms/Transforms.h
M mlir/include/mlir/Dialect/Linalg/Transforms/Transforms.h
M mlir/include/mlir/Dialect/MemRef/Utils/MemRefUtils.h
M mlir/include/mlir/Dialect/Mesh/IR/MeshOps.h
M mlir/include/mlir/Dialect/Mesh/IR/MeshOps.td
M mlir/include/mlir/Dialect/OpenMP/OpenMPAttrDefs.td
M mlir/include/mlir/Dialect/OpenMP/OpenMPOps.td
M mlir/include/mlir/Dialect/SCF/Transforms/Passes.td
M mlir/include/mlir/Dialect/SPIRV/IR/SPIRVTypes.h
M mlir/include/mlir/Dialect/XeGPU/IR/XeGPUAttrs.td
M mlir/include/mlir/Dialect/XeGPU/IR/XeGPUOps.td
M mlir/include/mlir/Dialect/XeGPU/IR/XeGPUTypes.td
M mlir/include/mlir/IR/OpDefinition.h
M mlir/include/mlir/Parser/Parser.h
M mlir/lib/Analysis/SliceAnalysis.cpp
M mlir/lib/Bindings/Python/IRCore.cpp
M mlir/lib/Bindings/Python/IRModule.h
M mlir/lib/CAPI/IR/IR.cpp
M mlir/lib/Conversion/AMDGPUToROCDL/AMDGPUToROCDL.cpp
M mlir/lib/Conversion/AffineToStandard/AffineToStandard.cpp
M mlir/lib/Conversion/ArithToAMDGPU/ArithToAMDGPU.cpp
M mlir/lib/Conversion/ArithToArmSME/ArithToArmSME.cpp
M mlir/lib/Conversion/ArithToEmitC/ArithToEmitC.cpp
M mlir/lib/Conversion/ArithToLLVM/ArithToLLVM.cpp
M mlir/lib/Conversion/ArithToSPIRV/ArithToSPIRV.cpp
M mlir/lib/Conversion/ArmNeon2dToIntr/ArmNeon2dToIntr.cpp
M mlir/lib/Conversion/ArmSMEToLLVM/ArmSMEToLLVM.cpp
M mlir/lib/Conversion/ArmSMEToSCF/ArmSMEToSCF.cpp
M mlir/lib/Conversion/AsyncToLLVM/AsyncToLLVM.cpp
M mlir/lib/Conversion/BufferizationToMemRef/BufferizationToMemRef.cpp
M mlir/lib/Conversion/VectorToArmSME/VectorToArmSME.cpp
M mlir/lib/Conversion/VectorToLLVM/ConvertVectorToLLVMPass.cpp
M mlir/lib/Dialect/AMDGPU/Transforms/CMakeLists.txt
A mlir/lib/Dialect/AMDGPU/Transforms/FoldMemRefsOps.cpp
M mlir/lib/Dialect/AMDGPU/Transforms/MaskedloadToLoad.cpp
M mlir/lib/Dialect/Affine/Analysis/AffineAnalysis.cpp
M mlir/lib/Dialect/Affine/Analysis/Utils.cpp
M mlir/lib/Dialect/Affine/IR/AffineOps.cpp
M mlir/lib/Dialect/Affine/Transforms/AffineParallelize.cpp
M mlir/lib/Dialect/Affine/Transforms/LoopFusion.cpp
M mlir/lib/Dialect/Affine/Transforms/LoopUnroll.cpp
M mlir/lib/Dialect/Affine/Utils/LoopUtils.cpp
M mlir/lib/Dialect/Affine/Utils/Utils.cpp
M mlir/lib/Dialect/Arith/Transforms/EmulateUnsupportedFloats.cpp
M mlir/lib/Dialect/Arith/Transforms/ExpandOps.cpp
M mlir/lib/Dialect/Arith/Utils/Utils.cpp
M mlir/lib/Dialect/ArmNeon/TransformOps/ArmNeonVectorTransformOps.cpp
M mlir/lib/Dialect/ArmNeon/Transforms/CMakeLists.txt
A mlir/lib/Dialect/ArmNeon/Transforms/LowerContractToNeonPatterns.cpp
R mlir/lib/Dialect/ArmNeon/Transforms/LowerContractionToNeonI8MMPattern.cpp
M mlir/lib/Dialect/ArmSVE/TransformOps/ArmSVEVectorTransformOps.cpp
M mlir/lib/Dialect/ArmSVE/Transforms/LowerContractToSVEPatterns.cpp
M mlir/lib/Dialect/Async/Transforms/AsyncParallelFor.cpp
M mlir/lib/Dialect/Async/Transforms/AsyncToAsyncRuntime.cpp
M mlir/lib/Dialect/Bufferization/Transforms/TensorCopyInsertion.cpp
M mlir/lib/Dialect/Complex/IR/ComplexOps.cpp
M mlir/lib/Dialect/ControlFlow/IR/ControlFlowOps.cpp
M mlir/lib/Dialect/GPU/TransformOps/Utils.cpp
M mlir/lib/Dialect/GPU/Transforms/EliminateBarriers.cpp
M mlir/lib/Dialect/GPU/Transforms/MemoryPromotion.cpp
M mlir/lib/Dialect/IRDL/IRDLVerifiers.cpp
M mlir/lib/Dialect/Index/IR/InferIntRangeInterfaceImpls.cpp
M mlir/lib/Dialect/LLVMIR/IR/LLVMTypeSyntax.cpp
M mlir/lib/Dialect/LLVMIR/IR/XeVMDialect.cpp
M mlir/lib/Dialect/Linalg/IR/LinalgInterfaces.cpp
M mlir/lib/Dialect/Linalg/TransformOps/GPUHeuristics.cpp
M mlir/lib/Dialect/Linalg/Transforms/DropUnitDims.cpp
M mlir/lib/Dialect/Linalg/Transforms/MeshShardingInterfaceImpl.cpp
M mlir/lib/Dialect/Linalg/Transforms/Promotion.cpp
M mlir/lib/Dialect/Linalg/Utils/Utils.cpp
M mlir/lib/Dialect/Math/Transforms/ExpandPatterns.cpp
M mlir/lib/Dialect/Math/Transforms/PolynomialApproximation.cpp
M mlir/lib/Dialect/MemRef/Transforms/FoldMemRefAliasOps.cpp
M mlir/lib/Dialect/MemRef/Transforms/ReifyResultShapes.cpp
M mlir/lib/Dialect/MemRef/Utils/MemRefUtils.cpp
M mlir/lib/Dialect/Mesh/IR/MeshOps.cpp
M mlir/lib/Dialect/Mesh/Interfaces/ShardingInterface.cpp
M mlir/lib/Dialect/Mesh/Transforms/Simplifications.cpp
M mlir/lib/Dialect/Mesh/Transforms/Spmdization.cpp
M mlir/lib/Dialect/Mesh/Transforms/Transforms.cpp
M mlir/lib/Dialect/NVGPU/TransformOps/NVGPUTransformOps.cpp
M mlir/lib/Dialect/OpenACC/IR/OpenACC.cpp
M mlir/lib/Dialect/OpenMP/IR/OpenMPDialect.cpp
M mlir/lib/Dialect/Quant/IR/TypeParser.cpp
M mlir/lib/Dialect/SCF/IR/SCF.cpp
M mlir/lib/Dialect/SCF/TransformOps/SCFTransformOps.cpp
M mlir/lib/Dialect/SCF/Transforms/BufferizableOpInterfaceImpl.cpp
M mlir/lib/Dialect/SCF/Transforms/CMakeLists.txt
M mlir/lib/Dialect/SCF/Transforms/ForToWhile.cpp
M mlir/lib/Dialect/SCF/Transforms/ForallToParallel.cpp
A mlir/lib/Dialect/SCF/Transforms/IfConditionPropagation.cpp
M mlir/lib/Dialect/SCF/Transforms/LoopPipelining.cpp
M mlir/lib/Dialect/SCF/Transforms/LoopSpecialization.cpp
M mlir/lib/Dialect/SCF/Transforms/ParallelLoopFusion.cpp
M mlir/lib/Dialect/SCF/Transforms/ParallelLoopTiling.cpp
M mlir/lib/Dialect/SCF/Transforms/StructuralTypeConversions.cpp
M mlir/lib/Dialect/SCF/Transforms/TileUsingInterface.cpp
M mlir/lib/Dialect/SCF/Transforms/UpliftWhileToFor.cpp
M mlir/lib/Dialect/SCF/Transforms/WrapInZeroTripCheck.cpp
M mlir/lib/Dialect/SCF/Utils/Utils.cpp
M mlir/lib/Dialect/SMT/IR/SMTDialect.cpp
M mlir/lib/Dialect/SMT/IR/SMTOps.cpp
M mlir/lib/Dialect/SPIRV/IR/SPIRVDialect.cpp
M mlir/lib/Dialect/SPIRV/IR/SPIRVTypes.cpp
M mlir/lib/Dialect/Shape/IR/Shape.cpp
M mlir/lib/Dialect/Shape/Transforms/BufferizableOpInterfaceImpl.cpp
M mlir/lib/Dialect/Shape/Transforms/OutlineShapeComputation.cpp
M mlir/lib/Dialect/Shape/Transforms/ShapeToShapeLowering.cpp
M mlir/lib/Dialect/Tensor/Extensions/MeshShardingExtensions.cpp
M mlir/lib/Dialect/Tensor/IR/TensorOps.cpp
M mlir/lib/Dialect/Tensor/IR/TensorTilingInterfaceImpl.cpp
M mlir/lib/Dialect/Tensor/TransformOps/TensorTransformOps.cpp
M mlir/lib/Dialect/Tensor/Transforms/BufferizableOpInterfaceImpl.cpp
M mlir/lib/Dialect/Tensor/Transforms/EmptyOpPatterns.cpp
M mlir/lib/Dialect/Tensor/Transforms/ExtractSliceFromReshapeUtils.cpp
M mlir/lib/Dialect/Tensor/Transforms/FoldTensorSubsetOps.cpp
M mlir/lib/Dialect/Tensor/Transforms/IndependenceTransforms.cpp
M mlir/lib/Dialect/Tensor/Transforms/ReshapePatterns.cpp
M mlir/lib/Dialect/Tensor/Transforms/RewriteAsConstant.cpp
M mlir/lib/Dialect/Tensor/Transforms/RuntimeOpVerification.cpp
M mlir/lib/Dialect/Tensor/Transforms/SubsetInsertionOpInterfaceImpl.cpp
M mlir/lib/Dialect/Tensor/Transforms/SwapExtractSliceWithProducerPatterns.cpp
M mlir/lib/Dialect/Tensor/Utils/Utils.cpp
M mlir/lib/Dialect/Tosa/IR/TosaCanonicalizations.cpp
M mlir/lib/Dialect/Tosa/Transforms/TosaConvertIntegerTypeToSignless.cpp
M mlir/lib/Dialect/Transform/Interfaces/TransformInterfaces.cpp
M mlir/lib/Dialect/Transform/TuneExtension/TuneExtensionOps.cpp
M mlir/lib/Dialect/Vector/IR/VectorOps.cpp
M mlir/lib/Dialect/Vector/Transforms/LowerVectorTranspose.cpp
M mlir/lib/Dialect/X86Vector/Transforms/AVXTranspose.cpp
M mlir/lib/Dialect/XeGPU/IR/XeGPUDialect.cpp
M mlir/lib/Dialect/XeGPU/IR/XeGPUOps.cpp
M mlir/lib/Dialect/XeGPU/Transforms/XeGPUBlocking.cpp
M mlir/lib/Dialect/XeGPU/Transforms/XeGPUFoldAliasOps.cpp
M mlir/lib/Dialect/XeGPU/Transforms/XeGPUSubgroupDistribute.cpp
M mlir/lib/Dialect/XeGPU/Transforms/XeGPUUnroll.cpp
M mlir/lib/Dialect/XeGPU/Transforms/XeGPUWgToSgDistribute.cpp
M mlir/lib/Dialect/XeGPU/Utils/XeGPUUtils.cpp
M mlir/lib/IR/SymbolTable.cpp
M mlir/lib/Target/LLVM/CMakeLists.txt
M mlir/lib/Target/LLVMIR/Dialect/OpenMP/OpenMPToLLVMIRTranslation.cpp
M mlir/lib/Target/SPIRV/Deserialization/Deserializer.cpp
M mlir/lib/Target/SPIRV/Serialization/Serializer.cpp
M mlir/lib/Transforms/CSE.cpp
M mlir/lib/Transforms/Utils/GreedyPatternRewriteDriver.cpp
M mlir/lib/Transforms/Utils/RegionUtils.cpp
M mlir/test/Conversion/ArmSMEToSCF/arm-sme-to-scf.mlir
A mlir/test/Dialect/AMDGPU/amdgpu-fold-memrefs.mlir
M mlir/test/Dialect/Affine/loop-fusion-4.mlir
A mlir/test/Dialect/ArmNeon/vector-bfmmla.mlir
M mlir/test/Dialect/Linalg/mesh-spmdization.mlir
M mlir/test/Dialect/Mesh/forward-sharding-propagation.mlir
M mlir/test/Dialect/Mesh/invalid.mlir
M mlir/test/Dialect/Mesh/ops.mlir
M mlir/test/Dialect/Mesh/resharding-spmdization.mlir
M mlir/test/Dialect/Mesh/sharding-propagation.mlir
M mlir/test/Dialect/Mesh/spmdization.mlir
M mlir/test/Dialect/NVGPU/transform-matmul-to-nvvm.mlir
M mlir/test/Dialect/OpenMP/ops.mlir
M mlir/test/Dialect/SCF/canonicalize.mlir
A mlir/test/Dialect/SCF/if-cond-prop.mlir
M mlir/test/Dialect/SPIRV/IR/types.mlir
M mlir/test/Dialect/Tosa/canonicalize.mlir
M mlir/test/Dialect/Vector/canonicalize.mlir
M mlir/test/Dialect/XeGPU/invalid.mlir
M mlir/test/Dialect/XeGPU/layout.mlir
M mlir/test/Dialect/XeGPU/ops.mlir
M mlir/test/Dialect/XeGPU/xegpu-blocking.mlir
M mlir/test/Dialect/XeGPU/xegpu-wg-to-sg-rr.mlir
M mlir/test/Dialect/XeGPU/xegpu-wg-to-sg.mlir
A mlir/test/Integration/Dialect/Vector/CPU/ArmNeon/vector-contract-bfmmla.mlir
M mlir/test/Integration/Dialect/Vector/CPU/ArmNeon/vector-contract-i8mm.mlir
M mlir/test/lib/Analysis/TestCFGLoopInfo.cpp
M mlir/test/lib/Dialect/Test/TestPatterns.cpp
M mlir/test/python/ir/operation.py
M offload/liboffload/API/Event.td
M offload/liboffload/API/Kernel.td
M offload/liboffload/API/Memory.td
M offload/liboffload/API/Queue.td
M offload/liboffload/src/OffloadImpl.cpp
M offload/test/lit.cfg
M offload/unittests/OffloadAPI/CMakeLists.txt
M offload/unittests/OffloadAPI/common/Fixtures.hpp
M offload/unittests/OffloadAPI/device_code/CMakeLists.txt
A offload/unittests/OffloadAPI/device_code/sequence.c
A offload/unittests/OffloadAPI/event/olCreateEvent.cpp
M offload/unittests/OffloadAPI/event/olDestroyEvent.cpp
A offload/unittests/OffloadAPI/event/olSyncEvent.cpp
R offload/unittests/OffloadAPI/event/olWaitEvent.cpp
M offload/unittests/OffloadAPI/kernel/olLaunchKernel.cpp
M offload/unittests/OffloadAPI/memory/olMemcpy.cpp
A offload/unittests/OffloadAPI/queue/olSyncQueue.cpp
A offload/unittests/OffloadAPI/queue/olWaitEvents.cpp
R offload/unittests/OffloadAPI/queue/olWaitQueue.cpp
M polly/include/polly/LinkAllPasses.h
M utils/bazel/llvm-project-overlay/clang-tools-extra/clang-tidy/BUILD.bazel
M utils/bazel/llvm-project-overlay/libc/BUILD.bazel
M utils/bazel/llvm-project-overlay/libc/test/UnitTest/BUILD.bazel
M utils/bazel/llvm-project-overlay/libc/test/libc_test_rules.bzl
M utils/bazel/llvm-project-overlay/libc/test/src/__support/FPUtil/BUILD.bazel
M utils/bazel/llvm-project-overlay/libc/test/src/string/BUILD.bazel
M utils/bazel/llvm-project-overlay/libc/utils/MPCWrapper/BUILD.bazel
M utils/bazel/llvm-project-overlay/libc/utils/MPFRWrapper/BUILD.bazel
M utils/bazel/llvm-project-overlay/llvm/BUILD.bazel
M utils/bazel/llvm-project-overlay/mlir/BUILD.bazel
M utils/bazel/llvm_configs/abi-breaking.h.cmake
Log Message:
-----------
Merge branch 'main' into users/hanhanW/restrict-pack-unpack-folding-patterns
Compare: https://github.com/llvm/llvm-project/compare/d832b43f5679...a23b8dcb293d
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