[all-commits] [llvm/llvm-project] b4edd8: [AArch64] Remove redundant FMOV for zero-extended ...

[Amina Chabane via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: b4edd827e4f71c2a0fcb13f79de7eae4545f0aea
      https://github.com/llvm/llvm-project/commit/b4edd827e4f71c2a0fcb13f79de7eae4545f0aea
  Author: Amina Chabane <amina.chabane at arm.com>
  Date:   2025-07-24 (Thu, 24 Jul 2025)

  Changed paths:
    M llvm/lib/Target/AArch64/AArch64InstrInfo.td
    A llvm/test/CodeGen/AArch64/load-zext-bitcast.ll

  Log Message:
  -----------
  [AArch64] Remove redundant FMOV for zero-extended i32/i16 loads to f64 (#146920)

Previously, a separate load, zext and FMOV instruction was emitted. This
patch adds a new TableGen pattern to avoid the unnecessary FMOV. A test
is included in test/CodeGen/AArch64/load_u64_from_u32.ll



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