[all-commits] [llvm/llvm-project] 992118: [IA] Add masked.load/store support for shuffle (de...

[Fangrui Song via All-commits]

  Branch: refs/heads/users/MaskRay/spr/main.goff-only-register-sections-within-mcobjectstreamerchangesection
  Home:   https://github.com/llvm/llvm-project
  Commit: 992118cb4deab139ae384bb85f03225a9a21b008
      https://github.com/llvm/llvm-project/commit/992118cb4deab139ae384bb85f03225a9a21b008
  Author: Philip Reames <preames at rivosinc.com>
  Date:   2025-07-23 (Wed, 23 Jul 2025)

  Changed paths:
    M llvm/lib/CodeGen/InterleavedAccessPass.cpp
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-interleaved-access.ll

  Log Message:
  -----------
  [IA] Add masked.load/store support for shuffle (de)interleave load/store (#150241)

This completes the basic support for masked.laod and masked.store in
InterleaveAccess. The backend already added via the intrinsic lowering
path and the common code structure (in RISCV at least).

Note that this isn't enough to enable in LV yet. We still need support
for recognizing an interleaved mask via a shufflevector in getMask.


  Commit: 5f35f06e5f50f5e2797cebf1e6204e1a15fc83bc
      https://github.com/llvm/llvm-project/commit/5f35f06e5f50f5e2797cebf1e6204e1a15fc83bc
  Author: Kazu Hirata <kazu at google.com>
  Date:   2025-07-23 (Wed, 23 Jul 2025)

  Changed paths:
    M lldb/tools/lldb-rpc-gen/RPCCommon.cpp
    M lldb/tools/lldb-rpc-gen/lldb-rpc-gen.cpp

  Log Message:
  -----------
  [lldb] Fix warnings

This patch fixes:

  lldb/tools/lldb-rpc-gen/RPCCommon.cpp:197:13: error: unused variable
  'CheckTypeForLLDBPrivate' [-Werror,-Wunused-variable]

  lldb/tools/lldb-rpc-gen/lldb-rpc-gen.cpp:105:18: error: unused
  variable 'HasCallbackParameter' [-Werror,-Wunused-variable]


  Commit: afbf86e719e11aeb9e2b944cd5cf914bdab12426
      https://github.com/llvm/llvm-project/commit/afbf86e719e11aeb9e2b944cd5cf914bdab12426
  Author: Qi Zhao <zhaoqi01 at loongson.cn>
  Date:   2025-07-24 (Thu, 24 Jul 2025)

  Changed paths:
    M llvm/test/CodeGen/LoongArch/lasx/build-vector.ll
    M llvm/test/CodeGen/LoongArch/lsx/build-vector.ll

  Log Message:
  -----------
  [LoongArch] Pre-commit tests for build_vector with undef elements inserting


  Commit: 42017c661c131ff85aa70345e100fa486db66bfa
      https://github.com/llvm/llvm-project/commit/42017c661c131ff85aa70345e100fa486db66bfa
  Author: lntue <lntue at google.com>
  Date:   2025-07-24 (Thu, 24 Jul 2025)

  Changed paths:
    M libc/include/CMakeLists.txt
    M libc/src/stdio/printf_core/CMakeLists.txt

  Log Message:
  -----------
  [libc] Add missing libc.include.inttypes for targets including <inttypes.h>. (#150345)


  Commit: 3e4be55c6b942fdcf1732b1a537e2477567ece54
      https://github.com/llvm/llvm-project/commit/3e4be55c6b942fdcf1732b1a537e2477567ece54
  Author: Uday Bondhugula <uday at polymagelabs.com>
  Date:   2025-07-24 (Thu, 24 Jul 2025)

  Changed paths:
    M mlir/lib/Dialect/Affine/Analysis/Utils.cpp
    M mlir/lib/Dialect/Affine/Transforms/LoopFusion.cpp
    M mlir/test/Dialect/Affine/loop-fusion-4.mlir

  Log Message:
  -----------
  [MLIR][Affine] Improve sibling fusion - handle memrefs from memref defining nodes (#149641)

Improve sibling fusion - handle memrefs from memref defining nodes which
were not being considered.

Remove the unnecessary restriction from MDG memref edge iteration to
restrict to affine.for ops. Nodes in the MDG could be other ops as well.

Fixes: https://github.com/llvm/llvm-project/issues/61825


  Commit: 0a2b97931014c34bef02700a9e9f42c304b54390
      https://github.com/llvm/llvm-project/commit/0a2b97931014c34bef02700a9e9f42c304b54390
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2025-07-23 (Wed, 23 Jul 2025)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVFeatures.td
    M llvm/test/CodeGen/RISCV/attributes.ll
    M llvm/test/MC/RISCV/attribute-arch.s

  Log Message:
  -----------
  [RISCV] Add missing Zvl dependencies for XSfvqmaccdod/XSfvqmaccqoq/XSfvfwmaccqqq. (#150346)

These have an LMUL=1 operand that must have a multiple of 16 or 32
elements in it. This places a lower bound on the VLEN.


  Commit: 5bbf01f7cbd98f9bf79eeaeecd43c28e38cb94fa
      https://github.com/llvm/llvm-project/commit/5bbf01f7cbd98f9bf79eeaeecd43c28e38cb94fa
  Author: Fangrui Song <i at maskray.me>
  Date:   2025-07-23 (Wed, 23 Jul 2025)

  Changed paths:
    M llvm/test/MC/ELF/section-sym-err.s
    R llvm/test/MC/ELF/section-sym-err2.s
    M llvm/test/MC/ELF/section-sym2.s

  Log Message:
  -----------
  MC,test: Improve section symbol test


  Commit: b56bb19e66f399729379b9a1a7ee03ee8060592b
      https://github.com/llvm/llvm-project/commit/b56bb19e66f399729379b9a1a7ee03ee8060592b
  Author: Fangrui Song <i at maskray.me>
  Date:   2025-07-23 (Wed, 23 Jul 2025)

  Changed paths:
    M libc/include/CMakeLists.txt
    M libc/src/stdio/printf_core/CMakeLists.txt
    M lldb/tools/lldb-rpc-gen/RPCCommon.cpp
    M lldb/tools/lldb-rpc-gen/lldb-rpc-gen.cpp
    M llvm/lib/CodeGen/InterleavedAccessPass.cpp
    M llvm/lib/Target/RISCV/RISCVFeatures.td
    M llvm/test/CodeGen/LoongArch/lasx/build-vector.ll
    M llvm/test/CodeGen/LoongArch/lsx/build-vector.ll
    M llvm/test/CodeGen/RISCV/attributes.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-interleaved-access.ll
    M llvm/test/MC/ELF/section-sym-err.s
    R llvm/test/MC/ELF/section-sym-err2.s
    M llvm/test/MC/ELF/section-sym2.s
    M llvm/test/MC/RISCV/attribute-arch.s
    M mlir/lib/Dialect/Affine/Analysis/Utils.cpp
    M mlir/lib/Dialect/Affine/Transforms/LoopFusion.cpp
    M mlir/test/Dialect/Affine/loop-fusion-4.mlir

  Log Message:
  -----------
  [𝘀𝗽𝗿] changes introduced through rebase

Created using spr 1.3.5-bogner

[skip ci]


Compare: https://github.com/llvm/llvm-project/compare/8c36d94a1ff4...b56bb19e66f3

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