[all-commits] [llvm/llvm-project] 0a2b97: [RISCV] Add missing Zvl dependencies for XSfvqmacc...

[Craig Topper via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 0a2b97931014c34bef02700a9e9f42c304b54390
      https://github.com/llvm/llvm-project/commit/0a2b97931014c34bef02700a9e9f42c304b54390
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2025-07-23 (Wed, 23 Jul 2025)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVFeatures.td
    M llvm/test/CodeGen/RISCV/attributes.ll
    M llvm/test/MC/RISCV/attribute-arch.s

  Log Message:
  -----------
  [RISCV] Add missing Zvl dependencies for XSfvqmaccdod/XSfvqmaccqoq/XSfvfwmaccqqq. (#150346)

These have an LMUL=1 operand that must have a multiple of 16 or 32
elements in it. This places a lower bound on the VLEN.



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