[all-commits] [llvm/llvm-project] c9714d: [RISCV] Add profitability checks to SelectAddrRegR...

[Craig Topper via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: c9714d20350f5895f292794eb82bce4231b9472b
      https://github.com/llvm/llvm-project/commit/c9714d20350f5895f292794eb82bce4231b9472b
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2025-07-22 (Tue, 22 Jul 2025)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
    M llvm/test/CodeGen/RISCV/xqcisls.ll
    M llvm/test/CodeGen/RISCV/xtheadmemidx.ll

  Log Message:
  -----------
  [RISCV] Add profitability checks to SelectAddrRegRegScale. (#150135)

-Only fold if the ADD can be folded into all uses.
-Don't reassociate an ADDI if the shl+add can be a shxadd or similar
instruction.
-Only reassociate a single ADDI. If there are 2 addis it's the same
number of instructions as shl+add. If there are more than 2 that it
would increase instructions over folding the addis into the
loads/stores.



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