[all-commits] [llvm/llvm-project] 115f76: [RISCV] Correct alignment of one-active (de)interl...

[Philip Reames via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 115f768b68d290995b3d9129f44e33cd7c8a11a6
      https://github.com/llvm/llvm-project/commit/115f768b68d290995b3d9129f44e33cd7c8a11a6
  Author: Philip Reames <preames at rivosinc.com>
  Date:   2025-07-22 (Tue, 22 Jul 2025)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVInterleavedAccess.cpp

  Log Message:
  -----------
  [RISCV] Correct alignment of one-active (de)interleave cases (#150052)

Noticed this while going to rewrite the load case as a DAG combine. I
don't have a test case which demonstrates this leading to a miscompile,
but it seems like it could be possible.



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