[all-commits] [llvm/llvm-project] bfb180: [RFC][NFC][AMDGPU] Remove `-verify-machineinstrs` ...

[Shilei Tian via All-commits]

  Branch: refs/heads/users/shiltian/remove-verify-machineinstrs-from-codegen-amdgpu
  Home:   https://github.com/llvm/llvm-project
  Commit: bfb1808f1b4e85038c51f18f349ee3d54fb43294
      https://github.com/llvm/llvm-project/commit/bfb1808f1b4e85038c51f18f349ee3d54fb43294
  Author: Shilei Tian <i at tianshilei.me>
  Date:   2025-07-22 (Tue, 22 Jul 2025)

  Changed paths:
    M llvm/test/CodeGen/AMDGPU/32-bit-local-address-space.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/add_shl.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/addo.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/addsubu64.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/artifact-combiner-asserts.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/assert-align.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/atomic_load_local.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/atomic_optimizations_mul_one.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/atomic_store_local.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/atomicrmw_udec_wrap.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/atomicrmw_uinc_wrap.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/bitcast_38_i16.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/bool-legalization.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/buffer-atomic-fadd.f32-no-rtn.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/buffer-atomic-fadd.f32-rtn.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/buffer-atomic-fadd.f64.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/buffer-atomic-fadd.v2f16-no-rtn.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/buffer-atomic-fadd.v2f16-rtn.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/buffer-load-store-pointers.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/buffer-schedule.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/call-outgoing-stack-args.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/clamp-fmed3-const-combine.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/clamp-minmax-const-combine.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/combine-add-nullptr.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/combine-add-to-ptradd.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/combine-amdgpu-cvt-f32-ubyte.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/combine-ashr-narrow.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/combine-extract-vector-load.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/combine-fabs-fneg.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/combine-fcanonicalize.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/combine-fdiv-sqrt-to-rsq.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/combine-fold-binop-into-select.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/combine-foldable-fneg.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/combine-fpneg-one-fneg.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/combine-fsh.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/combine-fsub-fneg.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/combine-itofp.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/combine-lshr-narrow.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/combine-or-redundant.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/combine-redundant-and.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/combine-redundant-neg.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/combine-rot.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/combine-rsq.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/combine-rsq.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/combine-sext-inreg.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/combine-shift-imm-chain-illegal-types.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/combine-shift-imm-chain-shlsat.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/combine-shift-imm-chain.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/combine-shift-of-shifted-logic-shlsat.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/combine-shift-of-shifted-logic.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/combine-shl-from-extend-narrow.postlegal.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/combine-shl-from-extend-narrow.prelegal.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/combine-shl-narrow.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/combine-short-clamp.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/combine-trunc-shift.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/combine-urem-pow-2.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/combine-zext-trunc.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/compute-num-sign-bits-med3.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/constant-bus-restriction.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/cvt_f32_ubyte.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/divergence-divergent-i1-phis-no-lane-mask-merging.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/divergence-divergent-i1-phis-no-lane-mask-merging.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/divergence-divergent-i1-used-outside-loop.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/divergence-divergent-i1-used-outside-loop.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/divergence-structurizer.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/divergence-structurizer.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/divergence-temporal-divergent-i1.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/divergence-temporal-divergent-i1.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/divergence-temporal-divergent-reg.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/divergence-temporal-divergent-reg.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/divergent-control-flow.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/dynamic-alloca-uniform.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/extractelement-stack-lower.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/extractelement.i128.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/extractelement.i16.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/extractelement.i8.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/extractelement.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/fdiv.f16.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/fdiv.f32.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/fdiv.f64.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/flat-atomic-fadd.f32.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/flat-atomic-fadd.v2f16.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/flat-scratch.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/fmed3-min-max-const-combine.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/fp64-atomics-gfx90a.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/frem.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/function-returns.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/hip.extern.shared.array.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/image-waterfall-loop-O0.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inline-asm-mismatched-size.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inline-asm.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/insertelement-stack-lower.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/insertelement.i16.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/insertelement.i8.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/insertelement.large.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-abs.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-add.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-add.s16.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.class.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.class.s16.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.cos.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.cos.s16.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.cvt.pk.i16.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.cvt.pk.u16.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.cvt.pknorm.i16.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.cvt.pknorm.u16.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.cvt.pkrtz.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.ds.swizzle.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.exp.compr.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.exp.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.fcmp.constants.w32.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.fcmp.constants.w64.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.fmad.ftz.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.fmed3.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.fmed3.s16.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.fract.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.fract.s16.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.groupstaticsize.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.mbcnt.lo.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.mul.u24.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.mulhi.i24.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.mulhi.u24.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.rcp.legacy.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.rcp.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.rcp.s16.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.readfirstlane.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.reloc.constant.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.rsq.clamp.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.rsq.legacy.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.rsq.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.rsq.s16.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.s.barrier.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.s.sendmsg.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.sffbh.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.sin.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.sin.s16.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgpu-atomic-cmpxchg-flat.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgpu-atomic-cmpxchg-global.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgpu-ffbh-u32.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgpu-ffbl-b32.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgpu-wave-address.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-and.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-anyext.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-ashr.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-ashr.s16.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-ashr.v2s16.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-atomic-cmpxchg-local.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-atomic-cmpxchg-region.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-atomicrmw-add-flat.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-atomicrmw-add-global.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-atomicrmw-fadd-local.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-atomicrmw-fadd-region.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-atomicrmw-xchg-local.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-atomicrmw-xchg-region.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-bitcast.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-bitreverse.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-br.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-brcond.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-bswap.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-build-vector-trunc.v2s16.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-build-vector.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-constant.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-copy.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-ctlz-zero-undef.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-ctpop.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-cttz-zero-undef.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-extract-vector-elt.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-extract.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fabs.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fadd.s16.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fadd.s32.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fadd.s64.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fcanonicalize.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fceil.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fceil.s16.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fcmp.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fcmp.s16.gfx11plus-fake16.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fcmp.s16.gfx11plus.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fcmp.s16.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fconstant.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fexp2.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-ffloor.s16.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-ffloor.s32.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-ffloor.s64.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fma.s32.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fmad.s32.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fmaxnum-ieee.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fmaxnum-ieee.s16.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fmaxnum-ieee.v2s16.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fmaxnum.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fmaxnum.s16.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fmaxnum.v2s16.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fminnum-ieee.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fminnum-ieee.s16.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fminnum-ieee.v2s16.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fminnum.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fminnum.s16.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fminnum.v2s16.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fmul.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fmul.v2s16.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fneg.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fptosi.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fptoui.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fract.f64.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-frame-index.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fshr.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-i1-copy.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-icmp.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-icmp.s16.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-icmp.s64.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-implicit-def.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-insert-vector-elt.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-insert.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-intrinsic-trunc.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-intrinsic-trunc.s16.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-inttoptr.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-load-atomic-flat.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-load-atomic-global.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-load-atomic-local.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-load-constant.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-load-flat.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-load-global-old-legalization.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-load-global-saddr.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-load-global.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-load-global.s96.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-load-local-128.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-load-local.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-load-private.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-load-smrd.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-lshr.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-lshr.s16.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-lshr.v2s16.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-mad_64_32.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-merge-values.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-mul.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-or.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-pattern-add3.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-pattern-and-or.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-pattern-or3.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-pattern-smed3.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-pattern-smed3.s16.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-pattern-umed3.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-pattern-umed3.s16.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-pattern-xor3.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-phi.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-pseudo-scalar-transcendental.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-ptr-add.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-ptrmask.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-ptrtoint.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-returnaddress.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-sbfx.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-scalar-float-sop1.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-scalar-float-sop2.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-scalar-float-sopc.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-scalar-packed.xfail.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-select.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-sext-inreg.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-sext.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-sextload-local.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-shl.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-shl.s16.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-shl.v2s16.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-sitofp.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-smax.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-smin.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-smulh.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-store-atomic-flat.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-store-atomic-local.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-store-flat.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-store-global.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-store-global.s96.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-store-local.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-store-private.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-sub.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-trunc.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-trunc.v2s16.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-uadde.gfx10.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-uadde.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-uaddo.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-ubfx.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-uitofp.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-umax.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-umin.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-umulh.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-usube.gfx10.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-usube.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-usubo.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-xor.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-zext.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-zextload-local.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-amdgcn-cs-chain.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-amdgcn-sendmsg.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-amdgpu_kernel.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-assert-align.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-call-abi-attribute-hints.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-call-implicit-args.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-call-non-fixed.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-call-return-values.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-call-sret.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-call.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-constantexpr.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-constrained-fp.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-fence.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-function-args.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-indirect-call.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-inline-asm.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-invariant.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-memory-intrinsics.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-prefetch.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-ptrmask.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-sibling-call.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-tail-call.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-zext-vec-index.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/is-safe-to-sink-bug.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/lds-global-value.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/lds-misaligned-bug.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/lds-relocs.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/lds-zero-initializer.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-brcond.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-extractelement-crash.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fcmp-s32.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fcmp.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-icmp.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-llvm.amdgcn.image.atomic.dim.a16.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-memcpy.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-memcpyinline.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-memmove.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-memset.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-phi.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-rotl-rotr.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-trap-gfx11.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-vector-args-gfx7.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-vector-args-gfx8-plus.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.abs.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.ballot.i32.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.ballot.i64.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.dispatch.ptr.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.div.scale.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.end.cf.i32.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.end.cf.i64.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.fdot2.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.fmul.legacy.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.global.atomic.csub.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.if.break.i32.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.if.break.i64.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.getresinfo.a16.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.getresinfo.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.load.1d.d16.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.load.1d.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.load.2d.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.load.2darraymsaa.a16.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.load.2darraymsaa.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.load.3d.a16.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.load.3d.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.sample.cd.g16.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.sample.g16.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.implicit.ptr.buffer.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.interp.inreg.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.interp.p1.f16.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.intersect_ray.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.kernarg.segment.ptr.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.make.buffer.rsrc.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.mfma.gfx90a.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.mov.dpp.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.queue.ptr.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.buffer.atomic.add.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.buffer.atomic.cmpswap.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.buffer.atomic.fadd-with-ret.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.buffer.atomic.fadd.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.buffer.load.format.f16.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.buffer.load.format.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.buffer.load.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.buffer.load.tfe.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.buffer.store.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.ptr.buffer.atomic.add.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.ptr.buffer.atomic.cmpswap.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.ptr.buffer.atomic.fadd-with-ret.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.ptr.buffer.atomic.fadd.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.ptr.buffer.load.format.f16.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.ptr.buffer.load.format.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.ptr.buffer.load.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.ptr.buffer.store.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.ptr.tbuffer.load.f16.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.ptr.tbuffer.load.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.ptr.tbuffer.store.f16.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.ptr.tbuffer.store.i8.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.ptr.tbuffer.store.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.tbuffer.load.f16.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.tbuffer.load.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.tbuffer.store.f16.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.tbuffer.store.i8.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.tbuffer.store.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.rsq.clamp.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.s.buffer.load.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.s.setreg.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.s.sleep.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.sbfe.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.sdot2.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.sdot4.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.sdot8.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.set.inactive.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.softwqm.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.buffer.atomic.add.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.buffer.atomic.cmpswap.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.buffer.atomic.fadd-with-ret.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.buffer.atomic.fadd.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.buffer.load.format.f16.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.buffer.load.format.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.buffer.load.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.buffer.load.tfe.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.buffer.store.format.f16.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.buffer.store.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.ptr.buffer.atomic.add.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.ptr.buffer.atomic.cmpswap.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.ptr.buffer.atomic.fadd-with-ret.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.ptr.buffer.atomic.fadd.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.ptr.buffer.load.format.f16.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.ptr.buffer.load.format.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.ptr.buffer.load.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.ptr.buffer.store.format.f16.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.ptr.buffer.store.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.ptr.tbuffer.load.f16.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.ptr.tbuffer.load.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.tbuffer.load.f16.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.tbuffer.load.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.sudot4.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.sudot8.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.ubfe.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.udot2.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.udot4.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.udot8.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.update.dpp.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.wmma_32.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.wmma_64.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.workitem.id.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.wqm.demote.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.wqm.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.writelane.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.wwm.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.memcpy.inline.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.memcpy.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.memmove.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.memset.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/load-local.128.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/load-local.96.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/load-unaligned.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/localizer-wrong-insert-point.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/merge-buffer-stores.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/mul-known-bits.i64.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/mul-known-bits.i64.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/mul.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/non-entry-alloca.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/postlegalizer-combiner-buildvector-identities.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/postlegalizer-combiner-divrem.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/postlegalizer-combiner-fcanonicalize.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/postlegalizer-combiner-freeze.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/postlegalizer-combiner-reassoc.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/postlegalizer-combiner-sextload-from-sextinreg.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/postlegalizer-combiner-trunc-bitcast-buildvector.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/postlegalizer-combiner-unmerge-undef.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/postlegalizer-combiner-zextload-from-and.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/postlegalizercombiner-and.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/postlegalizercombiner-ashr.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/postlegalizercombiner-load-and-mask.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/postlegalizercombiner-lshr.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/postlegalizercombiner-mul.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/postlegalizercombiner-sbfx.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/postlegalizercombiner-select.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/postlegalizercombiner-shl.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/postlegalizercombiner-ubfx.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/prelegalizer-combiner-divrem.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/prelegalizer-combiner-redundant-bitcast.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/prelegalizer-combiner-sext_inreg-to-and.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/prelegalizer-combiner-shuffle.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankcombiner-clamp-fmed3-const.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankcombiner-clamp-minmax-const.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankcombiner-fmed3-minmax-const.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankcombiner-redundant-and.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankcombiner-smed3.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankcombiner-umed3.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-abs.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-add.s16.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-add.s32.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-add.v2s16.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn-exp-compr.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn-exp.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn-s-buffer-load.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.ballot.i64.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.class.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.cvt.pkrtz.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.div.fmas.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.div.scale.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.ds.append.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.ds.bpermute.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.ds.consume.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.ds.gws.init.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.ds.gws.sema.v.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.ds.ordered.add.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.ds.ordered.swap.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.ds.permute.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.ds.swizzle.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.else.32.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.else.64.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.fcmp.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.fmul.legacy.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.groupstaticsize.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.icmp.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.interp.mov.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.interp.p1.f16.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.interp.p1.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.interp.p2.f16.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.interp.p2.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.kernarg.segment.ptr.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.kill.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.lds.direct.load.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.lds.param.load.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.live.mask.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.mfma.gfx90a.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.mfma.gfx942.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.mfma.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.ps.live.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.readfirstlane.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.readlane.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.s.get.waveid.in.workgroup.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.s.getpc.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.s.getreg.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.s.memrealtime.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.s.memtime.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.s.sendmsg.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.s.sendmsghalt.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.update.dpp.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.wqm.demote.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.wqm.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.wqm.vote.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.writelane.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.wwm.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgpu-ffbh-u32.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgpu-ffbl-b32.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-and-s1.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-and.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-anyext.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-ashr.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-assert-align.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-assert-zext.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-atomic-cmpxchg.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-atomicrmw-add.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-atomicrmw-and.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-atomicrmw-fadd.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-atomicrmw-max.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-atomicrmw-min.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-atomicrmw-or.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-atomicrmw-sub.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-atomicrmw-umax.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-atomicrmw-umin.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-atomicrmw-xchg.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-atomicrmw-xor.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-bitcast.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-bitreverse.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-brcond.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-bswap.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-build-vector.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-concat-vector.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-constant.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-copy.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-ctlz-zero-undef.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-ctpop.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-cttz-zero-undef.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-dyn-stackalloc.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-extract-vector-elt.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-extract.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fabs.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fadd.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fcanonicalize.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fceil.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fcmp.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fexp2.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-flog2.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fma.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fmul.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fneg.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fpext.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fptosi.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fptoui.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fptrunc.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-frame-index.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fshr.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fsqrt.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fsub.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-icmp.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-icmp.s16.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-implicit-def.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-insert-vector-elt.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-insert.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-intrinsic-trunc.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-inttoptr.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-load.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-lshr.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-mad_64_32.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-merge-values.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-mui-regbanklegalize.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-mui-regbankselect.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-mui-salu-float.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-mui.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-mul.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-or.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-phi-s1.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-phi.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-pseudo-scalar-transcendental.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-ptr-add.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-ptrmask.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-ptrtoint.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-reg-sequence.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-sadde.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-salu-float.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-sbfx.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-select.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-sext-inreg.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-sext.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-sextload.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-shl.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-sitofp.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-smax.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-smin.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-smulh.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-ssube.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-sub.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-trunc.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-uadde.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-uaddo.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-ubfx.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-uitofp.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-umax.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-umin.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-umulh.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-uniform-load-noclobber.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-unmerge-values.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-usube.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-usubo.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-waterfall-agpr.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-whole-wave-functions.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-widen-scalar-loads.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-xor.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-zext.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-zextload.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/sdivrem.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/select-to-fmin-fmax.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/shader-epilogs.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/shl-ext-reduce.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/shlN_add.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/shufflevector.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/smed3.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/smrd.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/store-local.128.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/store-local.96.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/subo.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/trunc.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/udivrem.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/umed3.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/v_bfe_i32.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/widen-i8-i16-scalar-loads.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/wmma-gfx12-w32-f16-f32-matrix-modifiers.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/wmma-gfx12-w32-imm.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/wmma-gfx12-w32-iu-modifiers.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/wmma-gfx12-w32-swmmac-index_key.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/wmma-gfx12-w32.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/wmma-gfx12-w64-f16-f32-matrix-modifiers.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/wmma-gfx12-w64-imm.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/wmma-gfx12-w64-iu-modifiers.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/wmma-gfx12-w64-swmmac-index_key.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/wmma-gfx12-w64.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/xnor.ll
    M llvm/test/CodeGen/AMDGPU/InlineAsmCrash.ll
    M llvm/test/CodeGen/AMDGPU/acc-ldst.ll
    M llvm/test/CodeGen/AMDGPU/accvgpr-copy.mir
    M llvm/test/CodeGen/AMDGPU/accvgpr-spill-scc-clobber.mir
    M llvm/test/CodeGen/AMDGPU/add.i16.ll
    M llvm/test/CodeGen/AMDGPU/add.ll
    M llvm/test/CodeGen/AMDGPU/add.v2i16.ll
    M llvm/test/CodeGen/AMDGPU/add3.ll
    M llvm/test/CodeGen/AMDGPU/add_i1.ll
    M llvm/test/CodeGen/AMDGPU/add_i128.ll
    M llvm/test/CodeGen/AMDGPU/add_i64.ll
    M llvm/test/CodeGen/AMDGPU/add_shl.ll
    M llvm/test/CodeGen/AMDGPU/addrspacecast-initializer-unsupported.ll
    M llvm/test/CodeGen/AMDGPU/addrspacecast-initializer.ll
    M llvm/test/CodeGen/AMDGPU/adjust-writemask-invalid-copy.ll
    M llvm/test/CodeGen/AMDGPU/adjust-writemask-vectorized.ll
    M llvm/test/CodeGen/AMDGPU/agpr-copy-no-vgprs.mir
    M llvm/test/CodeGen/AMDGPU/agpr-copy-propagation.mir
    M llvm/test/CodeGen/AMDGPU/agpr-copy-reuse-writes.mir
    M llvm/test/CodeGen/AMDGPU/agpr-copy-sgpr-no-vgprs.mir
    M llvm/test/CodeGen/AMDGPU/agpr-csr.ll
    M llvm/test/CodeGen/AMDGPU/agpr-register-count.ll
    M llvm/test/CodeGen/AMDGPU/agpr-remat.ll
    M llvm/test/CodeGen/AMDGPU/agpr-to-agpr-copy.mir
    M llvm/test/CodeGen/AMDGPU/alignbit-pat.ll
    M llvm/test/CodeGen/AMDGPU/alloc-aligned-tuples-gfx1250.mir
    M llvm/test/CodeGen/AMDGPU/alloc-aligned-tuples-gfx908.mir
    M llvm/test/CodeGen/AMDGPU/alloc-aligned-tuples-gfx90a.mir
    M llvm/test/CodeGen/AMDGPU/alloc-all-regs-reserved-in-class.mir
    M llvm/test/CodeGen/AMDGPU/always-uniform.ll
    M llvm/test/CodeGen/AMDGPU/amd.endpgm.ll
    M llvm/test/CodeGen/AMDGPU/amdgcn-ieee.ll
    M llvm/test/CodeGen/AMDGPU/amdgcn-load-offset-from-reg.ll
    M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.1024bit.ll
    M llvm/test/CodeGen/AMDGPU/amdgcn.private-memory.ll
    M llvm/test/CodeGen/AMDGPU/amdgpu-cs-chain-cc.ll
    M llvm/test/CodeGen/AMDGPU/amdgpu-cs-chain-preserve-cc.ll
    M llvm/test/CodeGen/AMDGPU/amdgpu-mul24-knownbits.ll
    M llvm/test/CodeGen/AMDGPU/amdgpu-nsa-threshold.ll
    M llvm/test/CodeGen/AMDGPU/amdgpu-reloc-const.ll
    M llvm/test/CodeGen/AMDGPU/amdgpu-shader-calling-convention.ll
    M llvm/test/CodeGen/AMDGPU/amdgpu.private-memory.ll
    M llvm/test/CodeGen/AMDGPU/amdgpu.work-item-intrinsics.deprecated.ll
    M llvm/test/CodeGen/AMDGPU/amdpal-callable.ll
    M llvm/test/CodeGen/AMDGPU/amdpal-cs.ll
    M llvm/test/CodeGen/AMDGPU/amdpal-es.ll
    M llvm/test/CodeGen/AMDGPU/amdpal-gs.ll
    M llvm/test/CodeGen/AMDGPU/amdpal-hs.ll
    M llvm/test/CodeGen/AMDGPU/amdpal-ls.ll
    M llvm/test/CodeGen/AMDGPU/amdpal-msgpack-cs.ll
    M llvm/test/CodeGen/AMDGPU/amdpal-msgpack-default.ll
    M llvm/test/CodeGen/AMDGPU/amdpal-msgpack-denormal.ll
    M llvm/test/CodeGen/AMDGPU/amdpal-msgpack-dx10-clamp.ll
    M llvm/test/CodeGen/AMDGPU/amdpal-msgpack-es.ll
    M llvm/test/CodeGen/AMDGPU/amdpal-msgpack-gs.ll
    M llvm/test/CodeGen/AMDGPU/amdpal-msgpack-hs.ll
    M llvm/test/CodeGen/AMDGPU/amdpal-msgpack-ieee.ll
    M llvm/test/CodeGen/AMDGPU/amdpal-msgpack-ls.ll
    M llvm/test/CodeGen/AMDGPU/amdpal-msgpack-ps.ll
    M llvm/test/CodeGen/AMDGPU/amdpal-msgpack-psenable.ll
    M llvm/test/CodeGen/AMDGPU/amdpal-msgpack-vs.ll
    M llvm/test/CodeGen/AMDGPU/amdpal-ps.ll
    M llvm/test/CodeGen/AMDGPU/amdpal-psenable.ll
    M llvm/test/CodeGen/AMDGPU/amdpal-usersgpr-init.ll
    M llvm/test/CodeGen/AMDGPU/amdpal-vs.ll
    M llvm/test/CodeGen/AMDGPU/amdpal_scratch_mergedshader.ll
    M llvm/test/CodeGen/AMDGPU/and-gcn.ll
    M llvm/test/CodeGen/AMDGPU/and.ll
    M llvm/test/CodeGen/AMDGPU/and_or.ll
    M llvm/test/CodeGen/AMDGPU/andorbitset.ll
    M llvm/test/CodeGen/AMDGPU/andorn2.ll
    M llvm/test/CodeGen/AMDGPU/andorxorinvimm.ll
    M llvm/test/CodeGen/AMDGPU/any_extend_vector_inreg.ll
    M llvm/test/CodeGen/AMDGPU/anyext.ll
    M llvm/test/CodeGen/AMDGPU/are-loads-from-same-base-ptr.ll
    M llvm/test/CodeGen/AMDGPU/array-ptr-calc-i32.ll
    M llvm/test/CodeGen/AMDGPU/array-ptr-calc-i64.ll
    M llvm/test/CodeGen/AMDGPU/artificial-terminators.mir
    M llvm/test/CodeGen/AMDGPU/ashr.v2i16.ll
    M llvm/test/CodeGen/AMDGPU/asm-printer-check-vcc.mir
    M llvm/test/CodeGen/AMDGPU/at-least-one-def-value-assert.mir
    M llvm/test/CodeGen/AMDGPU/atomic_cmp_swap_local.ll
    M llvm/test/CodeGen/AMDGPU/atomic_load_add.ll
    M llvm/test/CodeGen/AMDGPU/atomic_load_local.ll
    M llvm/test/CodeGen/AMDGPU/atomic_load_sub.ll
    M llvm/test/CodeGen/AMDGPU/atomic_optimizations_buffer.ll
    M llvm/test/CodeGen/AMDGPU/atomic_optimizations_global_pointer.ll
    M llvm/test/CodeGen/AMDGPU/atomic_optimizations_pixelshader.ll
    M llvm/test/CodeGen/AMDGPU/atomic_optimizations_raw_buffer.ll
    M llvm/test/CodeGen/AMDGPU/atomic_optimizations_struct_buffer.ll
    M llvm/test/CodeGen/AMDGPU/atomic_store_local.ll
    M llvm/test/CodeGen/AMDGPU/atomicrmw-expand.ll
    M llvm/test/CodeGen/AMDGPU/atomicrmw-nand.ll
    M llvm/test/CodeGen/AMDGPU/atomics-cas-remarks-gfx90a.ll
    M llvm/test/CodeGen/AMDGPU/atomics-hw-remarks-gfx90a.ll
    M llvm/test/CodeGen/AMDGPU/atomics_cond_sub.ll
    M llvm/test/CodeGen/AMDGPU/attr-amdgpu-flat-work-group-size-vgpr-limit.ll
    M llvm/test/CodeGen/AMDGPU/attr-amdgpu-flat-work-group-size.ll
    M llvm/test/CodeGen/AMDGPU/attr-amdgpu-num-sgpr.ll
    M llvm/test/CodeGen/AMDGPU/attr-amdgpu-num-vgpr.ll
    M llvm/test/CodeGen/AMDGPU/attr-amdgpu-waves-per-eu.ll
    M llvm/test/CodeGen/AMDGPU/attr-unparseable.ll
    M llvm/test/CodeGen/AMDGPU/av-spill-expansion-with-machine-cp.mir
    M llvm/test/CodeGen/AMDGPU/av_spill_cross_bb_usage.mir
    M llvm/test/CodeGen/AMDGPU/back-off-barrier-subtarget-feature.ll
    M llvm/test/CodeGen/AMDGPU/basic-branch.ll
    M llvm/test/CodeGen/AMDGPU/basic-call-return.ll
    M llvm/test/CodeGen/AMDGPU/basic-loop.ll
    M llvm/test/CodeGen/AMDGPU/bb-prolog-spill-during-regalloc.ll
    M llvm/test/CodeGen/AMDGPU/bfe-patterns.ll
    M llvm/test/CodeGen/AMDGPU/bfi_int.ll
    M llvm/test/CodeGen/AMDGPU/bfi_nested.ll
    M llvm/test/CodeGen/AMDGPU/bfm.ll
    M llvm/test/CodeGen/AMDGPU/bitcast-constant-to-vector.ll
    M llvm/test/CodeGen/AMDGPU/bitcast-v4f16-v4i16.ll
    M llvm/test/CodeGen/AMDGPU/bitcast-vector-extract.ll
    M llvm/test/CodeGen/AMDGPU/bitreverse-inline-immediates.ll
    M llvm/test/CodeGen/AMDGPU/bitreverse.ll
    M llvm/test/CodeGen/AMDGPU/block-should-not-be-in-alive-blocks.mir
    M llvm/test/CodeGen/AMDGPU/br_cc.f16.ll
    M llvm/test/CodeGen/AMDGPU/branch-relax-bundle.ll
    M llvm/test/CodeGen/AMDGPU/branch-relax-indirect-branch.mir
    M llvm/test/CodeGen/AMDGPU/branch-relax-no-terminators.mir
    M llvm/test/CodeGen/AMDGPU/branch-relax-spill.ll
    M llvm/test/CodeGen/AMDGPU/branch-relaxation-gfx10-branch-offset-bug.ll
    M llvm/test/CodeGen/AMDGPU/branch-relaxation-inst-size-gfx10.ll
    M llvm/test/CodeGen/AMDGPU/branch-relaxation.ll
    M llvm/test/CodeGen/AMDGPU/branch-uniformity.ll
    M llvm/test/CodeGen/AMDGPU/break-smem-soft-clauses.mir
    M llvm/test/CodeGen/AMDGPU/break-vmem-soft-clauses.mir
    M llvm/test/CodeGen/AMDGPU/bswap.ll
    M llvm/test/CodeGen/AMDGPU/buffer-atomic-fadd.f32-no-rtn.ll
    M llvm/test/CodeGen/AMDGPU/buffer-atomic-fadd.f32-rtn.ll
    M llvm/test/CodeGen/AMDGPU/buffer-atomic-fadd.f64.ll
    M llvm/test/CodeGen/AMDGPU/buffer-atomic-fadd.v2f16-no-rtn.ll
    M llvm/test/CodeGen/AMDGPU/buffer-atomic-fadd.v2f16-rtn.ll
    M llvm/test/CodeGen/AMDGPU/buffer-intrinsics-mmo-offsets.ll
    M llvm/test/CodeGen/AMDGPU/buffer-rsrc-ptr-ops.ll
    M llvm/test/CodeGen/AMDGPU/buffer-schedule.ll
    M llvm/test/CodeGen/AMDGPU/bug-deadlanes.ll
    M llvm/test/CodeGen/AMDGPU/bug-sdag-scheduler-cycle.ll
    M llvm/test/CodeGen/AMDGPU/bug-v4f64-subvector.ll
    M llvm/test/CodeGen/AMDGPU/build-vector-insert-elt-infloop.ll
    M llvm/test/CodeGen/AMDGPU/build-vector-packed-partial-undef.ll
    M llvm/test/CodeGen/AMDGPU/bundle-latency.mir
    M llvm/test/CodeGen/AMDGPU/byval-frame-setup.ll
    M llvm/test/CodeGen/AMDGPU/call-args-inreg-no-sgpr-for-csrspill-xfail.ll
    M llvm/test/CodeGen/AMDGPU/call-argument-types.ll
    M llvm/test/CodeGen/AMDGPU/call-c-function.ll
    M llvm/test/CodeGen/AMDGPU/call-constexpr.ll
    M llvm/test/CodeGen/AMDGPU/call-encoding.ll
    M llvm/test/CodeGen/AMDGPU/call-graph-register-usage.ll
    M llvm/test/CodeGen/AMDGPU/call-preserved-registers.ll
    M llvm/test/CodeGen/AMDGPU/call-return-types.ll
    M llvm/test/CodeGen/AMDGPU/call-waw-waitcnt.mir
    M llvm/test/CodeGen/AMDGPU/callee-frame-setup.ll
    M llvm/test/CodeGen/AMDGPU/calling-conventions.ll
    M llvm/test/CodeGen/AMDGPU/captured-frame-index.ll
    M llvm/test/CodeGen/AMDGPU/carryout-selection.ll
    M llvm/test/CodeGen/AMDGPU/cc-sgpr-limit.ll
    M llvm/test/CodeGen/AMDGPU/cc-sgpr-over-limit.ll
    M llvm/test/CodeGen/AMDGPU/cf-loop-on-constant.ll
    M llvm/test/CodeGen/AMDGPU/cgp-bitfield-extract.ll
    M llvm/test/CodeGen/AMDGPU/chain-hi-to-lo.ll
    M llvm/test/CodeGen/AMDGPU/change-scc-to-vcc.mir
    M llvm/test/CodeGen/AMDGPU/clamp-modifier.ll
    M llvm/test/CodeGen/AMDGPU/clamp-omod-special-case.mir
    M llvm/test/CodeGen/AMDGPU/clamp.ll
    M llvm/test/CodeGen/AMDGPU/cluster-flat-loads-postra.mir
    M llvm/test/CodeGen/AMDGPU/cluster_stores.ll
    M llvm/test/CodeGen/AMDGPU/cmp_shrink.mir
    M llvm/test/CodeGen/AMDGPU/cndmask-no-def-vcc.ll
    M llvm/test/CodeGen/AMDGPU/coalesce-identity-copies-undef-subregs.mir
    M llvm/test/CodeGen/AMDGPU/coalesce-vgpr-alignment.ll
    M llvm/test/CodeGen/AMDGPU/coalescer-early-clobber-subreg.mir
    M llvm/test/CodeGen/AMDGPU/coalescer-removepartial-extend-undef-subrange.mir
    M llvm/test/CodeGen/AMDGPU/coalescer-subranges-prune-kill-copy.mir
    M llvm/test/CodeGen/AMDGPU/coalescer-subregjoin-fullcopy.mir
    M llvm/test/CodeGen/AMDGPU/coalescer_remat.ll
    M llvm/test/CodeGen/AMDGPU/coalescing-subreg-was-undef-but-became-def.mir
    M llvm/test/CodeGen/AMDGPU/coalescing_makes_lanes_undef.mir
    M llvm/test/CodeGen/AMDGPU/codegen-prepare-addrmode-sext.ll
    M llvm/test/CodeGen/AMDGPU/collapse-endcf-broken.mir
    M llvm/test/CodeGen/AMDGPU/collapse-endcf.ll
    M llvm/test/CodeGen/AMDGPU/collapse-endcf.mir
    M llvm/test/CodeGen/AMDGPU/collapse-endcf2.mir
    M llvm/test/CodeGen/AMDGPU/combine-add-zext-xor.ll
    M llvm/test/CodeGen/AMDGPU/combine-and-sext-bool.ll
    M llvm/test/CodeGen/AMDGPU/combine-cond-add-sub.ll
    M llvm/test/CodeGen/AMDGPU/combine-ftrunc.ll
    M llvm/test/CodeGen/AMDGPU/combine-sreg64-inits.mir
    M llvm/test/CodeGen/AMDGPU/combine-vload-extract.ll
    M llvm/test/CodeGen/AMDGPU/combine_andor_with_cmps.ll
    M llvm/test/CodeGen/AMDGPU/commute-compares-scalar-float.ll
    M llvm/test/CodeGen/AMDGPU/commute-compares.ll
    M llvm/test/CodeGen/AMDGPU/commute-frame-index-operand.mir
    M llvm/test/CodeGen/AMDGPU/commute-op-sel.mir
    M llvm/test/CodeGen/AMDGPU/commute-shifts.ll
    M llvm/test/CodeGen/AMDGPU/commute-vop3.mir
    M llvm/test/CodeGen/AMDGPU/commute_modifiers.ll
    M llvm/test/CodeGen/AMDGPU/computeKnownBits-scalar-to-vector-crash.ll
    M llvm/test/CodeGen/AMDGPU/concat_vectors.ll
    M llvm/test/CodeGen/AMDGPU/constant-fold-imm-immreg.mir
    M llvm/test/CodeGen/AMDGPU/constant-fold-mi-operands.ll
    M llvm/test/CodeGen/AMDGPU/control-flow-fastregalloc.ll
    M llvm/test/CodeGen/AMDGPU/control-flow-optnone.ll
    M llvm/test/CodeGen/AMDGPU/convergence-tokens.ll
    M llvm/test/CodeGen/AMDGPU/convergent-inlineasm.ll
    M llvm/test/CodeGen/AMDGPU/copy-overlap-sgpr-kill.mir
    M llvm/test/CodeGen/AMDGPU/copy-overlap-vgpr-kill.mir
    M llvm/test/CodeGen/AMDGPU/copy-phys-reg-implicit-operand-kills-subregs.mir
    M llvm/test/CodeGen/AMDGPU/copy-vgpr-clobber-spill-vgpr.mir
    M llvm/test/CodeGen/AMDGPU/copy_phys_vgpr64.mir
    M llvm/test/CodeGen/AMDGPU/copy_to_scc.ll
    M llvm/test/CodeGen/AMDGPU/copyprop_regsequence_with_undef.mir
    M llvm/test/CodeGen/AMDGPU/couldnt-join-subrange-3.mir
    M llvm/test/CodeGen/AMDGPU/cross-block-use-is-not-abi-copy.ll
    M llvm/test/CodeGen/AMDGPU/cse-convergent.ll
    M llvm/test/CodeGen/AMDGPU/cse-phi-incoming-val.ll
    M llvm/test/CodeGen/AMDGPU/csr-sgpr-spill-live-ins.mir
    M llvm/test/CodeGen/AMDGPU/ctlz.ll
    M llvm/test/CodeGen/AMDGPU/ctlz_zero_undef.ll
    M llvm/test/CodeGen/AMDGPU/ctpop.ll
    M llvm/test/CodeGen/AMDGPU/ctpop16.ll
    M llvm/test/CodeGen/AMDGPU/ctpop64.ll
    M llvm/test/CodeGen/AMDGPU/cttz.ll
    M llvm/test/CodeGen/AMDGPU/cttz_zero_undef.ll
    M llvm/test/CodeGen/AMDGPU/cube.ll
    M llvm/test/CodeGen/AMDGPU/cvt_f32_ubyte.ll
    M llvm/test/CodeGen/AMDGPU/cvt_flr_i32_f32.ll
    M llvm/test/CodeGen/AMDGPU/cvt_rpi_i32_f32.ll
    M llvm/test/CodeGen/AMDGPU/dag-divergence.ll
    M llvm/test/CodeGen/AMDGPU/dagcomb-shuffle-vecextend-non2.ll
    M llvm/test/CodeGen/AMDGPU/dagcombine-fma-fmad.ll
    M llvm/test/CodeGen/AMDGPU/dagcombine-lshr-and-cmp.ll
    M llvm/test/CodeGen/AMDGPU/dagcombine-reassociate-bug.ll
    M llvm/test/CodeGen/AMDGPU/dagcombine-select.ll
    M llvm/test/CodeGen/AMDGPU/dagcombine-setcc-select.ll
    M llvm/test/CodeGen/AMDGPU/dbg-value-ends-sched-region.mir
    M llvm/test/CodeGen/AMDGPU/dce-disjoint-intervals.mir
    M llvm/test/CodeGen/AMDGPU/dead-lane.mir
    M llvm/test/CodeGen/AMDGPU/dead_bundle.mir
    M llvm/test/CodeGen/AMDGPU/dead_copy.mir
    M llvm/test/CodeGen/AMDGPU/debug-value-scheduler-crash.mir
    M llvm/test/CodeGen/AMDGPU/debug-value.ll
    M llvm/test/CodeGen/AMDGPU/debug-value2.ll
    M llvm/test/CodeGen/AMDGPU/debug.ll
    M llvm/test/CodeGen/AMDGPU/default-fp-mode.ll
    M llvm/test/CodeGen/AMDGPU/disable_form_clauses.ll
    M llvm/test/CodeGen/AMDGPU/div_v2i128.ll
    M llvm/test/CodeGen/AMDGPU/diverge-extra-formal-args.ll
    M llvm/test/CodeGen/AMDGPU/diverge-interp-mov-lower.ll
    M llvm/test/CodeGen/AMDGPU/divergence-driven-bfe-isel.ll
    M llvm/test/CodeGen/AMDGPU/divergent-branch-uniform-condition.ll
    M llvm/test/CodeGen/AMDGPU/dpp64_combine.ll
    M llvm/test/CodeGen/AMDGPU/dpp64_combine.mir
    M llvm/test/CodeGen/AMDGPU/dpp_combine-true16.mir
    M llvm/test/CodeGen/AMDGPU/dpp_combine.ll
    M llvm/test/CodeGen/AMDGPU/dpp_combine.mir
    M llvm/test/CodeGen/AMDGPU/dpp_combine_gfx11.mir
    M llvm/test/CodeGen/AMDGPU/drop-mem-operand-move-smrd.ll
    M llvm/test/CodeGen/AMDGPU/ds-combine-large-stride.ll
    M llvm/test/CodeGen/AMDGPU/ds-combine-with-dependence.ll
    M llvm/test/CodeGen/AMDGPU/ds-negative-offset-addressing-mode-loop.ll
    M llvm/test/CodeGen/AMDGPU/ds-sub-offset.ll
    M llvm/test/CodeGen/AMDGPU/ds-vectorization-alignment.ll
    M llvm/test/CodeGen/AMDGPU/ds_gws_align.ll
    M llvm/test/CodeGen/AMDGPU/ds_read2.ll
    M llvm/test/CodeGen/AMDGPU/ds_read2_offset_order.ll
    M llvm/test/CodeGen/AMDGPU/ds_read2_superreg.ll
    M llvm/test/CodeGen/AMDGPU/ds_read2st64.ll
    M llvm/test/CodeGen/AMDGPU/ds_write2.ll
    M llvm/test/CodeGen/AMDGPU/ds_write2st64.ll
    M llvm/test/CodeGen/AMDGPU/dual-source-blend-export.ll
    M llvm/test/CodeGen/AMDGPU/early-if-convert-cost.ll
    M llvm/test/CodeGen/AMDGPU/early-if-convert.ll
    M llvm/test/CodeGen/AMDGPU/early-lis-two-address-partial-def.mir
    M llvm/test/CodeGen/AMDGPU/early-tailduplicator-nophis.mir
    M llvm/test/CodeGen/AMDGPU/early-tailduplicator-terminator.mir
    M llvm/test/CodeGen/AMDGPU/early-term.mir
    M llvm/test/CodeGen/AMDGPU/elf.ll
    M llvm/test/CodeGen/AMDGPU/eliminate-frame-index-s-add-i32.mir
    M llvm/test/CodeGen/AMDGPU/eliminate-frame-index-s-add-u32.mir
    M llvm/test/CodeGen/AMDGPU/eliminate-frame-index-s-mov-b32.mir
    M llvm/test/CodeGen/AMDGPU/eliminate-frame-index-scalar-bit-ops.mir
    M llvm/test/CodeGen/AMDGPU/eliminate-frame-index-v-add-co-u32-wave32.mir
    M llvm/test/CodeGen/AMDGPU/eliminate-frame-index-v-add-co-u32.mir
    M llvm/test/CodeGen/AMDGPU/eliminate-frame-index-v-add-u32.mir
    M llvm/test/CodeGen/AMDGPU/else.ll
    M llvm/test/CodeGen/AMDGPU/empty-function.ll
    M llvm/test/CodeGen/AMDGPU/endcf-loop-header.ll
    M llvm/test/CodeGen/AMDGPU/endpgm-dce.mir
    M llvm/test/CodeGen/AMDGPU/exceed-max-sgprs.ll
    M llvm/test/CodeGen/AMDGPU/expand-atomicrmw-syncscope.ll
    M llvm/test/CodeGen/AMDGPU/extend-bit-ops-i16.ll
    M llvm/test/CodeGen/AMDGPU/extend-wwm-virt-reg-liveness.mir
    M llvm/test/CodeGen/AMDGPU/extload-align.ll
    M llvm/test/CodeGen/AMDGPU/extload-private.ll
    M llvm/test/CodeGen/AMDGPU/extload.ll
    M llvm/test/CodeGen/AMDGPU/extract-lowbits.ll
    M llvm/test/CodeGen/AMDGPU/extract-subvector-16bit.ll
    M llvm/test/CodeGen/AMDGPU/extract-subvector-equal-length.ll
    M llvm/test/CodeGen/AMDGPU/extract-subvector.ll
    M llvm/test/CodeGen/AMDGPU/extract-vector-elt-build-vector-combine.ll
    M llvm/test/CodeGen/AMDGPU/extract_vector_elt-f16.ll
    M llvm/test/CodeGen/AMDGPU/extract_vector_elt-f64.ll
    M llvm/test/CodeGen/AMDGPU/extract_vector_elt-i16.ll
    M llvm/test/CodeGen/AMDGPU/extract_vector_elt-i64.ll
    M llvm/test/CodeGen/AMDGPU/extractelt-to-trunc.ll
    M llvm/test/CodeGen/AMDGPU/fabs.f16.ll
    M llvm/test/CodeGen/AMDGPU/fabs.f64.ll
    M llvm/test/CodeGen/AMDGPU/fadd-fma-fmul-combine.ll
    M llvm/test/CodeGen/AMDGPU/fadd.f16.ll
    M llvm/test/CodeGen/AMDGPU/fadd.ll
    M llvm/test/CodeGen/AMDGPU/fadd64.ll
    M llvm/test/CodeGen/AMDGPU/fast-ra-kills-vcc.mir
    M llvm/test/CodeGen/AMDGPU/fast-regalloc-bundles.mir
    M llvm/test/CodeGen/AMDGPU/fastregalloc-illegal-subreg-physreg.mir
    M llvm/test/CodeGen/AMDGPU/fastregalloc-self-loop-heuristic.mir
    M llvm/test/CodeGen/AMDGPU/fcanonicalize-elimination.ll
    M llvm/test/CodeGen/AMDGPU/fcanonicalize.f16.ll
    M llvm/test/CodeGen/AMDGPU/fcanonicalize.ll
    M llvm/test/CodeGen/AMDGPU/fceil.ll
    M llvm/test/CodeGen/AMDGPU/fceil64.ll
    M llvm/test/CodeGen/AMDGPU/fcmp.f16.ll
    M llvm/test/CodeGen/AMDGPU/fcmp64.ll
    M llvm/test/CodeGen/AMDGPU/fconst64.ll
    M llvm/test/CodeGen/AMDGPU/fdiv.f16.ll
    M llvm/test/CodeGen/AMDGPU/fdiv.f64.ll
    M llvm/test/CodeGen/AMDGPU/fdot2.ll
    M llvm/test/CodeGen/AMDGPU/fence-barrier.ll
    M llvm/test/CodeGen/AMDGPU/fence-lds-read2-write2.ll
    M llvm/test/CodeGen/AMDGPU/ffloor.f64.ll
    M llvm/test/CodeGen/AMDGPU/ffloor.ll
    M llvm/test/CodeGen/AMDGPU/finalize-isel-kill-scc-vcc.mir
    M llvm/test/CodeGen/AMDGPU/fix-frame-ptr-reg-copy-livein.ll
    M llvm/test/CodeGen/AMDGPU/fix-frame-reg-in-custom-csr-spills.ll
    M llvm/test/CodeGen/AMDGPU/fix-sgpr-copies-f16-fake16.mir
    M llvm/test/CodeGen/AMDGPU/fix-sgpr-copies-f16-gfx12-fake16.mir
    M llvm/test/CodeGen/AMDGPU/fix-sgpr-copies-f16-gfx12-true16.mir
    M llvm/test/CodeGen/AMDGPU/fix-sgpr-copies-f16-true16.mir
    M llvm/test/CodeGen/AMDGPU/fix-sgpr-copies-f16.mir
    M llvm/test/CodeGen/AMDGPU/fix-sgpr-copies.mir
    M llvm/test/CodeGen/AMDGPU/fix-wwm-vgpr-copy.ll
    M llvm/test/CodeGen/AMDGPU/flat-atomic-fadd.f32.ll
    M llvm/test/CodeGen/AMDGPU/flat-atomic-fadd.f64.ll
    M llvm/test/CodeGen/AMDGPU/flat-load-clustering.mir
    M llvm/test/CodeGen/AMDGPU/flat-offset-bug.ll
    M llvm/test/CodeGen/AMDGPU/flat-scratch-fold-fi.mir
    M llvm/test/CodeGen/AMDGPU/flat-scratch-i8-i16.ll
    M llvm/test/CodeGen/AMDGPU/fma-combine.ll
    M llvm/test/CodeGen/AMDGPU/fma.f16.ll
    M llvm/test/CodeGen/AMDGPU/fma.f64.ll
    M llvm/test/CodeGen/AMDGPU/fma.ll
    M llvm/test/CodeGen/AMDGPU/fmac.sdwa.ll
    M llvm/test/CodeGen/AMDGPU/fmax3.f64.ll
    M llvm/test/CodeGen/AMDGPU/fmax3.ll
    M llvm/test/CodeGen/AMDGPU/fmax_legacy.f16.ll
    M llvm/test/CodeGen/AMDGPU/fmax_legacy.ll
    M llvm/test/CodeGen/AMDGPU/fmed3.ll
    M llvm/test/CodeGen/AMDGPU/fmin3.ll
    M llvm/test/CodeGen/AMDGPU/fmin_legacy.f16.ll
    M llvm/test/CodeGen/AMDGPU/fmin_legacy.ll
    M llvm/test/CodeGen/AMDGPU/fmul-2-combine-multi-use.ll
    M llvm/test/CodeGen/AMDGPU/fmul.f16.ll
    M llvm/test/CodeGen/AMDGPU/fmul64.ll
    M llvm/test/CodeGen/AMDGPU/fmuladd.f16.ll
    M llvm/test/CodeGen/AMDGPU/fmuladd.f32.ll
    M llvm/test/CodeGen/AMDGPU/fmuladd.f64.ll
    M llvm/test/CodeGen/AMDGPU/fmuladd.v2f16.ll
    M llvm/test/CodeGen/AMDGPU/fnearbyint.ll
    M llvm/test/CodeGen/AMDGPU/fneg-combines-gfx1200.ll
    M llvm/test/CodeGen/AMDGPU/fneg-combines.si.ll
    M llvm/test/CodeGen/AMDGPU/fneg-fabs.f16.ll
    M llvm/test/CodeGen/AMDGPU/fneg.f16.ll
    M llvm/test/CodeGen/AMDGPU/fneg.f64.ll
    M llvm/test/CodeGen/AMDGPU/fold-agpr-phis.mir
    M llvm/test/CodeGen/AMDGPU/fold-cndmask-wave32.mir
    M llvm/test/CodeGen/AMDGPU/fold-cndmask.mir
    M llvm/test/CodeGen/AMDGPU/fold-commute-sgpr.mir
    M llvm/test/CodeGen/AMDGPU/fold-fabs.ll
    M llvm/test/CodeGen/AMDGPU/fold-fi-mubuf.mir
    M llvm/test/CodeGen/AMDGPU/fold-fi-operand-shrink.mir
    M llvm/test/CodeGen/AMDGPU/fold-fmaak-bug.ll
    M llvm/test/CodeGen/AMDGPU/fold-fmul-to-neg-abs.ll
    M llvm/test/CodeGen/AMDGPU/fold-imm-copy.mir
    M llvm/test/CodeGen/AMDGPU/fold-imm-f16-f32.mir
    M llvm/test/CodeGen/AMDGPU/fold-immediate-operand-shrink-with-carry.mir
    M llvm/test/CodeGen/AMDGPU/fold-immediate-operand-shrink.mir
    M llvm/test/CodeGen/AMDGPU/fold-immediate-output-mods.mir
    M llvm/test/CodeGen/AMDGPU/fold-implicit-operand.mir
    M llvm/test/CodeGen/AMDGPU/fold-int-pow2-with-fmul-or-fdiv.ll
    M llvm/test/CodeGen/AMDGPU/fold-multiple-commute.mir
    M llvm/test/CodeGen/AMDGPU/fold-multiple.mir
    M llvm/test/CodeGen/AMDGPU/fold-omod-crash.mir
    M llvm/test/CodeGen/AMDGPU/fold-operands-frame-index.gfx10.mir
    M llvm/test/CodeGen/AMDGPU/fold-operands-frame-index.mir
    M llvm/test/CodeGen/AMDGPU/fold-operands-order.mir
    M llvm/test/CodeGen/AMDGPU/fold-operands-remove-m0-redef.mir
    M llvm/test/CodeGen/AMDGPU/fold-operands-s-add-copy-to-vgpr.mir
    M llvm/test/CodeGen/AMDGPU/fold-operands-scalar-fmac.mir
    M llvm/test/CodeGen/AMDGPU/fold-over-exec.mir
    M llvm/test/CodeGen/AMDGPU/fold-readlane.mir
    M llvm/test/CodeGen/AMDGPU/fold-reload-into-exec.mir
    M llvm/test/CodeGen/AMDGPU/fold-reload-into-m0.mir
    M llvm/test/CodeGen/AMDGPU/fold-sgpr-copy.mir
    M llvm/test/CodeGen/AMDGPU/fold-sgpr-multi-imm.mir
    M llvm/test/CodeGen/AMDGPU/fold-short-64-bit-literals.mir
    M llvm/test/CodeGen/AMDGPU/fold-vgpr-copy.mir
    M llvm/test/CodeGen/AMDGPU/fold-vgpr-phyreg.mir
    M llvm/test/CodeGen/AMDGPU/fold-zero-high-bits-clear-kill-flags.mir
    M llvm/test/CodeGen/AMDGPU/fold_acc_copy_into_valu.mir
    M llvm/test/CodeGen/AMDGPU/folding-of-i32-as-i64.mir
    M llvm/test/CodeGen/AMDGPU/force-wait-after-always-gds.mir
    M llvm/test/CodeGen/AMDGPU/fp-atomic-to-s_denormmode.mir
    M llvm/test/CodeGen/AMDGPU/fp-classify.ll
    M llvm/test/CodeGen/AMDGPU/fp-min-max-buffer-atomics.ll
    M llvm/test/CodeGen/AMDGPU/fp-min-max-buffer-ptr-atomics.ll
    M llvm/test/CodeGen/AMDGPU/fp-min-max-image-atomics.ll
    M llvm/test/CodeGen/AMDGPU/fp-min-max-num-flat-atomics.ll
    M llvm/test/CodeGen/AMDGPU/fp-min-max-num-global-atomics.ll
    M llvm/test/CodeGen/AMDGPU/fp16_to_fp32.ll
    M llvm/test/CodeGen/AMDGPU/fp16_to_fp64.ll
    M llvm/test/CodeGen/AMDGPU/fp32_to_fp16.ll
    M llvm/test/CodeGen/AMDGPU/fp64-min-max-buffer-atomics.ll
    M llvm/test/CodeGen/AMDGPU/fp64-min-max-buffer-ptr-atomics.ll
    M llvm/test/CodeGen/AMDGPU/fp_to_sint.f64.ll
    M llvm/test/CodeGen/AMDGPU/fp_to_sint.ll
    M llvm/test/CodeGen/AMDGPU/fp_to_uint.f64.ll
    M llvm/test/CodeGen/AMDGPU/fp_to_uint.ll
    M llvm/test/CodeGen/AMDGPU/fpext-free.ll
    M llvm/test/CodeGen/AMDGPU/fpext.f16.ll
    M llvm/test/CodeGen/AMDGPU/fpext.ll
    M llvm/test/CodeGen/AMDGPU/fptosi.f16.ll
    M llvm/test/CodeGen/AMDGPU/fptoui.f16.ll
    M llvm/test/CodeGen/AMDGPU/fptrunc.f16.ll
    M llvm/test/CodeGen/AMDGPU/fptrunc.ll
    M llvm/test/CodeGen/AMDGPU/fract.f64.ll
    M llvm/test/CodeGen/AMDGPU/fract.ll
    M llvm/test/CodeGen/AMDGPU/frame-index-elimination.ll
    M llvm/test/CodeGen/AMDGPU/frame-index.mir
    M llvm/test/CodeGen/AMDGPU/frame-lowering-entry-all-sgpr-used.mir
    M llvm/test/CodeGen/AMDGPU/frame-lowering-fp-adjusted.mir
    M llvm/test/CodeGen/AMDGPU/frame-setup-without-sgpr-to-vgpr-spills.ll
    M llvm/test/CodeGen/AMDGPU/frem.ll
    M llvm/test/CodeGen/AMDGPU/fshl.ll
    M llvm/test/CodeGen/AMDGPU/fshr.ll
    M llvm/test/CodeGen/AMDGPU/fsqrt.f64.ll
    M llvm/test/CodeGen/AMDGPU/fsub.f16.ll
    M llvm/test/CodeGen/AMDGPU/fsub.ll
    M llvm/test/CodeGen/AMDGPU/fsub64.ll
    M llvm/test/CodeGen/AMDGPU/function-args.ll
    M llvm/test/CodeGen/AMDGPU/function-returns.ll
    M llvm/test/CodeGen/AMDGPU/fused-bitlogic.ll
    M llvm/test/CodeGen/AMDGPU/gds-allocation.ll
    M llvm/test/CodeGen/AMDGPU/gds-atomic.ll
    M llvm/test/CodeGen/AMDGPU/gep-address-space.ll
    M llvm/test/CodeGen/AMDGPU/gfx-call-non-gfx-func.ll
    M llvm/test/CodeGen/AMDGPU/gfx-callable-argument-types.ll
    M llvm/test/CodeGen/AMDGPU/gfx-callable-preserved-registers.ll
    M llvm/test/CodeGen/AMDGPU/gfx-callable-return-types.ll
    M llvm/test/CodeGen/AMDGPU/gfx10-twoaddr-fma.mir
    M llvm/test/CodeGen/AMDGPU/gfx10-vop-literal.ll
    M llvm/test/CodeGen/AMDGPU/gfx11-twoaddr-fma.mir
    M llvm/test/CodeGen/AMDGPU/gfx12_scalar_subword_loads.ll
    M llvm/test/CodeGen/AMDGPU/gfx90a-enc.ll
    M llvm/test/CodeGen/AMDGPU/gfx942-hazards.mir
    M llvm/test/CodeGen/AMDGPU/global-address.ll
    M llvm/test/CodeGen/AMDGPU/global-atomic-fadd.f32-no-rtn.ll
    M llvm/test/CodeGen/AMDGPU/global-atomic-fadd.f32-rtn.ll
    M llvm/test/CodeGen/AMDGPU/global-constant.ll
    M llvm/test/CodeGen/AMDGPU/global-directive.ll
    M llvm/test/CodeGen/AMDGPU/global-extload-i16.ll
    M llvm/test/CodeGen/AMDGPU/global-i16-load-store.ll
    M llvm/test/CodeGen/AMDGPU/global-load-saddr-to-vaddr.ll
    M llvm/test/CodeGen/AMDGPU/global_atomics.ll
    M llvm/test/CodeGen/AMDGPU/global_atomics_i32_system.ll
    M llvm/test/CodeGen/AMDGPU/global_atomics_i64.ll
    M llvm/test/CodeGen/AMDGPU/global_atomics_i64_system.ll
    M llvm/test/CodeGen/AMDGPU/global_atomics_scan_fmax.ll
    M llvm/test/CodeGen/AMDGPU/global_atomics_scan_fmin.ll
    M llvm/test/CodeGen/AMDGPU/global_atomics_scan_fsub.ll
    M llvm/test/CodeGen/AMDGPU/global_smrd.ll
    M llvm/test/CodeGen/AMDGPU/global_smrd_cfg.ll
    M llvm/test/CodeGen/AMDGPU/greedy-broken-ssa-verifier-error.mir
    M llvm/test/CodeGen/AMDGPU/greedy-global-heuristic.mir
    M llvm/test/CodeGen/AMDGPU/gv-const-addrspace.ll
    M llvm/test/CodeGen/AMDGPU/gws-hazards.mir
    M llvm/test/CodeGen/AMDGPU/half.ll
    M llvm/test/CodeGen/AMDGPU/hard-clause-limit-attr.mir
    M llvm/test/CodeGen/AMDGPU/hard-clause-limit.mir
    M llvm/test/CodeGen/AMDGPU/hard-clauses-img-gfx10.mir
    M llvm/test/CodeGen/AMDGPU/hard-clauses-img-gfx11.mir
    M llvm/test/CodeGen/AMDGPU/hard-clauses-img-gfx12.mir
    M llvm/test/CodeGen/AMDGPU/hard-clauses.mir
    M llvm/test/CodeGen/AMDGPU/hazard-buffer-store-v-interp.mir
    M llvm/test/CodeGen/AMDGPU/hazard-flat-instruction-valu-check.mir
    M llvm/test/CodeGen/AMDGPU/hazard-hidden-bundle.mir
    M llvm/test/CodeGen/AMDGPU/hazard-in-bundle.mir
    M llvm/test/CodeGen/AMDGPU/hazard-inlineasm.mir
    M llvm/test/CodeGen/AMDGPU/hazard-kill.mir
    M llvm/test/CodeGen/AMDGPU/hazard-pseudo-machineinstrs.mir
    M llvm/test/CodeGen/AMDGPU/hazard-shift64.mir
    M llvm/test/CodeGen/AMDGPU/hazard.mir
    M llvm/test/CodeGen/AMDGPU/hazards-gfx950.mir
    M llvm/test/CodeGen/AMDGPU/hip.extern.shared.array.ll
    M llvm/test/CodeGen/AMDGPU/hoist-cond.ll
    M llvm/test/CodeGen/AMDGPU/hsa-fp-mode.ll
    M llvm/test/CodeGen/AMDGPU/hsa-metadata-agpr-register-count.ll
    M llvm/test/CodeGen/AMDGPU/huge-number-operand-folds.mir
    M llvm/test/CodeGen/AMDGPU/huge-private-buffer.ll
    M llvm/test/CodeGen/AMDGPU/i1-copies-rpo.mir
    M llvm/test/CodeGen/AMDGPU/i1-copy-from-loop.ll
    M llvm/test/CodeGen/AMDGPU/i1-copy-implicit-def.ll
    M llvm/test/CodeGen/AMDGPU/i1-copy-phi-uniform-branch.ll
    M llvm/test/CodeGen/AMDGPU/i1-copy-phi.ll
    M llvm/test/CodeGen/AMDGPU/i1_copy_phi_with_phi_incoming_value.mir
    M llvm/test/CodeGen/AMDGPU/icmp.i16.ll
    M llvm/test/CodeGen/AMDGPU/icmp64.ll
    M llvm/test/CodeGen/AMDGPU/idemponent-atomics.ll
    M llvm/test/CodeGen/AMDGPU/idiv-licm.ll
    M llvm/test/CodeGen/AMDGPU/illegal-sgpr-to-vgpr-copy.ll
    M llvm/test/CodeGen/AMDGPU/image-load-d16-tfe.ll
    M llvm/test/CodeGen/AMDGPU/image-sample-waterfall.ll
    M llvm/test/CodeGen/AMDGPU/image-schedule.ll
    M llvm/test/CodeGen/AMDGPU/img-nouse-adjust.ll
    M llvm/test/CodeGen/AMDGPU/imm.ll
    M llvm/test/CodeGen/AMDGPU/imm16.ll
    M llvm/test/CodeGen/AMDGPU/immv216.ll
    M llvm/test/CodeGen/AMDGPU/implicit-def-muse.ll
    M llvm/test/CodeGen/AMDGPU/indirect-addressing-si-gfx9.ll
    M llvm/test/CodeGen/AMDGPU/indirect-addressing-term.ll
    M llvm/test/CodeGen/AMDGPU/indirect-call.ll
    M llvm/test/CodeGen/AMDGPU/indirect-private-64.ll
    M llvm/test/CodeGen/AMDGPU/infinite-loop.ll
    M llvm/test/CodeGen/AMDGPU/inflate-reg-class-vgpr-mfma-to-av-with-load-source.mir
    M llvm/test/CodeGen/AMDGPU/inflate-reg-class-vgpr-mfma-to-av.mir
    M llvm/test/CodeGen/AMDGPU/inline-asm-reserved-regs.ll
    M llvm/test/CodeGen/AMDGPU/inline-asm.ll
    M llvm/test/CodeGen/AMDGPU/inline-calls.ll
    M llvm/test/CodeGen/AMDGPU/inline-constraints.ll
    M llvm/test/CodeGen/AMDGPU/inlineasm-16.ll
    M llvm/test/CodeGen/AMDGPU/inlineasm-illegal-type.ll
    M llvm/test/CodeGen/AMDGPU/inlineasm-packed.ll
    M llvm/test/CodeGen/AMDGPU/inlineasm-v16.ll
    M llvm/test/CodeGen/AMDGPU/insert-branch-w32.mir
    M llvm/test/CodeGen/AMDGPU/insert-delay-alu-bug.ll
    M llvm/test/CodeGen/AMDGPU/insert-delay-alu-literal.mir
    M llvm/test/CodeGen/AMDGPU/insert-delay-alu-parse.mir
    M llvm/test/CodeGen/AMDGPU/insert-delay-alu.mir
    M llvm/test/CodeGen/AMDGPU/insert-handle-flat-vmem-ds.mir
    M llvm/test/CodeGen/AMDGPU/insert-skip-from-vcc.mir
    M llvm/test/CodeGen/AMDGPU/insert-skips-gfx10.mir
    M llvm/test/CodeGen/AMDGPU/insert-skips-gfx12.mir
    M llvm/test/CodeGen/AMDGPU/insert-skips-gws.mir
    M llvm/test/CodeGen/AMDGPU/insert-subvector-unused-scratch.ll
    M llvm/test/CodeGen/AMDGPU/insert-waitcnts-callee.mir
    M llvm/test/CodeGen/AMDGPU/insert-waitcnts-crash.ll
    M llvm/test/CodeGen/AMDGPU/insert-waitcnts-exp.mir
    M llvm/test/CodeGen/AMDGPU/insert_subreg.ll
    M llvm/test/CodeGen/AMDGPU/insert_vector_elt.v2bf16.ll
    M llvm/test/CodeGen/AMDGPU/insert_vector_elt.v2i16.ll
    M llvm/test/CodeGen/AMDGPU/insert_vector_elt.v2i16.subtest-nosaddr.ll
    M llvm/test/CodeGen/AMDGPU/insert_vector_elt.v2i16.subtest-saddr.ll
    M llvm/test/CodeGen/AMDGPU/invariant-load-no-alias-store.ll
    M llvm/test/CodeGen/AMDGPU/invert-br-undef-vcc.mir
    M llvm/test/CodeGen/AMDGPU/ipra-return-address-save-restore.ll
    M llvm/test/CodeGen/AMDGPU/ipra.ll
    M llvm/test/CodeGen/AMDGPU/irtranslator-whole-wave-functions.ll
    M llvm/test/CodeGen/AMDGPU/isel-amdgcn-cs-chain-intrinsic-w32.ll
    M llvm/test/CodeGen/AMDGPU/isel-amdgcn-cs-chain-intrinsic-w64.ll
    M llvm/test/CodeGen/AMDGPU/isel-amdgpu-cs-chain-cc.ll
    M llvm/test/CodeGen/AMDGPU/isel-amdgpu-cs-chain-intrinsic-dyn-vgpr-w32.ll
    M llvm/test/CodeGen/AMDGPU/isel-amdgpu-cs-chain-preserve-cc.ll
    M llvm/test/CodeGen/AMDGPU/issue48473.mir
    M llvm/test/CodeGen/AMDGPU/issue92561-restore-undef-scc-verifier-error.ll
    M llvm/test/CodeGen/AMDGPU/issue98474-assigned-physreg-interference.mir
    M llvm/test/CodeGen/AMDGPU/issue98474-need-live-out-undef-subregister-def.ll
    M llvm/test/CodeGen/AMDGPU/issue98474-virtregrewriter-live-out-undef-subregisters.mir
    M llvm/test/CodeGen/AMDGPU/kernarg-stack-alignment.ll
    M llvm/test/CodeGen/AMDGPU/kernel-args.ll
    M llvm/test/CodeGen/AMDGPU/kernel-argument-dag-lowering.ll
    M llvm/test/CodeGen/AMDGPU/kernel-mubuf-with-voffset.mir
    M llvm/test/CodeGen/AMDGPU/kernel-vgpr-spill-mubuf-with-voffset.ll
    M llvm/test/CodeGen/AMDGPU/kill-infinite-loop.ll
    M llvm/test/CodeGen/AMDGPU/known-never-nan.ll
    M llvm/test/CodeGen/AMDGPU/known-never-snan.ll
    M llvm/test/CodeGen/AMDGPU/lds-bounds.ll
    M llvm/test/CodeGen/AMDGPU/lds-branch-vmem-hazard.mir
    M llvm/test/CodeGen/AMDGPU/lds-direct-hazards-gfx11.mir
    M llvm/test/CodeGen/AMDGPU/lds-direct-hazards-gfx12.mir
    M llvm/test/CodeGen/AMDGPU/lds-dma-hazards.mir
    M llvm/test/CodeGen/AMDGPU/lds-dma-waitcnt.mir
    M llvm/test/CodeGen/AMDGPU/lds-frame-extern.ll
    M llvm/test/CodeGen/AMDGPU/lds-global-non-entry-func.ll
    M llvm/test/CodeGen/AMDGPU/lds-m0-init-in-loop.ll
    M llvm/test/CodeGen/AMDGPU/lds-misaligned-bug.ll
    M llvm/test/CodeGen/AMDGPU/lds-oqap-crash.ll
    M llvm/test/CodeGen/AMDGPU/lds-output-queue.ll
    M llvm/test/CodeGen/AMDGPU/lds-relocs.ll
    M llvm/test/CodeGen/AMDGPU/lds-size-hsa-gfx950.ll
    M llvm/test/CodeGen/AMDGPU/lds-size-pal-gfx950.ll
    M llvm/test/CodeGen/AMDGPU/lds-zero-initializer.ll
    M llvm/test/CodeGen/AMDGPU/legalize-amdgcn.raw.buffer.load.format.f16.ll
    M llvm/test/CodeGen/AMDGPU/legalize-amdgcn.raw.buffer.load.format.ll
    M llvm/test/CodeGen/AMDGPU/legalize-amdgcn.raw.buffer.load.ll
    M llvm/test/CodeGen/AMDGPU/legalize-amdgcn.raw.buffer.store.format.f16.ll
    M llvm/test/CodeGen/AMDGPU/legalize-amdgcn.raw.buffer.store.format.f32.ll
    M llvm/test/CodeGen/AMDGPU/legalize-amdgcn.raw.buffer.store.ll
    M llvm/test/CodeGen/AMDGPU/legalize-amdgcn.raw.ptr.buffer.load.format.f16.ll
    M llvm/test/CodeGen/AMDGPU/legalize-amdgcn.raw.ptr.buffer.load.format.ll
    M llvm/test/CodeGen/AMDGPU/legalize-amdgcn.raw.ptr.buffer.load.ll
    M llvm/test/CodeGen/AMDGPU/legalize-amdgcn.raw.ptr.buffer.store.format.f16.ll
    M llvm/test/CodeGen/AMDGPU/legalize-amdgcn.raw.ptr.buffer.store.format.f32.ll
    M llvm/test/CodeGen/AMDGPU/legalize-amdgcn.raw.ptr.buffer.store.ll
    M llvm/test/CodeGen/AMDGPU/legalize-amdgcn.raw.ptr.tbuffer.load.f16.ll
    M llvm/test/CodeGen/AMDGPU/legalize-amdgcn.raw.ptr.tbuffer.load.ll
    M llvm/test/CodeGen/AMDGPU/legalize-amdgcn.raw.ptr.tbuffer.store.f16.ll
    M llvm/test/CodeGen/AMDGPU/legalize-amdgcn.raw.ptr.tbuffer.store.ll
    M llvm/test/CodeGen/AMDGPU/legalize-amdgcn.raw.tbuffer.load.f16.ll
    M llvm/test/CodeGen/AMDGPU/legalize-amdgcn.raw.tbuffer.load.ll
    M llvm/test/CodeGen/AMDGPU/legalize-amdgcn.raw.tbuffer.store.f16.ll
    M llvm/test/CodeGen/AMDGPU/legalize-amdgcn.raw.tbuffer.store.ll
    M llvm/test/CodeGen/AMDGPU/legalize-fp-load-invariant.ll
    M llvm/test/CodeGen/AMDGPU/legalize-soffset-mbuf.ll
    M llvm/test/CodeGen/AMDGPU/licm-regpressure.mir
    M llvm/test/CodeGen/AMDGPU/licm-valu.mir
    M llvm/test/CodeGen/AMDGPU/limit-soft-clause-reg-pressure.mir
    M llvm/test/CodeGen/AMDGPU/literal-constant-like-operand-instruction-size.ll
    M llvm/test/CodeGen/AMDGPU/liveness.mir
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.alignbyte.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.atomic.cond.sub.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.atomic.dec.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.atomic.inc.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.bitop3.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.bitreplicate.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.buffer.load.dwordx3.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.buffer.store.dwordx3.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.class.f16.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.class.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cos.f16.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cos.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cubeid.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cubema.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cubesc.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cubetc.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.fp8.dpp.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.fp8.dpp.mir
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.fp8.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.pk.i16.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.pk.u16.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.pknorm.i16.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.pknorm.u16.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.pkrtz.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.scalef32.pk.gfx950.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.scalef32.pk.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.scalef32.sr.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.scalef32.sr.pk.gfx950.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.scalef32.sr.pk.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.dispatch.ptr.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.div.fixup.f16.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.div.fixup.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.div.fmas.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.div.scale.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.dot4.f32.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.ds.add.gs.reg.rtn.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.ds.append.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.ds.bpermute.fi.b32.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.ds.bpermute.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.ds.bvh.stack.rtn.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.ds.consume.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.ds.gws.barrier-fastregalloc.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.ds.gws.barrier.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.ds.gws.init.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.ds.gws.sema.br.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.ds.gws.sema.p.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.ds.gws.sema.release.all.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.ds.gws.sema.v.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.ds.ordered.add.gfx10.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.ds.ordered.add.gfx11.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.ds.ordered.add.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.ds.ordered.swap.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.ds.permute.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.ds.read.tr.gfx950.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.ds.sub.gs.reg.rtn.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.ds.swizzle.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.dual_intersect_ray.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.exp.compr.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.exp.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.exp.prim.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.exp.row.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.fcmp.w32.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.fcmp.w64.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.fdiv.fast.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.fdot2.bf16.bf16.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.fdot2.f16.f16.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.fdot2.f32.bf16.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.fdot2.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.fmad.ftz.f16.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.fmad.ftz.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.fmed3.f16.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.fmed3.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.fmul.legacy.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.fract.f16.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.fract.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.frexp.exp.f16.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.frexp.exp.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.frexp.mant.f16.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.frexp.mant.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.global.atomic.csub.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.global.atomic.ordered.add.b64.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.global.load.lds.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.global.load.tr-w32.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.global.load.tr-w64.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.groupstaticsize.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.icmp.w32.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.icmp.w64.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.iglp.opt.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.a16.dim.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.atomic.dim.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.atomic.pk.add.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.d16.dim.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.dim.gfx90a.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.dim.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.gather4.a16.dim.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.gather4.d16.dim.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.gather4.dim.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.gather4.o.dim.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.getlod.dim.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.load.a16.d16.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.load.a16.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.msaa.load.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.msaa.load.x.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.nsa.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.sample.a16.dim.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.sample.cd.a16.dim.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.sample.cd.dim.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.sample.cd.g16.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.sample.d16.dim.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.sample.dim.gfx90a.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.sample.dim.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.sample.g16.a16.dim.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.sample.g16.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.sample.o.dim.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.store.a16.d16.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.store.a16.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.implicit.ptr.buffer.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.implicitarg.ptr.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.init.exec.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.init.exec.wave32.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.init.whole.wave-w32.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.init.whole.wave-w64.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.interp.f16.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.interp.inreg.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.interp.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.intersect_ray.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.inverse.ballot.i32.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.inverse.ballot.i64.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.kernarg.segment.ptr.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.kill.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.lds.direct.load.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.lds.kernel.id.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.lds.param.load.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.lerp.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.load.to.lds.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.log.clamp.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.make.buffer.rsrc.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.mfma.bf16.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.mfma.gfx90a.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.mfma.gfx942.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.mfma.gfx950.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.mfma.i8.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.mfma.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.mfma.xf32.gfx942.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.mov.dpp.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.mov.dpp8.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.mqsad.pk.u16.u8.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.mqsad.u32.u8.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.msad.u8.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.mul.i24.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.mul.u24.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.mulhi.i24.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.mulhi.u24.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.perm.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.permlane.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.permlane.ptr.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.permlane16.var.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.permlane64.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.permlane64.ptr.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.prng.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.ps.live.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.qsad.pk.u16.u8.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.quadmask.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.queue.ptr.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.buffer.atomic.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.buffer.load.format.d16.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.buffer.load.format.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.buffer.load.lds.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.buffer.load.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.buffer.load.tfe.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.buffer.store.format.d16.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.buffer.store.format.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.buffer.store.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.ptr.buffer.atomic.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.ptr.buffer.load.format.d16.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.ptr.buffer.load.format.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.ptr.buffer.load.lds.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.ptr.buffer.load.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.ptr.buffer.store.format.d16.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.ptr.buffer.store.format.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.ptr.buffer.store.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.ptr.tbuffer.load.d16.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.ptr.tbuffer.load.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.ptr.tbuffer.store.d16.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.ptr.tbuffer.store.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.tbuffer.load.d16.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.tbuffer.load.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.tbuffer.store.d16.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.tbuffer.store.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.rcp.f16.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.rcp.legacy.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.rcp.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.readfirstlane.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.readfirstlane.m0.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.readfirstlane.ptr.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.readlane.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.readlane.ptr.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.rsq.clamp.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.rsq.f16.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.rsq.legacy.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.rsq.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.s.barrier.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.s.buffer.load.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.s.decperflevel.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.s.get.waveid.in.workgroup.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.s.getpc.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.s.getreg.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.s.incperflevel.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.s.memrealtime.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.s.memtime.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.s.nop.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.s.sethalt.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.s.setprio.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.s.setreg.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.s.sleep.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.s.sleep.var.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.s.ttracedata.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.s.wait.event.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.s.wait.gfx12.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.s.waitcnt.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.sad.hi.u8.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.sad.u16.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.sad.u8.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.sbfe.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.sched.barrier.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.sched.group.barrier.gfx11.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.sched.group.barrier.iterative.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.sched.group.barrier.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.sdot2.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.sdot4.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.sdot8.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.sendmsg.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.sendmsg.rtn.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.set.inactive.chain.arg.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.set.inactive.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.sffbh.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.sin.f16.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.sin.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.softwqm.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.buffer.atomic.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.buffer.load.format.d16.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.buffer.load.format.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.buffer.load.format.v3f16.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.buffer.load.lds.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.buffer.load.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.buffer.load.tfe.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.buffer.store.format.d16.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.buffer.store.format.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.buffer.store.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.buffer.atomic.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.buffer.load.format.d16.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.buffer.load.format.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.buffer.load.format.v3f16.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.buffer.load.lds.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.buffer.load.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.buffer.store.format.d16.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.buffer.store.format.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.buffer.store.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.tbuffer.load.d16.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.tbuffer.load.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.tbuffer.store.d16.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.tbuffer.store.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.tbuffer.load.d16.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.tbuffer.load.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.tbuffer.store.d16.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.tbuffer.store.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.sudot4.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.sudot8.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.tbuffer.load.dwordx3.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.tbuffer.store.dwordx3.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.trig.preop.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.ubfe.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.udot2.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.udot4.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.udot8.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.update.dpp.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.waitcnt.out.order.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.wave.barrier.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.wave.id.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.wavefrontsize.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.wmma_32.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.wmma_64.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.wqm.demote.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.wqm.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.wqm.vote.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.writelane.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.writelane.ptr.ll
    M llvm/test/CodeGen/AMDGPU/llvm.ceil.f16.ll
    M llvm/test/CodeGen/AMDGPU/llvm.cos.bf16.ll
    M llvm/test/CodeGen/AMDGPU/llvm.cos.f16.ll
    M llvm/test/CodeGen/AMDGPU/llvm.dbg.value.ll
    M llvm/test/CodeGen/AMDGPU/llvm.floor.f16.ll
    M llvm/test/CodeGen/AMDGPU/llvm.fma.f16.ll
    M llvm/test/CodeGen/AMDGPU/llvm.fmuladd.f16.ll
    M llvm/test/CodeGen/AMDGPU/llvm.is.fpclass.ll
    M llvm/test/CodeGen/AMDGPU/llvm.maxnum.f16.ll
    M llvm/test/CodeGen/AMDGPU/llvm.memcpy.ll
    M llvm/test/CodeGen/AMDGPU/llvm.minnum.f16.ll
    M llvm/test/CodeGen/AMDGPU/llvm.mulo.ll
    M llvm/test/CodeGen/AMDGPU/llvm.prefetch.ll
    M llvm/test/CodeGen/AMDGPU/llvm.r600.dot4.ll
    M llvm/test/CodeGen/AMDGPU/llvm.r600.recipsqrt.clamped.ll
    M llvm/test/CodeGen/AMDGPU/llvm.r600.recipsqrt.ieee.ll
    M llvm/test/CodeGen/AMDGPU/llvm.rint.f16.ll
    M llvm/test/CodeGen/AMDGPU/llvm.rint.f64.ll
    M llvm/test/CodeGen/AMDGPU/llvm.rint.ll
    M llvm/test/CodeGen/AMDGPU/llvm.sin.bf16.ll
    M llvm/test/CodeGen/AMDGPU/llvm.sin.f16.ll
    M llvm/test/CodeGen/AMDGPU/llvm.sin.ll
    M llvm/test/CodeGen/AMDGPU/llvm.sqrt.f16.ll
    M llvm/test/CodeGen/AMDGPU/llvm.trunc.f16.ll
    M llvm/test/CodeGen/AMDGPU/lo16-hi16-illegal-copy.mir
    M llvm/test/CodeGen/AMDGPU/lo16-hi16-physreg-copy.mir
    M llvm/test/CodeGen/AMDGPU/lo16-lo16-physreg-copy-agpr.mir
    M llvm/test/CodeGen/AMDGPU/lo16-lo16-physreg-copy-sgpr.mir
    M llvm/test/CodeGen/AMDGPU/load-constant-f32.ll
    M llvm/test/CodeGen/AMDGPU/load-constant-f64.ll
    M llvm/test/CodeGen/AMDGPU/load-constant-i1.ll
    M llvm/test/CodeGen/AMDGPU/load-constant-i16.ll
    M llvm/test/CodeGen/AMDGPU/load-constant-i32.ll
    M llvm/test/CodeGen/AMDGPU/load-constant-i64.ll
    M llvm/test/CodeGen/AMDGPU/load-constant-i8.ll
    M llvm/test/CodeGen/AMDGPU/load-hi16.ll
    M llvm/test/CodeGen/AMDGPU/load-lo16.ll
    M llvm/test/CodeGen/AMDGPU/load-local-f32.ll
    M llvm/test/CodeGen/AMDGPU/load-local-f64.ll
    M llvm/test/CodeGen/AMDGPU/load-local-i1.ll
    M llvm/test/CodeGen/AMDGPU/load-local-i16.ll
    M llvm/test/CodeGen/AMDGPU/load-local-i32.ll
    M llvm/test/CodeGen/AMDGPU/load-local-i64.ll
    M llvm/test/CodeGen/AMDGPU/load-local-i8.ll
    M llvm/test/CodeGen/AMDGPU/load-local-redundant-copies.ll
    M llvm/test/CodeGen/AMDGPU/load-local.128.ll
    M llvm/test/CodeGen/AMDGPU/load-local.96.ll
    M llvm/test/CodeGen/AMDGPU/load-range-metadata-assert.ll
    M llvm/test/CodeGen/AMDGPU/load-select-ptr.ll
    M llvm/test/CodeGen/AMDGPU/load-store-opt-dlc.mir
    M llvm/test/CodeGen/AMDGPU/load-store-opt-scc.mir
    M llvm/test/CodeGen/AMDGPU/load-weird-sizes.ll
    M llvm/test/CodeGen/AMDGPU/local-64.ll
    M llvm/test/CodeGen/AMDGPU/local-atomics.ll
    M llvm/test/CodeGen/AMDGPU/local-atomics64.ll
    M llvm/test/CodeGen/AMDGPU/local-memory.amdgcn.ll
    M llvm/test/CodeGen/AMDGPU/local-memory.ll
    M llvm/test/CodeGen/AMDGPU/local-stack-alloc-add-references.gfx10.mir
    M llvm/test/CodeGen/AMDGPU/local-stack-alloc-add-references.gfx8.mir
    M llvm/test/CodeGen/AMDGPU/local-stack-alloc-add-references.gfx9.mir
    M llvm/test/CodeGen/AMDGPU/local-stack-slot-offset.ll
    M llvm/test/CodeGen/AMDGPU/long-branch-reserve-register.ll
    M llvm/test/CodeGen/AMDGPU/loop-idiom.ll
    M llvm/test/CodeGen/AMDGPU/loop-live-out-copy-undef-subrange.ll
    M llvm/test/CodeGen/AMDGPU/loop-prefetch.ll
    M llvm/test/CodeGen/AMDGPU/loop_break.ll
    M llvm/test/CodeGen/AMDGPU/loop_exit_with_xor.ll
    M llvm/test/CodeGen/AMDGPU/loop_header_nopred.mir
    M llvm/test/CodeGen/AMDGPU/lower-buffer-fat-pointers-nontemporal-metadata.ll
    M llvm/test/CodeGen/AMDGPU/lower-control-flow-live-intervals.mir
    M llvm/test/CodeGen/AMDGPU/lower-control-flow-live-variables-update.mir
    M llvm/test/CodeGen/AMDGPU/lower-control-flow-other-terminators.mir
    M llvm/test/CodeGen/AMDGPU/lower-i1-copies-clear-kills.mir
    M llvm/test/CodeGen/AMDGPU/lower-i1-copies-implicit-def-unstructured-loop.mir
    M llvm/test/CodeGen/AMDGPU/lower-module-lds-offsets.ll
    M llvm/test/CodeGen/AMDGPU/lower-module-lds-via-hybrid.ll
    M llvm/test/CodeGen/AMDGPU/lower-module-lds-via-table.ll
    M llvm/test/CodeGen/AMDGPU/lower-term-opcodes.mir
    M llvm/test/CodeGen/AMDGPU/lower-work-group-id-intrinsics-hsa.ll
    M llvm/test/CodeGen/AMDGPU/lower-work-group-id-intrinsics-pal.ll
    M llvm/test/CodeGen/AMDGPU/lshl-add-u64.ll
    M llvm/test/CodeGen/AMDGPU/lshl64-to-32.ll
    M llvm/test/CodeGen/AMDGPU/lshr.v2i16.ll
    M llvm/test/CodeGen/AMDGPU/machine-scheduler-sink-trivial-remats-attr.mir
    M llvm/test/CodeGen/AMDGPU/machine-scheduler-sink-trivial-remats-debug.mir
    M llvm/test/CodeGen/AMDGPU/machine-scheduler-sink-trivial-remats.mir
    M llvm/test/CodeGen/AMDGPU/machine-sink-ignorable-exec-use.mir
    M llvm/test/CodeGen/AMDGPU/macro-fusion-cluster-vcc-uses.mir
    M llvm/test/CodeGen/AMDGPU/mad-combine.ll
    M llvm/test/CodeGen/AMDGPU/mad-mix-hi.ll
    M llvm/test/CodeGen/AMDGPU/mad-mix-lo.ll
    M llvm/test/CodeGen/AMDGPU/mad-mix.ll
    M llvm/test/CodeGen/AMDGPU/mad.u16.ll
    M llvm/test/CodeGen/AMDGPU/mad24-get-global-id.ll
    M llvm/test/CodeGen/AMDGPU/mad_64_32.ll
    M llvm/test/CodeGen/AMDGPU/mad_int24.ll
    M llvm/test/CodeGen/AMDGPU/mad_u64_u32.ll
    M llvm/test/CodeGen/AMDGPU/mad_uint24.ll
    M llvm/test/CodeGen/AMDGPU/madak-inline-constant.mir
    M llvm/test/CodeGen/AMDGPU/madak.ll
    M llvm/test/CodeGen/AMDGPU/madmk.ll
    M llvm/test/CodeGen/AMDGPU/mai-hazards-gfx90a.mir
    M llvm/test/CodeGen/AMDGPU/mai-hazards-gfx942.mir
    M llvm/test/CodeGen/AMDGPU/mai-hazards-mfma-scale.gfx950.mir
    M llvm/test/CodeGen/AMDGPU/mai-hazards.mir
    M llvm/test/CodeGen/AMDGPU/mai-inline.ll
    M llvm/test/CodeGen/AMDGPU/match-perm-extract-vector-elt-bug.ll
    M llvm/test/CodeGen/AMDGPU/max-sgprs.ll
    M llvm/test/CodeGen/AMDGPU/max.i16.ll
    M llvm/test/CodeGen/AMDGPU/max.ll
    M llvm/test/CodeGen/AMDGPU/mcp-aligned-vgprs.mir
    M llvm/test/CodeGen/AMDGPU/mcp-implicit-clobber.mir
    M llvm/test/CodeGen/AMDGPU/mcp-overlap-after-propagation.mir
    M llvm/test/CodeGen/AMDGPU/mcp-use-before-def.mir
    M llvm/test/CodeGen/AMDGPU/med3-no-simplify.ll
    M llvm/test/CodeGen/AMDGPU/memory_clause.ll
    M llvm/test/CodeGen/AMDGPU/memory_clause.mir
    M llvm/test/CodeGen/AMDGPU/merge-buffer-gfx12.mir
    M llvm/test/CodeGen/AMDGPU/merge-buffer.mir
    M llvm/test/CodeGen/AMDGPU/merge-consecutive-wait-alus.mir
    M llvm/test/CodeGen/AMDGPU/merge-flat-load-store.mir
    M llvm/test/CodeGen/AMDGPU/merge-flat-with-global-load-store.mir
    M llvm/test/CodeGen/AMDGPU/merge-global-load-store.mir
    M llvm/test/CodeGen/AMDGPU/merge-image-load-gfx10.mir
    M llvm/test/CodeGen/AMDGPU/merge-image-load-gfx11.mir
    M llvm/test/CodeGen/AMDGPU/merge-image-load-gfx12.mir
    M llvm/test/CodeGen/AMDGPU/merge-image-load.mir
    M llvm/test/CodeGen/AMDGPU/merge-image-sample-gfx10.mir
    M llvm/test/CodeGen/AMDGPU/merge-image-sample-gfx11.mir
    M llvm/test/CodeGen/AMDGPU/merge-image-sample-gfx12.mir
    M llvm/test/CodeGen/AMDGPU/merge-image-sample.mir
    M llvm/test/CodeGen/AMDGPU/merge-load-store-agpr.mir
    M llvm/test/CodeGen/AMDGPU/merge-load-store-physreg.mir
    M llvm/test/CodeGen/AMDGPU/merge-load-store-vreg.mir
    M llvm/test/CodeGen/AMDGPU/merge-load-store.mir
    M llvm/test/CodeGen/AMDGPU/merge-m0.mir
    M llvm/test/CodeGen/AMDGPU/merge-out-of-order-ldst.ll
    M llvm/test/CodeGen/AMDGPU/merge-out-of-order-ldst.mir
    M llvm/test/CodeGen/AMDGPU/merge-s-load.mir
    M llvm/test/CodeGen/AMDGPU/merge-sbuffer-load.mir
    M llvm/test/CodeGen/AMDGPU/merge-store-crash.ll
    M llvm/test/CodeGen/AMDGPU/merge-store-usedef.ll
    M llvm/test/CodeGen/AMDGPU/merge-stores.ll
    M llvm/test/CodeGen/AMDGPU/merge-tbuffer-gfx10.mir
    M llvm/test/CodeGen/AMDGPU/merge-tbuffer-gfx11.mir
    M llvm/test/CodeGen/AMDGPU/merge-tbuffer-gfx12.mir
    M llvm/test/CodeGen/AMDGPU/merge-tbuffer-gfx9.mir
    M llvm/test/CodeGen/AMDGPU/mesa3d.ll
    M llvm/test/CodeGen/AMDGPU/mesa_regression.ll
    M llvm/test/CodeGen/AMDGPU/mfma-bf16-vgpr-cd-select.ll
    M llvm/test/CodeGen/AMDGPU/mfma-cd-select.ll
    M llvm/test/CodeGen/AMDGPU/mfma-loop.ll
    M llvm/test/CodeGen/AMDGPU/mfma-no-register-aliasing.ll
    M llvm/test/CodeGen/AMDGPU/mfma-vgpr-cd-select-gfx942.ll
    M llvm/test/CodeGen/AMDGPU/mfma-vgpr-cd-select.ll
    M llvm/test/CodeGen/AMDGPU/min-waves-per-eu-not-respected.ll
    M llvm/test/CodeGen/AMDGPU/min.ll
    M llvm/test/CodeGen/AMDGPU/minimummaximum.ll
    M llvm/test/CodeGen/AMDGPU/minmax.ll
    M llvm/test/CodeGen/AMDGPU/misched-killflags.mir
    M llvm/test/CodeGen/AMDGPU/missing-store.ll
    M llvm/test/CodeGen/AMDGPU/mixed-vmem-types.ll
    M llvm/test/CodeGen/AMDGPU/mixed-wave32-wave64.ll
    M llvm/test/CodeGen/AMDGPU/mixed_wave32_wave64.ll
    M llvm/test/CodeGen/AMDGPU/module-lds-false-sharing.ll
    M llvm/test/CodeGen/AMDGPU/move-load-addr-to-valu.mir
    M llvm/test/CodeGen/AMDGPU/move-to-valu-addsubu64.ll
    M llvm/test/CodeGen/AMDGPU/move-to-valu-atomicrmw-system.ll
    M llvm/test/CodeGen/AMDGPU/move-to-valu-atomicrmw.ll
    M llvm/test/CodeGen/AMDGPU/move-to-valu-ctlz-cttz.ll
    M llvm/test/CodeGen/AMDGPU/move-to-valu-lshlrev.mir
    M llvm/test/CodeGen/AMDGPU/move-to-valu-pseudo-scalar-trans-f16-fake16.ll
    M llvm/test/CodeGen/AMDGPU/move-to-valu-pseudo-scalar-trans-f16-true16.ll
    M llvm/test/CodeGen/AMDGPU/move-to-valu-pseudo-scalar-trans.ll
    M llvm/test/CodeGen/AMDGPU/move-to-valu-vimage-vsample.ll
    M llvm/test/CodeGen/AMDGPU/move-to-valu-worklist.ll
    M llvm/test/CodeGen/AMDGPU/movreld-bug.ll
    M llvm/test/CodeGen/AMDGPU/movrels-bug.mir
    M llvm/test/CodeGen/AMDGPU/mubuf-legalize-operands-non-ptr-intrinsics.ll
    M llvm/test/CodeGen/AMDGPU/mubuf-legalize-operands.ll
    M llvm/test/CodeGen/AMDGPU/mubuf-legalize-operands.mir
    M llvm/test/CodeGen/AMDGPU/mubuf-shader-vgpr-non-ptr-intrinsics.ll
    M llvm/test/CodeGen/AMDGPU/mubuf-shader-vgpr.ll
    M llvm/test/CodeGen/AMDGPU/mubuf.ll
    M llvm/test/CodeGen/AMDGPU/mul.i16.ll
    M llvm/test/CodeGen/AMDGPU/mul.ll
    M llvm/test/CodeGen/AMDGPU/mul24-pass-ordering.ll
    M llvm/test/CodeGen/AMDGPU/mul_int24.ll
    M llvm/test/CodeGen/AMDGPU/mul_uint24-amdgcn.ll
    M llvm/test/CodeGen/AMDGPU/multi-divergent-exit-region.ll
    M llvm/test/CodeGen/AMDGPU/multilevel-break.ll
    M llvm/test/CodeGen/AMDGPU/nand.ll
    M llvm/test/CodeGen/AMDGPU/need-fp-from-vgpr-spills.ll
    M llvm/test/CodeGen/AMDGPU/neighboring-mfma-padding.mir
    M llvm/test/CodeGen/AMDGPU/nested-calls.ll
    M llvm/test/CodeGen/AMDGPU/nested-loop-conditions.ll
    M llvm/test/CodeGen/AMDGPU/no-dup-inst-prefetch.ll
    M llvm/test/CodeGen/AMDGPU/no-shrink-extloads.ll
    M llvm/test/CodeGen/AMDGPU/no-source-locations-in-prologue.ll
    M llvm/test/CodeGen/AMDGPU/noclobber-barrier.ll
    M llvm/test/CodeGen/AMDGPU/non-entry-alloca.ll
    M llvm/test/CodeGen/AMDGPU/noop-shader-O0.ll
    M llvm/test/CodeGen/AMDGPU/nor.ll
    M llvm/test/CodeGen/AMDGPU/nsa-reassign.ll
    M llvm/test/CodeGen/AMDGPU/nsa-reassign.mir
    M llvm/test/CodeGen/AMDGPU/nsa-vmem-hazard.mir
    M llvm/test/CodeGen/AMDGPU/nullptr.ll
    M llvm/test/CodeGen/AMDGPU/offset-split-flat.ll
    M llvm/test/CodeGen/AMDGPU/offset-split-global.ll
    M llvm/test/CodeGen/AMDGPU/omod-nsz-flag.mir
    M llvm/test/CodeGen/AMDGPU/omod.ll
    M llvm/test/CodeGen/AMDGPU/opencl-image-metadata.ll
    M llvm/test/CodeGen/AMDGPU/operand-folding.ll
    M llvm/test/CodeGen/AMDGPU/operand-spacing.ll
    M llvm/test/CodeGen/AMDGPU/opt-sgpr-to-vgpr-copy.mir
    M llvm/test/CodeGen/AMDGPU/opt-vgpr-live-range-verifier-error.mir
    M llvm/test/CodeGen/AMDGPU/opt_exec_copy_fold.mir
    M llvm/test/CodeGen/AMDGPU/optimize-compare.ll
    M llvm/test/CodeGen/AMDGPU/optimize-compare.mir
    M llvm/test/CodeGen/AMDGPU/optimize-exec-copies-extra-insts-after-copy.mir
    M llvm/test/CodeGen/AMDGPU/optimize-exec-mask-pre-ra-def-after-use.mir
    M llvm/test/CodeGen/AMDGPU/optimize-exec-mask-pre-ra-loop-phi.mir
    M llvm/test/CodeGen/AMDGPU/optimize-exec-mask-pre-ra-non-empty-but-used-interval.mir
    M llvm/test/CodeGen/AMDGPU/optimize-exec-masking-pre-ra.mir
    M llvm/test/CodeGen/AMDGPU/optimize-exec-masking-strip-terminator-bits.mir
    M llvm/test/CodeGen/AMDGPU/optimize-if-exec-masking.mir
    M llvm/test/CodeGen/AMDGPU/optimize-negated-cond-exec-masking-wave32.mir
    M llvm/test/CodeGen/AMDGPU/optimize-negated-cond-exec-masking.mir
    M llvm/test/CodeGen/AMDGPU/optimize-negated-cond.ll
    M llvm/test/CodeGen/AMDGPU/or.ll
    M llvm/test/CodeGen/AMDGPU/or3.ll
    M llvm/test/CodeGen/AMDGPU/overlapping-tuple-copy-implicit-op-failure.ll
    M llvm/test/CodeGen/AMDGPU/pack.v2f16.ll
    M llvm/test/CodeGen/AMDGPU/pack.v2i16.ll
    M llvm/test/CodeGen/AMDGPU/packed-fp32.ll
    M llvm/test/CodeGen/AMDGPU/pal-metadata-3.0-callable-dvgpr.ll
    M llvm/test/CodeGen/AMDGPU/pal-metadata-3.0-callable.ll
    M llvm/test/CodeGen/AMDGPU/parallelandifcollapse.ll
    M llvm/test/CodeGen/AMDGPU/partial-forwarding-hazards.mir
    M llvm/test/CodeGen/AMDGPU/partial-regcopy-and-spill-missed-at-regalloc.ll
    M llvm/test/CodeGen/AMDGPU/partial-sgpr-to-vgpr-spills.ll
    M llvm/test/CodeGen/AMDGPU/partial-shift-shrink.ll
    M llvm/test/CodeGen/AMDGPU/partially-dead-super-register-immediate.ll
    M llvm/test/CodeGen/AMDGPU/peephole-fold-imm.mir
    M llvm/test/CodeGen/AMDGPU/peephole-opt-regseq-removal.mir
    M llvm/test/CodeGen/AMDGPU/pei-amdgpu-cs-chain-preserve.mir
    M llvm/test/CodeGen/AMDGPU/pei-amdgpu-cs-chain.mir
    M llvm/test/CodeGen/AMDGPU/pei-build-av-spill.mir
    M llvm/test/CodeGen/AMDGPU/pei-build-spill-partial-agpr.mir
    M llvm/test/CodeGen/AMDGPU/pei-build-spill.mir
    M llvm/test/CodeGen/AMDGPU/pei-reg-scavenger-position.mir
    M llvm/test/CodeGen/AMDGPU/pei-scavenge-sgpr-carry-out.mir
    M llvm/test/CodeGen/AMDGPU/pei-scavenge-sgpr-gfx9.mir
    M llvm/test/CodeGen/AMDGPU/pei-scavenge-sgpr.mir
    M llvm/test/CodeGen/AMDGPU/pei-scavenge-vgpr-spill.mir
    M llvm/test/CodeGen/AMDGPU/pei-vgpr-block-spill-csr.mir
    M llvm/test/CodeGen/AMDGPU/permlane16_opsel.ll
    M llvm/test/CodeGen/AMDGPU/permute.ll
    M llvm/test/CodeGen/AMDGPU/permute_i8.ll
    M llvm/test/CodeGen/AMDGPU/phi-elimination-end-cf.mir
    M llvm/test/CodeGen/AMDGPU/phi-vgpr-input-moveimm.mir
    M llvm/test/CodeGen/AMDGPU/phys-partial-liveness.mir
    M llvm/test/CodeGen/AMDGPU/pk_max_f16_literal.ll
    M llvm/test/CodeGen/AMDGPU/post-ra-sched-kill-bundle-use-inst.mir
    M llvm/test/CodeGen/AMDGPU/post-ra-sched-reset.mir
    M llvm/test/CodeGen/AMDGPU/post-ra-soft-clause-dbg-info.ll
    M llvm/test/CodeGen/AMDGPU/postra-bundle-memops.mir
    M llvm/test/CodeGen/AMDGPU/postra-machine-sink.mir
    M llvm/test/CodeGen/AMDGPU/postra-sink-update-dependency.mir
    M llvm/test/CodeGen/AMDGPU/preload-kernargs.ll
    M llvm/test/CodeGen/AMDGPU/preserve-hi16.ll
    M llvm/test/CodeGen/AMDGPU/preserve-only-inactive-lane.mir
    M llvm/test/CodeGen/AMDGPU/preserve-user-waitcnt.ll
    M llvm/test/CodeGen/AMDGPU/preserve-wwm-copy-dst-reg.ll
    M llvm/test/CodeGen/AMDGPU/private-access-no-objects.ll
    M llvm/test/CodeGen/AMDGPU/prologue-epilogue-markers.ll
    M llvm/test/CodeGen/AMDGPU/promote-alloca-stored-pointer-value.ll
    M llvm/test/CodeGen/AMDGPU/promote-alloca-vector-to-vector.ll
    M llvm/test/CodeGen/AMDGPU/promote-constOffset-to-imm-gfx10.mir
    M llvm/test/CodeGen/AMDGPU/promote-constOffset-to-imm-gfx90a.mir
    M llvm/test/CodeGen/AMDGPU/promote-constOffset-to-imm.ll
    M llvm/test/CodeGen/AMDGPU/promote-constOffset-to-imm.mir
    M llvm/test/CodeGen/AMDGPU/promote-vect3-load.ll
    M llvm/test/CodeGen/AMDGPU/propagate-attributes-bitcast-function.ll
    M llvm/test/CodeGen/AMDGPU/ps-shader-arg-count.ll
    M llvm/test/CodeGen/AMDGPU/pseudo-scalar-transcendental.mir
    M llvm/test/CodeGen/AMDGPU/ptr-buffer-alias-scheduling.ll
    M llvm/test/CodeGen/AMDGPU/r600-constant-array-fixup.ll
    M llvm/test/CodeGen/AMDGPU/r600.bitcast.ll
    M llvm/test/CodeGen/AMDGPU/r600.extract-lowbits.ll
    M llvm/test/CodeGen/AMDGPU/r600.global_atomics.ll
    M llvm/test/CodeGen/AMDGPU/r600.sub.ll
    M llvm/test/CodeGen/AMDGPU/r600.work-item-intrinsics.ll
    M llvm/test/CodeGen/AMDGPU/ra-inserted-scalar-instructions.mir
    M llvm/test/CodeGen/AMDGPU/ran-out-of-registers-error-all-regs-reserved.ll
    M llvm/test/CodeGen/AMDGPU/rcp_iflag.ll
    M llvm/test/CodeGen/AMDGPU/read-register-invalid-subtarget.ll
    M llvm/test/CodeGen/AMDGPU/read-register-invalid-type-i32.ll
    M llvm/test/CodeGen/AMDGPU/read-register-invalid-type-i64.ll
    M llvm/test/CodeGen/AMDGPU/read_register.ll
    M llvm/test/CodeGen/AMDGPU/readcyclecounter.ll
    M llvm/test/CodeGen/AMDGPU/readlane_exec0.mir
    M llvm/test/CodeGen/AMDGPU/readsteadycounter.ll
    M llvm/test/CodeGen/AMDGPU/reassoc-scalar.ll
    M llvm/test/CodeGen/AMDGPU/recursion.ll
    M llvm/test/CodeGen/AMDGPU/reduce-build-vec-ext-to-ext-build-vec.ll
    M llvm/test/CodeGen/AMDGPU/reduce-load-width-alignment.ll
    M llvm/test/CodeGen/AMDGPU/reduce-saveexec.mir
    M llvm/test/CodeGen/AMDGPU/reduce-store-width-alignment.ll
    M llvm/test/CodeGen/AMDGPU/reduction.ll
    M llvm/test/CodeGen/AMDGPU/regalloc-failure-overlapping-insert-assert.mir
    M llvm/test/CodeGen/AMDGPU/regalloc-illegal-eviction-assert.ll
    M llvm/test/CodeGen/AMDGPU/regalloc-undef-copy-fold.mir
    M llvm/test/CodeGen/AMDGPU/regcoalesce-cannot-join-failures.mir
    M llvm/test/CodeGen/AMDGPU/regcoalesce-keep-valid-lanes-implicit-def-bug39602.mir
    M llvm/test/CodeGen/AMDGPU/regcoalescer-resolve-lane-conflict-by-subranges.mir
    M llvm/test/CodeGen/AMDGPU/regcoalescing-remove-partial-redundancy-assert.mir
    M llvm/test/CodeGen/AMDGPU/register-count-comments.ll
    M llvm/test/CodeGen/AMDGPU/register-killed-error-after-alloc-failure1.ll
    M llvm/test/CodeGen/AMDGPU/regpressure_printer.mir
    M llvm/test/CodeGen/AMDGPU/reject-agpr-usage-before-gfx908.ll
    M llvm/test/CodeGen/AMDGPU/rel32.ll
    M llvm/test/CodeGen/AMDGPU/release-vgprs-gfx12-dvgpr.mir
    M llvm/test/CodeGen/AMDGPU/release-vgprs-gfx12.mir
    M llvm/test/CodeGen/AMDGPU/release-vgprs.mir
    M llvm/test/CodeGen/AMDGPU/remaining-virtual-register-operands.ll
    M llvm/test/CodeGen/AMDGPU/remaining-virtual-register-operands.mir
    M llvm/test/CodeGen/AMDGPU/remat-dead-subreg.mir
    M llvm/test/CodeGen/AMDGPU/remat-fp64-constants.ll
    M llvm/test/CodeGen/AMDGPU/remat-smrd.mir
    M llvm/test/CodeGen/AMDGPU/remat-sop.mir
    M llvm/test/CodeGen/AMDGPU/remove-incompatible-extended-image-insts.ll
    M llvm/test/CodeGen/AMDGPU/remove-incompatible-functions.ll
    M llvm/test/CodeGen/AMDGPU/remove-incompatible-gws.ll
    M llvm/test/CodeGen/AMDGPU/remove-incompatible-s-time.ll
    M llvm/test/CodeGen/AMDGPU/remove-incompatible-wave32-feature.ll
    M llvm/test/CodeGen/AMDGPU/remove-register-flags.mir
    M llvm/test/CodeGen/AMDGPU/remove-short-exec-branches-gpr-idx-mode.mir
    M llvm/test/CodeGen/AMDGPU/remove-short-exec-branches-special-instructions.mir
    M llvm/test/CodeGen/AMDGPU/rename-disconnected-bug.ll
    M llvm/test/CodeGen/AMDGPU/rename-independent-subregs-mac-operands.mir
    M llvm/test/CodeGen/AMDGPU/rename-independent-subregs.mir
    M llvm/test/CodeGen/AMDGPU/reserved-reg-in-clause.mir
    M llvm/test/CodeGen/AMDGPU/resource-usage-crash-unhandled-reg.mir
    M llvm/test/CodeGen/AMDGPU/resource-usage-pal.ll
    M llvm/test/CodeGen/AMDGPU/ret.ll
    M llvm/test/CodeGen/AMDGPU/ret_jump.ll
    M llvm/test/CodeGen/AMDGPU/return-with-successors.mir
    M llvm/test/CodeGen/AMDGPU/returnaddress.ll
    M llvm/test/CodeGen/AMDGPU/rewrite-partial-reg-uses-dbg.mir
    M llvm/test/CodeGen/AMDGPU/rewrite-partial-reg-uses-gen.mir
    M llvm/test/CodeGen/AMDGPU/rewrite-partial-reg-uses.mir
    M llvm/test/CodeGen/AMDGPU/rotate-add.ll
    M llvm/test/CodeGen/AMDGPU/rotl.i64.ll
    M llvm/test/CodeGen/AMDGPU/rotl.ll
    M llvm/test/CodeGen/AMDGPU/rotr.i64.ll
    M llvm/test/CodeGen/AMDGPU/rotr.ll
    M llvm/test/CodeGen/AMDGPU/s-getpc-b64-remat.ll
    M llvm/test/CodeGen/AMDGPU/s_add_co_pseudo_lowering.mir
    M llvm/test/CodeGen/AMDGPU/s_addk_i32.ll
    M llvm/test/CodeGen/AMDGPU/s_movk_i32.ll
    M llvm/test/CodeGen/AMDGPU/s_mulk_i32.ll
    M llvm/test/CodeGen/AMDGPU/s_or_saveexec_xor_combine.mir
    M llvm/test/CodeGen/AMDGPU/sad.ll
    M llvm/test/CodeGen/AMDGPU/saddo.ll
    M llvm/test/CodeGen/AMDGPU/salu-to-valu.ll
    M llvm/test/CodeGen/AMDGPU/same-slot-agpr-sgpr.mir
    M llvm/test/CodeGen/AMDGPU/save-fp.ll
    M llvm/test/CodeGen/AMDGPU/scalar-branch-missing-and-exec.ll
    M llvm/test/CodeGen/AMDGPU/scalar-float-sop1.ll
    M llvm/test/CodeGen/AMDGPU/scalar-float-sop2.ll
    M llvm/test/CodeGen/AMDGPU/scalar-float-sopc.ll
    M llvm/test/CodeGen/AMDGPU/scalar_to_vector.ll
    M llvm/test/CodeGen/AMDGPU/scalar_to_vector.v8i16.ll
    M llvm/test/CodeGen/AMDGPU/scalar_to_vector_v2x16.ll
    M llvm/test/CodeGen/AMDGPU/scc-clobbered-sgpr-to-vmem-spill.ll
    M llvm/test/CodeGen/AMDGPU/sched-assert-dead-def-subreg-use-other-subreg.mir
    M llvm/test/CodeGen/AMDGPU/sched-assert-onlydbg-value-empty-region.mir
    M llvm/test/CodeGen/AMDGPU/sched-crash-dbg-value.mir
    M llvm/test/CodeGen/AMDGPU/sched-handleMoveUp-subreg-def-across-subreg-def.mir
    M llvm/test/CodeGen/AMDGPU/sched-prefer-non-mfma.mir
    M llvm/test/CodeGen/AMDGPU/sched-setprio.ll
    M llvm/test/CodeGen/AMDGPU/schedule-avoid-spills.ll
    M llvm/test/CodeGen/AMDGPU/schedule-fs-loop-nested-if.ll
    M llvm/test/CodeGen/AMDGPU/schedule-fs-loop-nested.ll
    M llvm/test/CodeGen/AMDGPU/schedule-fs-loop.ll
    M llvm/test/CodeGen/AMDGPU/schedule-global-loads.ll
    M llvm/test/CodeGen/AMDGPU/schedule-if-2.ll
    M llvm/test/CodeGen/AMDGPU/schedule-if.ll
    M llvm/test/CodeGen/AMDGPU/schedule-ilp-liveness-tracking.mir
    M llvm/test/CodeGen/AMDGPU/schedule-ilp.ll
    M llvm/test/CodeGen/AMDGPU/schedule-ilp.mir
    M llvm/test/CodeGen/AMDGPU/schedule-kernel-arg-loads.ll
    M llvm/test/CodeGen/AMDGPU/schedule-physregdeps.mir
    M llvm/test/CodeGen/AMDGPU/schedule-regpressure-ilp-metric-spills.mir
    M llvm/test/CodeGen/AMDGPU/schedule-regpressure-lds.ll
    M llvm/test/CodeGen/AMDGPU/schedule-regpressure-limit-clustering.ll
    M llvm/test/CodeGen/AMDGPU/schedule-regpressure-limit.ll
    M llvm/test/CodeGen/AMDGPU/schedule-regpressure-limit2.ll
    M llvm/test/CodeGen/AMDGPU/schedule-regpressure-limit3.ll
    M llvm/test/CodeGen/AMDGPU/schedule-regpressure-misched-max-waves.ll
    M llvm/test/CodeGen/AMDGPU/schedule-relaxed-occupancy.ll
    M llvm/test/CodeGen/AMDGPU/schedule-vs-if-nested-loop-failure.ll
    M llvm/test/CodeGen/AMDGPU/schedule-xdl-resource.ll
    M llvm/test/CodeGen/AMDGPU/scheduler-handle-move-bundle.mir
    M llvm/test/CodeGen/AMDGPU/scratch-buffer.ll
    M llvm/test/CodeGen/AMDGPU/scratch-pointer-sink.ll
    M llvm/test/CodeGen/AMDGPU/scratch-simple.ll
    M llvm/test/CodeGen/AMDGPU/sdag-print-divergence.ll
    M llvm/test/CodeGen/AMDGPU/sdiv64.ll
    M llvm/test/CodeGen/AMDGPU/sdwa-cse.mir
    M llvm/test/CodeGen/AMDGPU/sdwa-op64-test.ll
    M llvm/test/CodeGen/AMDGPU/sdwa-ops.mir
    M llvm/test/CodeGen/AMDGPU/sdwa-peephole-instr-gfx10.mir
    M llvm/test/CodeGen/AMDGPU/sdwa-peephole-instr.mir
    M llvm/test/CodeGen/AMDGPU/sdwa-peephole.ll
    M llvm/test/CodeGen/AMDGPU/sdwa-preserve.mir
    M llvm/test/CodeGen/AMDGPU/sdwa-stack.mir
    M llvm/test/CodeGen/AMDGPU/select-constant-cttz.ll
    M llvm/test/CodeGen/AMDGPU/select-fabs-fneg-extract-legacy.ll
    M llvm/test/CodeGen/AMDGPU/select-fabs-fneg-extract.ll
    M llvm/test/CodeGen/AMDGPU/select-i1.ll
    M llvm/test/CodeGen/AMDGPU/select-opt.ll
    M llvm/test/CodeGen/AMDGPU/select-vectors.ll
    M llvm/test/CodeGen/AMDGPU/select.f16.ll
    M llvm/test/CodeGen/AMDGPU/select64.ll
    M llvm/test/CodeGen/AMDGPU/selectcc.ll
    M llvm/test/CodeGen/AMDGPU/sendmsg-m0-hazard.mir
    M llvm/test/CodeGen/AMDGPU/set-gpr-idx-peephole.mir
    M llvm/test/CodeGen/AMDGPU/set-inactive-wwm-overwrite.ll
    M llvm/test/CodeGen/AMDGPU/set_kill_i1_for_floation_point_comparison.ll
    M llvm/test/CodeGen/AMDGPU/setcc-fneg-constant.ll
    M llvm/test/CodeGen/AMDGPU/setcc-limit-load-shrink.ll
    M llvm/test/CodeGen/AMDGPU/setcc-opt.ll
    M llvm/test/CodeGen/AMDGPU/setcc-sext.ll
    M llvm/test/CodeGen/AMDGPU/setcc.ll
    M llvm/test/CodeGen/AMDGPU/setcc64.ll
    M llvm/test/CodeGen/AMDGPU/seto.ll
    M llvm/test/CodeGen/AMDGPU/setuo.ll
    M llvm/test/CodeGen/AMDGPU/sext-divergence-driven-isel.ll
    M llvm/test/CodeGen/AMDGPU/sext-eliminate.ll
    M llvm/test/CodeGen/AMDGPU/sext-in-reg-failure-r600.ll
    M llvm/test/CodeGen/AMDGPU/sext-in-reg.ll
    M llvm/test/CodeGen/AMDGPU/sgpr-control-flow.ll
    M llvm/test/CodeGen/AMDGPU/sgpr-copy-duplicate-operand.ll
    M llvm/test/CodeGen/AMDGPU/sgpr-copy-local-cse.ll
    M llvm/test/CodeGen/AMDGPU/sgpr-copy.ll
    M llvm/test/CodeGen/AMDGPU/sgpr-regalloc-flags.ll
    M llvm/test/CodeGen/AMDGPU/sgpr-spill-dead-frame-in-dbg-value.mir
    M llvm/test/CodeGen/AMDGPU/sgpr-spill-fi-skip-processing-stack-arg-dbg-value.mir
    M llvm/test/CodeGen/AMDGPU/sgpr-spill-incorrect-fi-bookkeeping-bug.ll
    M llvm/test/CodeGen/AMDGPU/sgpr-spill-no-vgprs.ll
    M llvm/test/CodeGen/AMDGPU/sgpr-spill-overlap-wwm-reserve.mir
    M llvm/test/CodeGen/AMDGPU/sgpr-spill-partially-undef.mir
    M llvm/test/CodeGen/AMDGPU/sgpr-spill-to-vmem-scc-clobber.mir
    M llvm/test/CodeGen/AMDGPU/sgpr-spill-update-only-slot-indexes.ll
    M llvm/test/CodeGen/AMDGPU/sgpr-spill-vmem-large-frame.mir
    M llvm/test/CodeGen/AMDGPU/sgpr-spill-wrong-stack-id.mir
    M llvm/test/CodeGen/AMDGPU/sgpr-spill.mir
    M llvm/test/CodeGen/AMDGPU/sgpr-spills-empty-prolog-block.mir
    M llvm/test/CodeGen/AMDGPU/sgpr-spills-split-regalloc.ll
    M llvm/test/CodeGen/AMDGPU/sgpr-to-vreg1-copy.mir
    M llvm/test/CodeGen/AMDGPU/sgprcopies.ll
    M llvm/test/CodeGen/AMDGPU/shader-addr64-nonuniform.ll
    M llvm/test/CodeGen/AMDGPU/shift-and-i128-ubfe.ll
    M llvm/test/CodeGen/AMDGPU/shift-and-i64-ubfe.ll
    M llvm/test/CodeGen/AMDGPU/shift-i128.ll
    M llvm/test/CodeGen/AMDGPU/shift-select.ll
    M llvm/test/CodeGen/AMDGPU/shl.ll
    M llvm/test/CodeGen/AMDGPU/shl.v2i16.ll
    M llvm/test/CodeGen/AMDGPU/shl_add.ll
    M llvm/test/CodeGen/AMDGPU/shl_add_constant.ll
    M llvm/test/CodeGen/AMDGPU/shl_add_ptr.ll
    M llvm/test/CodeGen/AMDGPU/shl_add_ptr_csub.ll
    M llvm/test/CodeGen/AMDGPU/shl_add_ptr_global.ll
    M llvm/test/CodeGen/AMDGPU/shl_or.ll
    M llvm/test/CodeGen/AMDGPU/should-not-hoist-set-inactive.ll
    M llvm/test/CodeGen/AMDGPU/shrink-carry.mir
    M llvm/test/CodeGen/AMDGPU/shrink-i32-kimm.mir
    M llvm/test/CodeGen/AMDGPU/shrink-insts-scalar-bit-ops.mir
    M llvm/test/CodeGen/AMDGPU/shrink-mad-fma-fake16.mir
    M llvm/test/CodeGen/AMDGPU/shrink-mad-fma-gfx10.mir
    M llvm/test/CodeGen/AMDGPU/shrink-mad-fma.mir
    M llvm/test/CodeGen/AMDGPU/shrink-true16.mir
    M llvm/test/CodeGen/AMDGPU/shrink-vop3-carry-out.mir
    M llvm/test/CodeGen/AMDGPU/shufflevector-physreg-copy.ll
    M llvm/test/CodeGen/AMDGPU/si-annotate-cf-kill.ll
    M llvm/test/CodeGen/AMDGPU/si-annotate-cf-noloop.ll
    M llvm/test/CodeGen/AMDGPU/si-annotate-cf-unreachable.ll
    M llvm/test/CodeGen/AMDGPU/si-annotate-cf.ll
    M llvm/test/CodeGen/AMDGPU/si-annotate-cfg-loop-assert.ll
    M llvm/test/CodeGen/AMDGPU/si-fix-sgpr-copies-copy-to-sgpr.mir
    M llvm/test/CodeGen/AMDGPU/si-fold-aligned-agprs.mir
    M llvm/test/CodeGen/AMDGPU/si-fold-aligned-vgprs.mir
    M llvm/test/CodeGen/AMDGPU/si-fold-copy-kills.mir
    M llvm/test/CodeGen/AMDGPU/si-fold-kimm.mir
    M llvm/test/CodeGen/AMDGPU/si-fold-reg-sequence.mir
    M llvm/test/CodeGen/AMDGPU/si-fold-scalar-clamp.mir
    M llvm/test/CodeGen/AMDGPU/si-i1-copies.mir
    M llvm/test/CodeGen/AMDGPU/si-init-whole-wave.mir
    M llvm/test/CodeGen/AMDGPU/si-instr-info-correct-implicit-operands.ll
    M llvm/test/CodeGen/AMDGPU/si-lower-control-flow-kill.ll
    M llvm/test/CodeGen/AMDGPU/si-lower-control-flow-unreachable-block.ll
    M llvm/test/CodeGen/AMDGPU/si-lower-control-flow.mir
    M llvm/test/CodeGen/AMDGPU/si-lower-i1-copies-order-of-phi-incomings.mir
    M llvm/test/CodeGen/AMDGPU/si-lower-i1-copies.mir
    M llvm/test/CodeGen/AMDGPU/si-lower-sgpr-spills-vgpr-lanes-usage.mir
    M llvm/test/CodeGen/AMDGPU/si-lower-sgpr-spills.mir
    M llvm/test/CodeGen/AMDGPU/si-opt-vgpr-liverange-bug-deadlanes.mir
    M llvm/test/CodeGen/AMDGPU/si-pre-allocate-wwm-regs.mir
    M llvm/test/CodeGen/AMDGPU/si-sgpr-spill.ll
    M llvm/test/CodeGen/AMDGPU/si-spill-cf.ll
    M llvm/test/CodeGen/AMDGPU/si-triv-disjoint-mem-access.ll
    M llvm/test/CodeGen/AMDGPU/si-unify-exit-multiple-unreachables.ll
    M llvm/test/CodeGen/AMDGPU/si-unify-exit-return-unreachable.ll
    M llvm/test/CodeGen/AMDGPU/si-vector-hang.ll
    M llvm/test/CodeGen/AMDGPU/sibling-call.ll
    M llvm/test/CodeGen/AMDGPU/sign_extend.ll
    M llvm/test/CodeGen/AMDGPU/sink-after-control-flow-postra.mir
    M llvm/test/CodeGen/AMDGPU/sink-after-control-flow.mir
    M llvm/test/CodeGen/AMDGPU/sink-image-sample.ll
    M llvm/test/CodeGen/AMDGPU/sint_to_fp.f64.ll
    M llvm/test/CodeGen/AMDGPU/sint_to_fp.i64.ll
    M llvm/test/CodeGen/AMDGPU/sint_to_fp.ll
    M llvm/test/CodeGen/AMDGPU/sitofp.f16.ll
    M llvm/test/CodeGen/AMDGPU/skip-branch-taildup-ret.mir
    M llvm/test/CodeGen/AMDGPU/skip-branch-trap.ll
    M llvm/test/CodeGen/AMDGPU/skip-fold-regsequence.mir
    M llvm/test/CodeGen/AMDGPU/skip-if-dead.ll
    M llvm/test/CodeGen/AMDGPU/smed3.ll
    M llvm/test/CodeGen/AMDGPU/smem-no-clause-coalesced.mir
    M llvm/test/CodeGen/AMDGPU/smem-war-hazard.mir
    M llvm/test/CodeGen/AMDGPU/smfmac_no_agprs.ll
    M llvm/test/CodeGen/AMDGPU/sminmax.ll
    M llvm/test/CodeGen/AMDGPU/smrd-gfx10.ll
    M llvm/test/CodeGen/AMDGPU/smrd-vccz-bug.ll
    M llvm/test/CodeGen/AMDGPU/smrd.ll
    M llvm/test/CodeGen/AMDGPU/smrd_vmem_war.ll
    M llvm/test/CodeGen/AMDGPU/soft-clause-dbg-value.mir
    M llvm/test/CodeGen/AMDGPU/sopk-compares.ll
    M llvm/test/CodeGen/AMDGPU/sopk-no-literal.ll
    M llvm/test/CodeGen/AMDGPU/spill-agpr-partially-undef.mir
    M llvm/test/CodeGen/AMDGPU/spill-agpr.ll
    M llvm/test/CodeGen/AMDGPU/spill-alloc-sgpr-init-bug.ll
    M llvm/test/CodeGen/AMDGPU/spill-before-exec.mir
    M llvm/test/CodeGen/AMDGPU/spill-cfg-position.ll
    M llvm/test/CodeGen/AMDGPU/spill-csr-frame-ptr-reg-copy.ll
    M llvm/test/CodeGen/AMDGPU/spill-empty-live-interval.mir
    M llvm/test/CodeGen/AMDGPU/spill-m0.ll
    M llvm/test/CodeGen/AMDGPU/spill-partial-csr-sgpr-live-ins.mir
    M llvm/test/CodeGen/AMDGPU/spill-reg-tuple-super-reg-use.mir
    M llvm/test/CodeGen/AMDGPU/spill-sgpr-csr-live-ins.mir
    M llvm/test/CodeGen/AMDGPU/spill-sgpr-to-virtual-vgpr.mir
    M llvm/test/CodeGen/AMDGPU/spill-sgpr-used-for-exec-copy.mir
    M llvm/test/CodeGen/AMDGPU/spill-special-sgpr.mir
    M llvm/test/CodeGen/AMDGPU/spill-to-agpr-partial.mir
    M llvm/test/CodeGen/AMDGPU/spill-vector-superclass.ll
    M llvm/test/CodeGen/AMDGPU/spill-vgpr-to-agpr-update-regscavenger.ll
    M llvm/test/CodeGen/AMDGPU/spill-vgpr-to-agpr.ll
    M llvm/test/CodeGen/AMDGPU/spill-vgpr.ll
    M llvm/test/CodeGen/AMDGPU/spill-wide-sgpr.ll
    M llvm/test/CodeGen/AMDGPU/spill-writelane-vgprs.ll
    M llvm/test/CodeGen/AMDGPU/spill_kill_v16.mir
    M llvm/test/CodeGen/AMDGPU/spill_more_than_wavesize_csr_sgprs.ll
    M llvm/test/CodeGen/AMDGPU/spillv16.mir
    M llvm/test/CodeGen/AMDGPU/split-scalar-i64-add.ll
    M llvm/test/CodeGen/AMDGPU/split-smrd.ll
    M llvm/test/CodeGen/AMDGPU/split-vector-memoperand-offsets.ll
    M llvm/test/CodeGen/AMDGPU/splitkit-copy-bundle.mir
    M llvm/test/CodeGen/AMDGPU/splitkit.mir
    M llvm/test/CodeGen/AMDGPU/sra.ll
    M llvm/test/CodeGen/AMDGPU/srem.ll
    M llvm/test/CodeGen/AMDGPU/srem64.ll
    M llvm/test/CodeGen/AMDGPU/srl.ll
    M llvm/test/CodeGen/AMDGPU/ssubo.ll
    M llvm/test/CodeGen/AMDGPU/stack-pointer-offset-relative-frameindex.ll
    M llvm/test/CodeGen/AMDGPU/stack-realign.ll
    M llvm/test/CodeGen/AMDGPU/stack-slot-color-sgpr-vgpr-spills.mir
    M llvm/test/CodeGen/AMDGPU/stale-livevar-in-twoaddr-pass.mir
    M llvm/test/CodeGen/AMDGPU/stop-tail-duplicate-cfg-intrinsic.mir
    M llvm/test/CodeGen/AMDGPU/store-barrier.ll
    M llvm/test/CodeGen/AMDGPU/store-global.ll
    M llvm/test/CodeGen/AMDGPU/store-hi16.ll
    M llvm/test/CodeGen/AMDGPU/store-local.128.ll
    M llvm/test/CodeGen/AMDGPU/store-local.96.ll
    M llvm/test/CodeGen/AMDGPU/store-local.ll
    M llvm/test/CodeGen/AMDGPU/store-private.ll
    M llvm/test/CodeGen/AMDGPU/store-v3i64.ll
    M llvm/test/CodeGen/AMDGPU/store-vector-ptrs.ll
    M llvm/test/CodeGen/AMDGPU/store-weird-sizes.ll
    M llvm/test/CodeGen/AMDGPU/sub-zext-cc-zext-cc.ll
    M llvm/test/CodeGen/AMDGPU/sub.i16.ll
    M llvm/test/CodeGen/AMDGPU/sub.ll
    M llvm/test/CodeGen/AMDGPU/sub.v2i16.ll
    M llvm/test/CodeGen/AMDGPU/sub_i1.ll
    M llvm/test/CodeGen/AMDGPU/subreg-intervals.mir
    M llvm/test/CodeGen/AMDGPU/subreg-undef-def-with-other-subreg-defs.mir
    M llvm/test/CodeGen/AMDGPU/subreg_interference.mir
    M llvm/test/CodeGen/AMDGPU/subvector-test.mir
    M llvm/test/CodeGen/AMDGPU/swdev373493.ll
    M llvm/test/CodeGen/AMDGPU/swdev503538-move-to-valu-stack-srd-physreg.ll
    M llvm/test/CodeGen/AMDGPU/switch-default-block-unreachable.ll
    M llvm/test/CodeGen/AMDGPU/switch-unreachable.ll
    M llvm/test/CodeGen/AMDGPU/swizzle.bit.extract.ll
    M llvm/test/CodeGen/AMDGPU/tail-call-amdgpu-gfx.ll
    M llvm/test/CodeGen/AMDGPU/tail-call-inreg-arguments.error.ll
    M llvm/test/CodeGen/AMDGPU/tail-call-inreg-arguments.ll
    M llvm/test/CodeGen/AMDGPU/tail-call-uniform-target-in-vgprs-issue110930.ll
    M llvm/test/CodeGen/AMDGPU/tail-dup-bundle.mir
    M llvm/test/CodeGen/AMDGPU/target-cpu.ll
    M llvm/test/CodeGen/AMDGPU/threeaddr-wmma.mir
    M llvm/test/CodeGen/AMDGPU/tied-op-for-wwm-scratch-reg-spill-restore.mir
    M llvm/test/CodeGen/AMDGPU/token-factor-inline-limit-test.ll
    M llvm/test/CodeGen/AMDGPU/track-spilled-vgpr-liveness.mir
    M llvm/test/CodeGen/AMDGPU/trans-forwarding-hazards.mir
    M llvm/test/CodeGen/AMDGPU/transform-block-with-return-to-epilog.ll
    M llvm/test/CodeGen/AMDGPU/trap-abis.ll
    M llvm/test/CodeGen/AMDGPU/trap.ll
    M llvm/test/CodeGen/AMDGPU/triv-disjoint-mem-access-neg-offset.mir
    M llvm/test/CodeGen/AMDGPU/true16-ra-pre-gfx11-regression-test.mir
    M llvm/test/CodeGen/AMDGPU/trunc-bitcast-vector.ll
    M llvm/test/CodeGen/AMDGPU/trunc-cmp-constant.ll
    M llvm/test/CodeGen/AMDGPU/trunc-combine.ll
    M llvm/test/CodeGen/AMDGPU/trunc-store-f64-to-f16.ll
    M llvm/test/CodeGen/AMDGPU/trunc-store-i1.ll
    M llvm/test/CodeGen/AMDGPU/trunc-store-i64.ll
    M llvm/test/CodeGen/AMDGPU/trunc-store-vec-i16-to-i8.ll
    M llvm/test/CodeGen/AMDGPU/trunc.ll
    M llvm/test/CodeGen/AMDGPU/twoaddr-constrain.ll
    M llvm/test/CodeGen/AMDGPU/twoaddr-fma-f64.mir
    M llvm/test/CodeGen/AMDGPU/twoaddr-fma.mir
    M llvm/test/CodeGen/AMDGPU/twoaddr-mad.mir
    M llvm/test/CodeGen/AMDGPU/twoaddr-regsequence.mir
    M llvm/test/CodeGen/AMDGPU/twoaddr-wmma.mir
    M llvm/test/CodeGen/AMDGPU/uaddo.ll
    M llvm/test/CodeGen/AMDGPU/udiv.ll
    M llvm/test/CodeGen/AMDGPU/udiv64.ll
    M llvm/test/CodeGen/AMDGPU/udivrem.ll
    M llvm/test/CodeGen/AMDGPU/udivrem24.ll
    M llvm/test/CodeGen/AMDGPU/uint_to_fp.f64.ll
    M llvm/test/CodeGen/AMDGPU/uint_to_fp.i64.ll
    M llvm/test/CodeGen/AMDGPU/uint_to_fp.ll
    M llvm/test/CodeGen/AMDGPU/uitofp.f16.ll
    M llvm/test/CodeGen/AMDGPU/umed3.ll
    M llvm/test/CodeGen/AMDGPU/unaligned-load-store.ll
    M llvm/test/CodeGen/AMDGPU/unallocatable-bundle-regression.mir
    M llvm/test/CodeGen/AMDGPU/undef-copy-propagation.mir
    M llvm/test/CodeGen/AMDGPU/undef-subreg-use-after-coalesce.mir
    M llvm/test/CodeGen/AMDGPU/undefined-physreg-sgpr-spill.mir
    M llvm/test/CodeGen/AMDGPU/undefined-subreg-liverange.ll
    M llvm/test/CodeGen/AMDGPU/unexpected-reg-unit-state.mir
    M llvm/test/CodeGen/AMDGPU/unhandled-loop-condition-assertion.ll
    M llvm/test/CodeGen/AMDGPU/uniform-branch-intrinsic-cond.ll
    M llvm/test/CodeGen/AMDGPU/uniform-cfg.ll
    M llvm/test/CodeGen/AMDGPU/uniform-crash.ll
    M llvm/test/CodeGen/AMDGPU/uniform-load-from-tid.ll
    M llvm/test/CodeGen/AMDGPU/uniform-phi-with-undef.ll
    M llvm/test/CodeGen/AMDGPU/unigine-liveness-crash.ll
    M llvm/test/CodeGen/AMDGPU/unknown-processor.ll
    M llvm/test/CodeGen/AMDGPU/unpack-half.ll
    M llvm/test/CodeGen/AMDGPU/unstructured-cfg-def-use-issue.ll
    M llvm/test/CodeGen/AMDGPU/unsupported-calls.ll
    M llvm/test/CodeGen/AMDGPU/unsupported-cs-chain.ll
    M llvm/test/CodeGen/AMDGPU/unsupported-image-a16.ll
    M llvm/test/CodeGen/AMDGPU/unsupported-image-g16.ll
    M llvm/test/CodeGen/AMDGPU/unsupported-image-sample.ll
    M llvm/test/CodeGen/AMDGPU/urem.ll
    M llvm/test/CodeGen/AMDGPU/urem64.ll
    M llvm/test/CodeGen/AMDGPU/use-sgpr-multiple-times.ll
    M llvm/test/CodeGen/AMDGPU/use_restore_frame_reg.mir
    M llvm/test/CodeGen/AMDGPU/usubo.ll
    M llvm/test/CodeGen/AMDGPU/v1024.ll
    M llvm/test/CodeGen/AMDGPU/v_add_u64_pseudo_sdwa.ll
    M llvm/test/CodeGen/AMDGPU/v_ashr_pk.ll
    M llvm/test/CodeGen/AMDGPU/v_cmp_gfx11.ll
    M llvm/test/CodeGen/AMDGPU/v_cndmask.ll
    M llvm/test/CodeGen/AMDGPU/v_cvt_pk_u8_f32.ll
    M llvm/test/CodeGen/AMDGPU/v_mac.ll
    M llvm/test/CodeGen/AMDGPU/v_mac_f16.ll
    M llvm/test/CodeGen/AMDGPU/v_madak_f16.ll
    M llvm/test/CodeGen/AMDGPU/v_mov_b64_expand_and_shrink.mir
    M llvm/test/CodeGen/AMDGPU/v_mov_b64_expansion.mir
    M llvm/test/CodeGen/AMDGPU/v_pack.ll
    M llvm/test/CodeGen/AMDGPU/v_sat_pk_u8_i16.ll
    M llvm/test/CodeGen/AMDGPU/v_sub_u64_pseudo_sdwa.ll
    M llvm/test/CodeGen/AMDGPU/v_swap_b16.ll
    M llvm/test/CodeGen/AMDGPU/v_swap_b32.mir
    M llvm/test/CodeGen/AMDGPU/valu-i1.ll
    M llvm/test/CodeGen/AMDGPU/valu-mask-write-hazard-true16.mir
    M llvm/test/CodeGen/AMDGPU/valu-mask-write-hazard.mir
    M llvm/test/CodeGen/AMDGPU/valu-read-sgpr-hazard.mir
    M llvm/test/CodeGen/AMDGPU/vcmp-saveexec-to-vcmpx-set-kill.mir
    M llvm/test/CodeGen/AMDGPU/vcmp-saveexec-to-vcmpx-wrong-kill-flags.mir
    M llvm/test/CodeGen/AMDGPU/vcmp-saveexec-to-vcmpx.ll
    M llvm/test/CodeGen/AMDGPU/vcmp-saveexec-to-vcmpx.mir
    M llvm/test/CodeGen/AMDGPU/vcmpx-exec-war-hazard.mir
    M llvm/test/CodeGen/AMDGPU/vcmpx-permlane-hazard-sdwa.mir
    M llvm/test/CodeGen/AMDGPU/vcmpx-permlane-hazard.mir
    M llvm/test/CodeGen/AMDGPU/vcmpx-permlane16var-hazard.mir
    M llvm/test/CodeGen/AMDGPU/vector-alloca-bitcast.ll
    M llvm/test/CodeGen/AMDGPU/vector-alloca.ll
    M llvm/test/CodeGen/AMDGPU/vector-extract-insert.ll
    M llvm/test/CodeGen/AMDGPU/vector-spill-restore-to-other-vector-type.mir
    M llvm/test/CodeGen/AMDGPU/vector_shuffle.packed.ll
    M llvm/test/CodeGen/AMDGPU/vectorize-global-local.ll
    M llvm/test/CodeGen/AMDGPU/vectorize-loads.ll
    M llvm/test/CodeGen/AMDGPU/vgpr-blocks-funcinfo.mir
    M llvm/test/CodeGen/AMDGPU/vgpr-large-tuple-alloc-error.ll
    M llvm/test/CodeGen/AMDGPU/vgpr-liverange-ir.ll
    M llvm/test/CodeGen/AMDGPU/vgpr-liverange.ll
    M llvm/test/CodeGen/AMDGPU/vgpr-mark-last-scratch-load.mir
    M llvm/test/CodeGen/AMDGPU/vgpr-spill-dead-frame-in-dbg-value.mir
    M llvm/test/CodeGen/AMDGPU/vgpr-spill-emergency-stack-slot-compute.ll
    M llvm/test/CodeGen/AMDGPU/vgpr-spill-emergency-stack-slot.ll
    M llvm/test/CodeGen/AMDGPU/vgpr-spill-fi-skip-processing-stack-arg-dbg-value.mir
    M llvm/test/CodeGen/AMDGPU/vgpr-spill-scc-clobber.mir
    M llvm/test/CodeGen/AMDGPU/vgpr-spill.mir
    M llvm/test/CodeGen/AMDGPU/vgpr-tuple-allocation.ll
    M llvm/test/CodeGen/AMDGPU/vgpr_constant64_to_sgpr.mir
    M llvm/test/CodeGen/AMDGPU/virtregrewrite-undef-identity-copy.mir
    M llvm/test/CodeGen/AMDGPU/vmem-to-salu-hazard.mir
    M llvm/test/CodeGen/AMDGPU/vmem-vcc-hazard.mir
    M llvm/test/CodeGen/AMDGPU/vop-shrink-frame-index.mir
    M llvm/test/CodeGen/AMDGPU/vop-shrink-non-ssa.mir
    M llvm/test/CodeGen/AMDGPU/vop-shrink.ll
    M llvm/test/CodeGen/AMDGPU/vopc_dpp-true16.mir
    M llvm/test/CodeGen/AMDGPU/vopc_dpp.ll
    M llvm/test/CodeGen/AMDGPU/vopc_dpp.mir
    M llvm/test/CodeGen/AMDGPU/vopd-combine.mir
    M llvm/test/CodeGen/AMDGPU/vopd-src2acc-delay.mir
    M llvm/test/CodeGen/AMDGPU/vselect.ll
    M llvm/test/CodeGen/AMDGPU/wait-before-stores-with-scope_sys.ll
    M llvm/test/CodeGen/AMDGPU/wait.ll
    M llvm/test/CodeGen/AMDGPU/waitcnt-agpr.mir
    M llvm/test/CodeGen/AMDGPU/waitcnt-back-edge-loop.mir
    M llvm/test/CodeGen/AMDGPU/waitcnt-bvh.mir
    M llvm/test/CodeGen/AMDGPU/waitcnt-debug.mir
    M llvm/test/CodeGen/AMDGPU/waitcnt-global-inv-wb.mir
    M llvm/test/CodeGen/AMDGPU/waitcnt-loop-irreducible.mir
    M llvm/test/CodeGen/AMDGPU/waitcnt-loop-single-basic-block.mir
    M llvm/test/CodeGen/AMDGPU/waitcnt-meta-instructions.mir
    M llvm/test/CodeGen/AMDGPU/waitcnt-multiple-funcs.mir
    M llvm/test/CodeGen/AMDGPU/waitcnt-no-redundant.mir
    M llvm/test/CodeGen/AMDGPU/waitcnt-overflow.mir
    M llvm/test/CodeGen/AMDGPU/waitcnt-permute.mir
    M llvm/test/CodeGen/AMDGPU/waitcnt-preexisting-vscnt.mir
    M llvm/test/CodeGen/AMDGPU/waitcnt-preexisting.mir
    M llvm/test/CodeGen/AMDGPU/waitcnt-sample-out-order.mir
    M llvm/test/CodeGen/AMDGPU/waitcnt-sample-waw.mir
    M llvm/test/CodeGen/AMDGPU/waitcnt-trailing.mir
    M llvm/test/CodeGen/AMDGPU/waitcnt-vinterp.mir
    M llvm/test/CodeGen/AMDGPU/waitcnt-vmcnt-loop.mir
    M llvm/test/CodeGen/AMDGPU/waitcnt-vmem-waw.mir
    M llvm/test/CodeGen/AMDGPU/waitcnt-vscnt.ll
    M llvm/test/CodeGen/AMDGPU/waitcnt-vscnt.mir
    M llvm/test/CodeGen/AMDGPU/waterfall_kills_scc.ll
    M llvm/test/CodeGen/AMDGPU/wave32.ll
    M llvm/test/CodeGen/AMDGPU/wave_dispatch_regs.ll
    M llvm/test/CodeGen/AMDGPU/while-break.ll
    M llvm/test/CodeGen/AMDGPU/whole-wave-functions.ll
    M llvm/test/CodeGen/AMDGPU/whole-wave-register-copy.ll
    M llvm/test/CodeGen/AMDGPU/whole-wave-register-spill.ll
    M llvm/test/CodeGen/AMDGPU/widen-smrd-loads.ll
    M llvm/test/CodeGen/AMDGPU/widen-vselect-and-mask.ll
    M llvm/test/CodeGen/AMDGPU/wmma-gfx12-w32-f16-f32-matrix-modifiers.ll
    M llvm/test/CodeGen/AMDGPU/wmma-gfx12-w32-imm.ll
    M llvm/test/CodeGen/AMDGPU/wmma-gfx12-w32-iu-modifiers.ll
    M llvm/test/CodeGen/AMDGPU/wmma-gfx12-w32-swmmac-index_key.ll
    M llvm/test/CodeGen/AMDGPU/wmma-gfx12-w32.ll
    M llvm/test/CodeGen/AMDGPU/wmma-gfx12-w64-f16-f32-matrix-modifiers.ll
    M llvm/test/CodeGen/AMDGPU/wmma-gfx12-w64-imm.ll
    M llvm/test/CodeGen/AMDGPU/wmma-gfx12-w64-iu-modifiers.ll
    M llvm/test/CodeGen/AMDGPU/wmma-gfx12-w64-swmmac-index_key.ll
    M llvm/test/CodeGen/AMDGPU/wmma-gfx12-w64.ll
    M llvm/test/CodeGen/AMDGPU/wmma-hazards-gfx12-w32.mir
    M llvm/test/CodeGen/AMDGPU/wmma-hazards-gfx12-w64.mir
    M llvm/test/CodeGen/AMDGPU/wmma-hazards.mir
    M llvm/test/CodeGen/AMDGPU/wmma_modifiers.ll
    M llvm/test/CodeGen/AMDGPU/wmma_multiple_32.ll
    M llvm/test/CodeGen/AMDGPU/wmma_multiple_64.ll
    M llvm/test/CodeGen/AMDGPU/workgroup-id-in-arch-sgprs.ll
    M llvm/test/CodeGen/AMDGPU/wqm-gfx11.ll
    M llvm/test/CodeGen/AMDGPU/wqm-terminators.mir
    M llvm/test/CodeGen/AMDGPU/wqm.ll
    M llvm/test/CodeGen/AMDGPU/wqm.mir
    M llvm/test/CodeGen/AMDGPU/write-register-vgpr-into-sgpr.ll
    M llvm/test/CodeGen/AMDGPU/write_register.ll
    M llvm/test/CodeGen/AMDGPU/wwm-reserved-spill.ll
    M llvm/test/CodeGen/AMDGPU/wwm-reserved.ll
    M llvm/test/CodeGen/AMDGPU/wwm-spill-superclass-pseudo.mir
    M llvm/test/CodeGen/AMDGPU/xnor.ll
    M llvm/test/CodeGen/AMDGPU/xor3-i1-const.ll
    M llvm/test/CodeGen/AMDGPU/xor3.ll
    M llvm/test/CodeGen/AMDGPU/xor_add.ll
    M llvm/test/CodeGen/AMDGPU/zero_extend.ll
    M llvm/test/CodeGen/AMDGPU/zext-divergence-driven-isel.ll
    M llvm/test/CodeGen/AMDGPU/zext-i64-bit-operand.ll

  Log Message:
  -----------
  [RFC][NFC][AMDGPU] Remove `-verify-machineinstrs` from `llvm/test/CodeGen/AMDGPU/`



To unsubscribe from these emails, change your notification settings at https://github.com/llvm/llvm-project/settings/notifications