[all-commits] [llvm/llvm-project] eafe31: [RISCV] Don't lose elements from False in vmerge -...

[Luke Lau via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: eafe31b293a5166522fff4f3e2d88c2b5c881381
      https://github.com/llvm/llvm-project/commit/eafe31b293a5166522fff4f3e2d88c2b5c881381
  Author: Luke Lau <luke at igalia.com>
  Date:   2025-07-22 (Tue, 22 Jul 2025)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVVectorPeephole.cpp
    M llvm/test/CodeGen/RISCV/rvv/rvv-peephole-vmerge-to-vmv.mir
    M llvm/test/CodeGen/RISCV/rvv/rvv-vmerge-to-vmv.ll

  Log Message:
  -----------
  [RISCV] Don't lose elements from False in vmerge -> vmv peephole (#149720)

In the vmerge peephole, we currently allow different AVLs for the vmerge
and its true operand.
If vmerge's VL > true's VL, vmerge can "preserve" elements from false
that would otherwise be clobbered with a tail agnostic policy on true.

    mask	1 1 1 1 0 0 0 0
    true	x x x x|. . . . AVL=4
    vmerge	x x x x f f|. . AVL=6

If we convert this to vmv.v.v we will lose those false elements:

    mask	1 1 1 1 0 0 0 0
    true	x x x x|. . . . AVL=4
    vmv.v.v	x x x x . .|. . AVL=6

Fix this by checking that vmerge's AVL is <= true's AVL.

Should fix #149335



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