[all-commits] [llvm/llvm-project] c58225: [RISCV] Add RISCV::SUBW to RISCVOptWInstrs::stripW...

[Alex Bradbury via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: c58225f7571bf52ca7b8e674c6a443e910302c18
      https://github.com/llvm/llvm-project/commit/c58225f7571bf52ca7b8e674c6a443e910302c18
  Author: Alex Bradbury <asb at igalia.com>
  Date:   2025-07-20 (Sun, 20 Jul 2025)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVOptWInstrs.cpp
    M llvm/test/CodeGen/RISCV/GlobalISel/div-by-constant.ll
    M llvm/test/CodeGen/RISCV/GlobalISel/rotl-rotr.ll
    M llvm/test/CodeGen/RISCV/GlobalISel/rv64zbb-zbkb.ll
    M llvm/test/CodeGen/RISCV/GlobalISel/rv64zbb.ll
    M llvm/test/CodeGen/RISCV/GlobalISel/shifts.ll
    M llvm/test/CodeGen/RISCV/GlobalISel/wide-scalar-shift-by-byte-multiple-legalization.ll
    M llvm/test/CodeGen/RISCV/abds-neg.ll
    M llvm/test/CodeGen/RISCV/abds.ll
    M llvm/test/CodeGen/RISCV/addimm-mulimm.ll
    M llvm/test/CodeGen/RISCV/aext-to-sext.ll
    M llvm/test/CodeGen/RISCV/atomicrmw-cond-sub-clamp.ll
    M llvm/test/CodeGen/RISCV/atomicrmw-uinc-udec-wrap.ll
    M llvm/test/CodeGen/RISCV/ctlz-cttz-ctpop.ll
    M llvm/test/CodeGen/RISCV/ctz_zero_return_test.ll
    M llvm/test/CodeGen/RISCV/div-by-constant.ll
    M llvm/test/CodeGen/RISCV/iabs.ll
    M llvm/test/CodeGen/RISCV/intrinsic-cttz-elts-vscale.ll
    M llvm/test/CodeGen/RISCV/intrinsic-cttz-elts.ll
    M llvm/test/CodeGen/RISCV/machine-combiner.ll
    M llvm/test/CodeGen/RISCV/mul.ll
    M llvm/test/CodeGen/RISCV/neg-abs.ll
    M llvm/test/CodeGen/RISCV/overflow-intrinsics.ll
    M llvm/test/CodeGen/RISCV/pr145360.ll
    M llvm/test/CodeGen/RISCV/rotl-rotr.ll
    M llvm/test/CodeGen/RISCV/rv64i-demanded-bits.ll
    M llvm/test/CodeGen/RISCV/rv64i-exhaustive-w-insts.ll
    M llvm/test/CodeGen/RISCV/rv64i-w-insts-legalization.ll
    M llvm/test/CodeGen/RISCV/rv64xtheadbb.ll
    M llvm/test/CodeGen/RISCV/rv64zba.ll
    M llvm/test/CodeGen/RISCV/rv64zbb-zbkb.ll
    M llvm/test/CodeGen/RISCV/rv64zbb.ll
    M llvm/test/CodeGen/RISCV/rvv/expand-no-v.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-strided-load-store-asm.ll
    M llvm/test/CodeGen/RISCV/rvv/fpclamptosat_vec.ll
    M llvm/test/CodeGen/RISCV/rvv/known-never-zero.ll
    M llvm/test/CodeGen/RISCV/rvv/sink-splat-operands.ll
    M llvm/test/CodeGen/RISCV/rvv/vandn-sdnode.ll
    M llvm/test/CodeGen/RISCV/rvv/vec3-setcc-crash.ll
    M llvm/test/CodeGen/RISCV/rvv/vrol-sdnode.ll
    M llvm/test/CodeGen/RISCV/rvv/vror-sdnode.ll
    M llvm/test/CodeGen/RISCV/rvv/vscale-power-of-two.ll
    M llvm/test/CodeGen/RISCV/select.ll
    M llvm/test/CodeGen/RISCV/sextw-removal.ll
    M llvm/test/CodeGen/RISCV/shifts.ll
    M llvm/test/CodeGen/RISCV/shl-cttz.ll
    M llvm/test/CodeGen/RISCV/srem-seteq-illegal-types.ll
    M llvm/test/CodeGen/RISCV/srem-vector-lkk.ll
    M llvm/test/CodeGen/RISCV/typepromotion-overflow.ll
    M llvm/test/CodeGen/RISCV/urem-lkk.ll
    M llvm/test/CodeGen/RISCV/urem-seteq-illegal-types.ll
    M llvm/test/CodeGen/RISCV/urem-vector-lkk.ll

  Log Message:
  -----------
  [RISCV] Add RISCV::SUBW to RISCVOptWInstrs::stripWSuffixes (#149071)

This is purely a benefit for reducing unnecessary diffs between RV32 and
RV64, as RVC does have a compressed form of SUBW (so SUB isn't more
compressible). This affects ~57.2k instructions in an rva22u64 build of
llvm-test-suite with SPEC CPU 2017 included.



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