[all-commits] [llvm/llvm-project] 3866e4: [NVPTX] Add im2colw/w128 modes support to TMA intr...

[Durgadoss R via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 3866e4e7f85aacd0e47978b22084ed00ebcd0531
      https://github.com/llvm/llvm-project/commit/3866e4e7f85aacd0e47978b22084ed00ebcd0531
  Author: Durgadoss R <durgadossr at nvidia.com>
  Date:   2025-07-19 (Sat, 19 Jul 2025)

  Changed paths:
    M llvm/docs/NVPTXUsage.rst
    M llvm/include/llvm/IR/IntrinsicsNVVM.td
    M llvm/lib/Target/NVPTX/NVPTXInstrInfo.td
    M llvm/lib/Target/NVPTX/NVPTXIntrinsics.td
    A llvm/test/CodeGen/NVPTX/cp-async-bulk-tensor-g2s-cta-sm100.ll
    A llvm/test/CodeGen/NVPTX/cp-async-bulk-tensor-g2s-cta-sm100a.ll
    A llvm/test/CodeGen/NVPTX/cp-async-bulk-tensor-g2s-cta-sm90.ll
    A llvm/test/CodeGen/NVPTX/cp-async-bulk-tensor-g2s-gather4.ll
    A llvm/test/CodeGen/NVPTX/cp-async-bulk-tensor-g2s-im2colw.ll
    A llvm/test/CodeGen/NVPTX/cp-async-bulk-tensor-g2s-im2colw128.ll
    A llvm/test/CodeGen/NVPTX/cp-async-bulk-tensor-prefetch-sm100a.ll
    A llvm/test/CodeGen/NVPTX/cp-async-bulk-tensor-s2g-scatter4.ll

  Log Message:
  -----------
  [NVPTX] Add im2colw/w128 modes support to TMA intrinsics (#148863)

This patch adds support for the im2col-w/w128 and scatter/gather modes
for TMA Copy and Prefetch intrinsics, completing support for all the
available modes. These are lowered through tablegen, building
on top of earlier patches.

* lit tests are added for all the combinations and verified with a
  12.8 ptxas executable.
* Documentation is updated in the NVPTXUsage.rst file.

Signed-off-by: Durgadoss R <durgadossr at nvidia.com>



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