[all-commits] [llvm/llvm-project] 52a9c4: Reland "[RISCV] AddEdge between mask producer and...
Prabhu Rajasekaran via All-commits
all-commits at lists.llvm.org
Fri Jul 18 15:40:15 PDT 2025
Branch: refs/heads/users/Prabhuk/sprclangcallgraphsection-add-call-graph-section-option-and-docs
Home: https://github.com/llvm/llvm-project
Commit: 52a9c493e62c8af8f1299cae0babb92f2693065b
https://github.com/llvm/llvm-project/commit/52a9c493e62c8af8f1299cae0babb92f2693065b
Author: Liao Chunyu <chunyu at iscas.ac.cn>
Date: 2025-07-18 (Fri, 18 Jul 2025)
Changed paths:
M llvm/lib/Target/RISCV/RISCVVectorMaskDAGMutation.cpp
M llvm/test/CodeGen/RISCV/rvv/combine-reduce-add-to-vcpop.ll
M llvm/test/CodeGen/RISCV/rvv/extractelt-i1.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-extract-i1.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-deinterleave.ll
A llvm/test/CodeGen/RISCV/rvv/reproducer-pr146855.ll
M llvm/test/CodeGen/RISCV/rvv/vscale-vw-web-simplification.ll
M llvm/test/CodeGen/RISCV/rvv/vselect-fp.ll
Log Message:
-----------
Reland "[RISCV] AddEdge between mask producer and user of V0 (#146855)" (#148566)
The defmask vector cannot contain instructions that use V0.
for `MultiSource/Benchmarks/DOE-ProxyApps-C++/CLAMR/mesh.cpp`
Save `%173:vrm2nov0 = PseudoVMERGE_VVM_M2 undef %173:vrm2nov0(tied-def
0), %116:vrm2, %173:vrm2nov0, killed $v0, -1, 5 `to def mask caused crash.
Commit: df56b1a2cf06d1954a9cd1a290a264375f47440d
https://github.com/llvm/llvm-project/commit/df56b1a2cf06d1954a9cd1a290a264375f47440d
Author: Kelvin Li <kli at ca.ibm.com>
Date: 2025-07-17 (Thu, 17 Jul 2025)
Changed paths:
M flang/lib/Optimizer/CodeGen/CodeGen.cpp
M flang/test/Fir/alloc-32.fir
M flang/test/Fir/alloc.fir
M flang/test/Fir/arrexp.fir
M flang/test/Fir/convert-to-llvm.fir
M flang/test/Lower/forall/character-1.f90
Log Message:
-----------
[flang] handle allocation of zero-sized objects (#149165)
This PR handles the allocation of zero-sized objects for different
implementations. One byte is allocated for the zero-sized objects.
Commit: 4c85bf2fe8042c855c9dd5be4b02191e9d071ffd
https://github.com/llvm/llvm-project/commit/4c85bf2fe8042c855c9dd5be4b02191e9d071ffd
Author: Kazu Hirata <kazu at google.com>
Date: 2025-07-17 (Thu, 17 Jul 2025)
Changed paths:
M clang-tools-extra/clangd/unittests/FindTargetTests.cpp
M clang-tools-extra/clangd/unittests/HoverTests.cpp
M clang/docs/ReleaseNotes.rst
M clang/include/clang/AST/ASTContext.h
M clang/include/clang/AST/FormatString.h
M clang/include/clang/AST/RecursiveASTVisitor.h
M clang/include/clang/AST/Type.h
M clang/include/clang/AST/TypeLoc.h
M clang/include/clang/AST/TypeProperties.td
M clang/include/clang/Basic/TypeNodes.td
M clang/include/clang/Serialization/TypeBitCodes.def
M clang/lib/AST/ASTContext.cpp
M clang/lib/AST/ASTImporter.cpp
M clang/lib/AST/ASTStructuralEquivalence.cpp
M clang/lib/AST/FormatString.cpp
M clang/lib/AST/ItaniumMangle.cpp
M clang/lib/AST/PrintfFormatString.cpp
M clang/lib/AST/ScanfFormatString.cpp
M clang/lib/AST/Type.cpp
M clang/lib/AST/TypePrinter.cpp
M clang/lib/CodeGen/CGCall.cpp
M clang/lib/CodeGen/CGCoroutine.cpp
M clang/lib/CodeGen/CGDebugInfo.cpp
M clang/lib/CodeGen/CGObjCMac.cpp
M clang/lib/CodeGen/CodeGenFunction.cpp
M clang/lib/Sema/SemaChecking.cpp
M clang/lib/Sema/SemaExpr.cpp
M clang/lib/Sema/SemaExprCXX.cpp
M clang/lib/Sema/TreeTransform.h
M clang/lib/Serialization/ASTReader.cpp
M clang/lib/Serialization/ASTWriter.cpp
M clang/lib/StaticAnalyzer/Checkers/MallocChecker.cpp
M clang/lib/StaticAnalyzer/Checkers/StdLibraryFunctionsChecker.cpp
M clang/lib/StaticAnalyzer/Checkers/VLASizeChecker.cpp
M clang/test/AST/HLSL/is_structured_resource_element_compatible_concept.hlsl
M clang/test/AST/ast-dump-array.cpp
M clang/test/AST/ast-dump-expr-json.c
M clang/test/AST/ast-dump-expr-json.cpp
M clang/test/AST/ast-dump-expr.c
M clang/test/AST/ast-dump-expr.cpp
M clang/test/AST/ast-dump-openmp-distribute-parallel-for-simd.c
M clang/test/AST/ast-dump-openmp-distribute-parallel-for.c
M clang/test/AST/ast-dump-openmp-target-teams-distribute-parallel-for-simd.c
M clang/test/AST/ast-dump-openmp-target-teams-distribute-parallel-for.c
M clang/test/AST/ast-dump-openmp-teams-distribute-parallel-for-simd.c
M clang/test/AST/ast-dump-openmp-teams-distribute-parallel-for.c
M clang/test/AST/ast-dump-stmt-json.cpp
M clang/test/AST/ast-dump-stmt.cpp
M clang/test/AST/ast-dump-traits.cpp
M clang/test/AST/ast-dump-types-errors-json.cpp
M clang/test/Analysis/cfg.cpp
M clang/test/Analysis/explain-svals.cpp
M clang/test/Analysis/std-c-library-functions-arg-weakdeps.c
M clang/test/Analysis/std-c-library-functions-lookup.c
M clang/test/Analysis/std-c-library-functions-vs-stream-checker.c
M clang/test/Analysis/std-c-library-functions.c
M clang/test/CXX/drs/cwg2xx.cpp
M clang/test/CXX/lex/lex.literal/lex.ext/p2.cpp
M clang/test/CXX/lex/lex.literal/lex.ext/p5.cpp
M clang/test/CXX/lex/lex.literal/lex.ext/p7.cpp
M clang/test/FixIt/fixit-format-ios-nopedantic.m
M clang/test/FixIt/format.m
M clang/test/Sema/format-strings-fixit-ssize_t.c
M clang/test/Sema/format-strings-int-typedefs.c
M clang/test/Sema/format-strings-scanf.c
M clang/test/Sema/format-strings-size_t.c
M clang/test/Sema/matrix-type-builtins.c
M clang/test/Sema/ptrauth-atomic-ops.c
M clang/test/Sema/ptrauth.c
M clang/test/SemaCXX/cxx2c-trivially-relocatable.cpp
M clang/test/SemaCXX/enum-scoped.cpp
M clang/test/SemaCXX/microsoft-varargs-diagnostics.cpp
M clang/test/SemaCXX/new-delete.cpp
M clang/test/SemaCXX/static-assert-cxx26.cpp
M clang/test/SemaCXX/type-aware-new-delete-basic-free-declarations.cpp
M clang/test/SemaCXX/unavailable_aligned_allocation.cpp
M clang/test/SemaHLSL/Language/AssignArray.hlsl
M clang/test/SemaHLSL/Language/InitListAST.hlsl
M clang/test/SemaObjC/format-size-spec-nsinteger.m
M clang/test/SemaObjC/matrix-type-builtins.m
M clang/test/SemaOpenCL/cl20-device-side-enqueue.cl
M clang/test/SemaTemplate/type_pack_element.cpp
M clang/tools/libclang/CIndex.cpp
M libcxx/test/libcxx/containers/sequences/deque/spare_block_handling.pass.cpp
M lldb/source/Plugins/TypeSystem/Clang/TypeSystemClang.cpp
Log Message:
-----------
Revert "[Clang] Make the SizeType, SignedSizeType and PtrdiffType be named sugar types instead of built-in types (#143653)"
This reverts commit c27e283cfbca2bd22f34592430e98ee76ed60ad8.
A builbot failure has been reported:
https://lab.llvm.org/buildbot/#/builders/186/builds/10819/steps/10/logs/stdio
I'm also getting a large number of warnings related to %zu and %zx.
Commit: aecd44818adcc26c0535e779629682c76ea44832
https://github.com/llvm/llvm-project/commit/aecd44818adcc26c0535e779629682c76ea44832
Author: Shilei Tian <i at tianshilei.me>
Date: 2025-07-18 (Fri, 18 Jul 2025)
Changed paths:
M clang/include/clang/Basic/BuiltinsAMDGPU.def
M clang/lib/CodeGen/TargetBuiltins/AMDGPU.cpp
M clang/test/CodeGenOpenCL/builtins-amdgcn-gfx1250.cl
M llvm/lib/Target/AMDGPU/VOP1Instructions.td
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.tanh.ll
M llvm/test/MC/AMDGPU/gfx1250_asm_vop1-fake16.s
M llvm/test/MC/AMDGPU/gfx1250_asm_vop1.s
M llvm/test/MC/AMDGPU/gfx1250_asm_vop1_dpp16-fake16.s
M llvm/test/MC/AMDGPU/gfx1250_asm_vop1_dpp16.s
M llvm/test/MC/AMDGPU/gfx1250_asm_vop1_dpp8-fake16.s
M llvm/test/MC/AMDGPU/gfx1250_asm_vop1_dpp8.s
M llvm/test/MC/AMDGPU/gfx1250_asm_vop3_from_vop1-fake16.s
M llvm/test/MC/AMDGPU/gfx1250_asm_vop3_from_vop1.s
M llvm/test/MC/AMDGPU/gfx1250_asm_vop3_from_vop1_dpp16-fake16.s
M llvm/test/MC/AMDGPU/gfx1250_asm_vop3_from_vop1_dpp16.s
M llvm/test/MC/AMDGPU/gfx1250_asm_vop3_from_vop1_dpp8-fake16.s
M llvm/test/MC/AMDGPU/gfx1250_asm_vop3_from_vop1_dpp8.s
M llvm/test/MC/Disassembler/AMDGPU/gfx1250_dasm_vop1.txt
M llvm/test/MC/Disassembler/AMDGPU/gfx1250_dasm_vop1_dpp16.txt
M llvm/test/MC/Disassembler/AMDGPU/gfx1250_dasm_vop1_dpp8.txt
M llvm/test/MC/Disassembler/AMDGPU/gfx1250_dasm_vop3_from_vop1.txt
M llvm/test/MC/Disassembler/AMDGPU/gfx1250_dasm_vop3_from_vop1_dpp16.txt
M llvm/test/MC/Disassembler/AMDGPU/gfx1250_dasm_vop3_from_vop1_dpp8.txt
Log Message:
-----------
[AMDGPU] Add support for `v_tanh_f16` on gfx1250 (#149439)
Co-authored-by: Mekhanoshin, Stanislav <Stanislav.Mekhanoshin at amd.com>
Commit: fb81a0dd9ebe42702190a56db5c9dae7a3dbaec7
https://github.com/llvm/llvm-project/commit/fb81a0dd9ebe42702190a56db5c9dae7a3dbaec7
Author: Madhur Amilkanthwar <madhura at nvidia.com>
Date: 2025-07-18 (Fri, 18 Jul 2025)
Changed paths:
A llvm/test/Transforms/LoopInterchange/fp-reductions.ll
M llvm/test/Transforms/LoopInterchange/reductions-non-wrapped-operations.ll
Log Message:
-----------
[LoopInterchange][NFCI] Split reductions-non-wrapped-operations.ll (#149449)
This test has grown too big. Having one for float for int would be more
manageable.
Commit: 3eb07996b1d6874e4c288a49712d2a5ada57cd2d
https://github.com/llvm/llvm-project/commit/3eb07996b1d6874e4c288a49712d2a5ada57cd2d
Author: Madhur Amilkanthwar <madhura at nvidia.com>
Date: 2025-07-18 (Fri, 18 Jul 2025)
Changed paths:
M llvm/lib/Transforms/Scalar/GVN.cpp
Log Message:
-----------
[GVN][NFCI] Use early return in phiTranslateImpl() (#149273)
Commit: 4e6157f7844cc801bc84ac06f53052e8c6d6c478
https://github.com/llvm/llvm-project/commit/4e6157f7844cc801bc84ac06f53052e8c6d6c478
Author: Baranov Victor <bar.victor.2002 at gmail.com>
Date: 2025-07-18 (Fri, 18 Jul 2025)
Changed paths:
M clang-tools-extra/docs/clang-tidy/Contributing.rst
Log Message:
-----------
[clang-tidy][NFC] Add mention of running 'clang-tidy' on changes in Contributing.rst (#148547)
Follow up to https://github.com/llvm/llvm-project/pull/147793.
_Originally suggested by carlosgalvezp in
https://github.com/llvm/llvm-project/pull/147793#issuecomment-3059021433_
Commit: a8f5e9ed6b44562938ce07e2790be90be8f0a6b5
https://github.com/llvm/llvm-project/commit/a8f5e9ed6b44562938ce07e2790be90be8f0a6b5
Author: Owen Pan <owenpiano at gmail.com>
Date: 2025-07-17 (Thu, 17 Jul 2025)
Changed paths:
M clang/lib/Format/TokenAnnotator.cpp
M clang/unittests/Format/TokenAnnotatorTest.cpp
Log Message:
-----------
[clang-format] Fix a regression of annotating PointerOrReference (#149039)
Fixes #149010
Commit: 03fe1a493d55cfc27a32ee3064639b86cb54d16a
https://github.com/llvm/llvm-project/commit/03fe1a493d55cfc27a32ee3064639b86cb54d16a
Author: Jorn Tuyls <jorn.tuyls at gmail.com>
Date: 2025-07-18 (Fri, 18 Jul 2025)
Changed paths:
M llvm/lib/Target/AMDGPU/SIFixSGPRCopies.cpp
A llvm/test/CodeGen/AMDGPU/sgpr-to-vreg1-copy.ll
A llvm/test/CodeGen/AMDGPU/sgpr-to-vreg1-copy.mir
Log Message:
-----------
[AMDGPU] Fix sgpr to vreg_1 copy analysis (#149181)
Commit: de453e86977adf4f418b003b5c25931b8365c9cc
https://github.com/llvm/llvm-project/commit/de453e86977adf4f418b003b5c25931b8365c9cc
Author: Wanyi <wanyi at meta.com>
Date: 2025-07-18 (Fri, 18 Jul 2025)
Changed paths:
M lldb/tools/lldb-dap/DAP.cpp
Log Message:
-----------
[lldb-dap] Fix type req->arguments == "disconnect" (#149446)
This typo was introduced in PR #140331. This branch will never get
executed. We also set the `disconnecting = true` in the
`DAP::Disconnect()` so I am not sure if we need it in both places.
Commit: f761d73265119eeb3b1ab64543e6d3012078ad13
https://github.com/llvm/llvm-project/commit/f761d73265119eeb3b1ab64543e6d3012078ad13
Author: Shoreshen <372660931 at qq.com>
Date: 2025-07-18 (Fri, 18 Jul 2025)
Changed paths:
M llvm/lib/Target/AMDGPU/SIISelLowering.cpp
M llvm/test/CodeGen/AMDGPU/amdgpu-codegenprepare-idiv.ll
M llvm/test/CodeGen/AMDGPU/div_i128.ll
M llvm/test/CodeGen/AMDGPU/fmaximum3.ll
M llvm/test/CodeGen/AMDGPU/fminimum3.ll
M llvm/test/CodeGen/AMDGPU/fnearbyint.ll
M llvm/test/CodeGen/AMDGPU/fract-match.ll
M llvm/test/CodeGen/AMDGPU/llvm.frexp.ll
M llvm/test/CodeGen/AMDGPU/llvm.rint.f64.ll
M llvm/test/CodeGen/AMDGPU/llvm.round.f64.ll
M llvm/test/CodeGen/AMDGPU/lround.ll
M llvm/test/CodeGen/AMDGPU/rem_i128.ll
M llvm/test/CodeGen/AMDGPU/roundeven.ll
M llvm/test/CodeGen/AMDGPU/select-undef.ll
M llvm/test/CodeGen/AMDGPU/srem.ll
M llvm/test/CodeGen/AMDGPU/srem64.ll
M llvm/test/CodeGen/AMDGPU/vector-reduce-smax.ll
M llvm/test/CodeGen/AMDGPU/vector-reduce-smin.ll
M llvm/test/CodeGen/AMDGPU/vector-reduce-umax.ll
M llvm/test/CodeGen/AMDGPU/vector-reduce-umin.ll
Log Message:
-----------
[AMDGPU] Add freeze for LowerSELECT (#148796)
Trying to solve https://github.com/llvm/llvm-project/issues/147635
Add freeze for legalizer when breaking i64 select to 2 i32 select.
Several tests changed, still need to investigate why.
---------
Co-authored-by: Shilei Tian <i at tianshilei.me>
Commit: 5fe9b5235298dc67864e947ea23df201aec177fc
https://github.com/llvm/llvm-project/commit/5fe9b5235298dc67864e947ea23df201aec177fc
Author: Shoreshen <372660931 at qq.com>
Date: 2025-07-18 (Fri, 18 Jul 2025)
Changed paths:
M llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
M llvm/test/CodeGen/AMDGPU/fmaximum3.ll
M llvm/test/CodeGen/AMDGPU/fminimum3.ll
M llvm/test/CodeGen/AMDGPU/fnearbyint.ll
M llvm/test/CodeGen/AMDGPU/fract-match.ll
M llvm/test/CodeGen/AMDGPU/freeze.ll
M llvm/test/CodeGen/AMDGPU/llvm.frexp.ll
M llvm/test/CodeGen/AMDGPU/llvm.rint.f64.ll
M llvm/test/CodeGen/AMDGPU/llvm.round.f64.ll
M llvm/test/CodeGen/AMDGPU/lround.ll
M llvm/test/CodeGen/AMDGPU/roundeven.ll
Log Message:
-----------
Add FABS to canCreateUndefOrPoison (#149440)
FABS will not create undef/poison, add it into canCreateUndefOrPoison
return false
Commit: 06528070fce04d580821b3448f1d5321e0a9a97b
https://github.com/llvm/llvm-project/commit/06528070fce04d580821b3448f1d5321e0a9a97b
Author: Vikram Hegde <115221833+vikramRH at users.noreply.github.com>
Date: 2025-07-18 (Fri, 18 Jul 2025)
Changed paths:
M llvm/include/llvm/CodeGen/MachineFunctionAnalysis.h
M llvm/include/llvm/IR/PassManager.h
M llvm/include/llvm/Passes/CodeGenPassBuilder.h
M llvm/lib/CodeGen/MachineFunctionAnalysis.cpp
M llvm/lib/Passes/PassRegistry.def
M llvm/test/CodeGen/AMDGPU/llc-pipeline-npm.ll
M llvm/test/tools/llc/new-pm/start-stop.ll
Log Message:
-----------
[CodeGen][NPM] Clear MachineFunctions without using PA (#148113)
same as https://github.com/llvm/llvm-project/pull/139517
This replaces the InvalidateAnalysisPass<MachineFunctionAnalysis> pass.
There are no cross-function analysis requirements right now, so clearing
all analyses works for the last pass in the pipeline.
Having the InvalidateAnalysisPass<MachineFunctionAnalysis>() is causing
a problem with ModuleToCGSCCPassAdaptor by deleting machine functions
for other functions and ending up with exactly one correctly compiled
MF, with the rest being vanished.
This is because ModuleToCGSCCPAdaptor propagates PassPA (received from
the CGSCCToFunctionPassAdaptor that runs the actual codegen pipeline on
MFs) to the next SCC. That causes MFA invalidation on functions in the
next SCC.
For us, PassPA happens to be returned from
invalidate<machine-function-analysis> which abandons the
MachineFunctionAnalysis. So while the first function runs through the
pipeline normally, invalidate also deletes the functions in the next SCC
before its pipeline is run. (this seems to be the intended mechanism of
the CG adaptor to allow cross-SCC invalidations.
Co-authored-by : Oke, Akshat
<[Akshat.Oke at amd.com](mailto:Akshat.Oke at amd.com)>
Commit: 1614c3b3c74b50dc6d5a7f359897bca221de931b
https://github.com/llvm/llvm-project/commit/1614c3b3c74b50dc6d5a7f359897bca221de931b
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2025-07-18 (Fri, 18 Jul 2025)
Changed paths:
M llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
M llvm/lib/Target/AMDGPU/SIInstrInfo.h
M llvm/test/CodeGen/AMDGPU/buffer-fat-pointers-memcpy.ll
M llvm/test/CodeGen/AMDGPU/inflate-av-remat-imm.mir
M llvm/test/CodeGen/AMDGPU/inflated-reg-class-snippet-copy-use-after-free.mir
M llvm/test/CodeGen/AMDGPU/regalloc-undef-copy-fold.mir
M llvm/test/CodeGen/AMDGPU/spill-agpr.mir
M llvm/test/CodeGen/AMDGPU/swdev502267-use-after-free-last-chance-recoloring-alloc-succeeds.mir
Log Message:
-----------
AMDGPU: Always use AV spill pseudos on targets with AGPRs (#149099)
This increases allocator freedom to inflate register classes
to the AV class, we don't need to introduce a new restriction
by basing the opcode on the current virtual register class.
Ideally we would avoid this if we don't have any allocatable
AGPRs for the function, but it probably doesn't make much
difference in the end result if they are excluded from the
final allocation order.
Commit: c435cd173059863b44262ace75e0f381bbc6cb86
https://github.com/llvm/llvm-project/commit/c435cd173059863b44262ace75e0f381bbc6cb86
Author: Antonio Frighetto <me at antoniofrighetto.com>
Date: 2025-07-18 (Fri, 18 Jul 2025)
Changed paths:
M llvm/lib/Transforms/Utils/SimplifyCFG.cpp
M llvm/test/Transforms/SimplifyCFG/switch-dup-bbs.ll
M llvm/test/Transforms/SimplifyCFG/switch-range-to-icmp.ll
Log Message:
-----------
[SimplifyCFG] Cache unique predecessors in `simplifyDuplicateSwitchArms`
Avoid repeatedly querying `getUniquePredecessor` for already-visited
switch successors so as not to incur quadratic runtime.
Fixes: https://github.com/llvm/llvm-project/issues/147239.
Commit: 176ae32de060d8c4767904bf16fbde3faa59b60a
https://github.com/llvm/llvm-project/commit/176ae32de060d8c4767904bf16fbde3faa59b60a
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2025-07-18 (Fri, 18 Jul 2025)
Changed paths:
M llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
M llvm/test/CodeGen/AMDGPU/accvgpr-copy.mir
Log Message:
-----------
AMDGPU: Fix introducing use of killed vgpr in gfx908 agpr copy (#149291)
When searching for an existing VGPR source for an AGPR to AGPR
copy on gfx908, this wasn't verifying the vgpr wasn't killed by
other prior uses.
Commit: 90f733ce6eaea6930c31d7aa320e18a5ef00ac75
https://github.com/llvm/llvm-project/commit/90f733ce6eaea6930c31d7aa320e18a5ef00ac75
Author: Florian Hahn <flo at fhahn.com>
Date: 2025-07-18 (Fri, 18 Jul 2025)
Changed paths:
M llvm/test/Transforms/LoopUnroll/AArch64/apple-unrolling.ll
A llvm/test/Transforms/LoopUnroll/partial-unroll-reductions.ll
A llvm/test/Transforms/LoopUnroll/runtime-unroll-reductions.ll
Log Message:
-----------
[LoopUnroll] Add tests for unrolling loops with reductions.
Add tests for unrolling loops with reductions. In some cases, multiple
parallel reduction phis could be retained to improve performance.
Commit: 5bac67d9213da8afa0e35199395774ca3c7daa39
https://github.com/llvm/llvm-project/commit/5bac67d9213da8afa0e35199395774ca3c7daa39
Author: Diana Picus <Diana-Magda.Picus at amd.com>
Date: 2025-07-18 (Fri, 18 Jul 2025)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPUResourceUsageAnalysis.cpp
M llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
M llvm/lib/Target/AMDGPU/SIRegisterInfo.h
Log Message:
-----------
[AMDGPU] Use SIRegisterInfo to compute used registers. NFCI (#149051)
Simplify the code in AMDGPUResourceUsageAnalysis to rely more
on the TargetRegisterInfo for computing the number of used SGPRs and
AGPRs. This is a preliminary refactoring split out from #144855.
(While we could technically use TRI to compute the used number of VGPRs
at this point too, I'm leaving some of the original code in since for
VGPRs we're going to introduce some special cases).
Commit: beec840822867079b829f35cbd4b360aa8971438
https://github.com/llvm/llvm-project/commit/beec840822867079b829f35cbd4b360aa8971438
Author: Younan Zhang <zyn7109 at gmail.com>
Date: 2025-07-18 (Fri, 18 Jul 2025)
Changed paths:
M clang/docs/ReleaseNotes.rst
M clang/lib/Sema/SemaConcept.cpp
M clang/test/SemaTemplate/concepts-using-decl.cpp
Log Message:
-----------
[Clang] Ensure correct parameters are in the scope for constraint equivalence checking (#149264)
This is another case where untransformed constraint expressions led to
inconsistent transforms.
We did fix some of those issues by looking at parent scopes, however the
parent instantiation scope is not always available because we could also
reach here after the parents get instantiated.
Fixes #146614
Commit: 2a1869b9815c1f59af9eae91a3ef7e7d78e8f4f2
https://github.com/llvm/llvm-project/commit/2a1869b9815c1f59af9eae91a3ef7e7d78e8f4f2
Author: Jeremy Morse <jeremy.morse at sony.com>
Date: 2025-07-18 (Fri, 18 Jul 2025)
Changed paths:
M llvm/include/llvm/IR/DebugInfo.h
M llvm/include/llvm/IR/DebugInfoMetadata.h
M llvm/lib/IR/DebugInfo.cpp
M llvm/lib/IR/DebugInfoMetadata.cpp
M llvm/lib/Transforms/InstCombine/InstCombineInternal.h
M llvm/lib/Transforms/InstCombine/InstructionCombining.cpp
M llvm/lib/Transforms/Scalar/ConstraintElimination.cpp
M llvm/lib/Transforms/Utils/CodeExtractor.cpp
M llvm/lib/Transforms/Utils/InlineFunction.cpp
M llvm/lib/Transforms/Utils/Local.cpp
M llvm/lib/Transforms/Utils/PromoteMemoryToRegister.cpp
M llvm/unittests/Transforms/Utils/DebugifyTest.cpp
M llvm/unittests/Transforms/Utils/LocalTest.cpp
Log Message:
-----------
[DebugInfo] Shave even more users of DbgVariableIntrinsic from LLVM (#149136)
At this stage I'm just opportunistically deleting any code using
debug-intrinsic types, largely adjacent to calls to findDbgUsers. I'll
get to deleting that in probably one or more two commits.
Commit: 74c396afb26dec74c0b799e218c63f1a26e90d21
https://github.com/llvm/llvm-project/commit/74c396afb26dec74c0b799e218c63f1a26e90d21
Author: clubby789 <jamie at hill-daniel.co.uk>
Date: 2025-07-18 (Fri, 18 Jul 2025)
Changed paths:
M llvm/lib/Transforms/Scalar/DeadStoreElimination.cpp
M llvm/test/Transforms/DeadStoreElimination/zeroed-missing.ll
Log Message:
-----------
[DSE] Remove `uninitialized` from `allockind` when creating dummy zeroed variant function (#149336)
cc https://github.com/llvm/llvm-project/pull/138299
rustc sets `allockind("uninitialized")` - if we copy the attributes
as-is when creating a dummy function, Verify complains about
`allockind("uninitialized,zeroed")` conflicting, so we need to clear the
flag.
Co-authored-by: Jamie Hill-Daniel <jamie at osec.io>
Commit: 3f991f5067bd45064af4afb0594ab5d614e357df
https://github.com/llvm/llvm-project/commit/3f991f5067bd45064af4afb0594ab5d614e357df
Author: Timm Baeder <tbaeder at redhat.com>
Date: 2025-07-18 (Fri, 18 Jul 2025)
Changed paths:
M clang/lib/AST/ByteCode/InterpBlock.h
M clang/lib/AST/ByteCode/InterpBuiltin.cpp
Log Message:
-----------
[clang][bytecode][NFC] Remove unused includes (#149460)
Commit: 1e7446fe45f2de473fe180a065733f68ced8e653
https://github.com/llvm/llvm-project/commit/1e7446fe45f2de473fe180a065733f68ced8e653
Author: Trevor Gross <tmgross at umich.edu>
Date: 2025-07-18 (Fri, 18 Jul 2025)
Changed paths:
M llvm/lib/Target/X86/X86CallingConv.cpp
Log Message:
-----------
[X86] Correct an assertion message (NFC) (#149386)
I introduced this in a78a0f8d2043 ("[X86] Align f128 and i128 to 16
bytes"). Correct the message here.
Commit: cda28e203d8f396af65cd4e19c62cfaa58480280
https://github.com/llvm/llvm-project/commit/cda28e203d8f396af65cd4e19c62cfaa58480280
Author: Oleksandr T. <oleksandr.tarasiuk at outlook.com>
Date: 2025-07-18 (Fri, 18 Jul 2025)
Changed paths:
M clang/docs/ReleaseNotes.rst
M clang/include/clang/StaticAnalyzer/Core/PathSensitive/ExprEngine.h
M clang/lib/StaticAnalyzer/Core/ExprEngine.cpp
M clang/lib/StaticAnalyzer/Core/ExprEngineC.cpp
A clang/test/Analysis/div-zero-cxx20.cpp
M clang/test/Analysis/div-zero.cpp
Log Message:
-----------
[analyzer] Support parenthesized list initialization (CXXParenListInitExpr) (#148988)
This patch addresses the lack of support for parenthesized
initialization in the Clang Static Analyzer's `ExprEngine`. Previously,
initializations such as `V v(1, 2);` were not modeled properly, which
could lead to false negatives in analyses like `DivideZero`.
```cpp
struct A {
int x;
A(int v) : x(v) {}
};
int t() {
A a(42);
return 1 / (a.x - 42); // expected-warning {{Division by zero}}
}
```
Fixes #148875
Commit: daa6de37bac9e547d37a3c5f2c9a51559679a7ed
https://github.com/llvm/llvm-project/commit/daa6de37bac9e547d37a3c5f2c9a51559679a7ed
Author: Fabian Ritter <fabian.ritter at amd.com>
Date: 2025-07-18 (Fri, 18 Jul 2025)
Changed paths:
M llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
M llvm/lib/Target/AMDGPU/SIISelLowering.cpp
M llvm/test/CodeGen/AMDGPU/ptradd-sdag-optimizations.ll
Log Message:
-----------
[AMDGPU][SDAG] Add target-specific ISD::PTRADD combines (#143673)
This patch adds several (AMDGPU-)target-specific DAG combines for
ISD::PTRADD nodes that reproduce existing similar transforms for
ISD::ADD nodes. There is no functional change intended for the existing
target-specific PTRADD combine.
For SWDEV-516125.
Commit: efedd49a22832f8b0981a084c503cdcdf4ed8e65
https://github.com/llvm/llvm-project/commit/efedd49a22832f8b0981a084c503cdcdf4ed8e65
Author: Fabian Ritter <fabian.ritter at amd.com>
Date: 2025-07-18 (Fri, 18 Jul 2025)
Changed paths:
M llvm/test/CodeGen/AMDGPU/ptradd-sdag-optimizations.ll
Log Message:
-----------
[AMDGPU][SDAG] Test ISD::PTRADD handling in VOP3 patterns (#143880)
Pre-committing tests to show improvements in a follow-up PR.
Commit: 64a0478e08829ec6bcae2b05e154aa58c2c46ac0
https://github.com/llvm/llvm-project/commit/64a0478e08829ec6bcae2b05e154aa58c2c46ac0
Author: tangaac <tangyan01 at loongson.cn>
Date: 2025-07-18 (Fri, 18 Jul 2025)
Changed paths:
M llvm/lib/Target/LoongArch/LoongArchFrameLowering.cpp
M llvm/test/CodeGen/LoongArch/calling-conv-common.ll
M llvm/test/CodeGen/LoongArch/calling-conv-half.ll
M llvm/test/CodeGen/LoongArch/can-not-realign-stack.ll
M llvm/test/CodeGen/LoongArch/emergency-spill-slot.ll
M llvm/test/CodeGen/LoongArch/frame.ll
M llvm/test/CodeGen/LoongArch/intrinsic-memcpy.ll
M llvm/test/CodeGen/LoongArch/lasx/fpowi.ll
M llvm/test/CodeGen/LoongArch/lasx/ir-instruction/extractelement.ll
M llvm/test/CodeGen/LoongArch/lasx/ir-instruction/insertelement.ll
M llvm/test/CodeGen/LoongArch/llvm.sincos.ll
A llvm/test/CodeGen/LoongArch/lsx/pr146455.ll
M llvm/test/CodeGen/LoongArch/stack-realignment-with-variable-sized-objects.ll
M llvm/test/CodeGen/LoongArch/stack-realignment.ll
M llvm/test/CodeGen/LoongArch/unaligned-memcpy-inline.ll
M llvm/test/CodeGen/LoongArch/vararg.ll
Log Message:
-----------
[LoongArch] Strengthen stack size estimation for LSX/LASX extension (#146455)
This patch adds an emergency spill slot when ran out of registers.
PR #139201 introduces `vstelm` instructions with only 8-bit imm offset,
it causes no spill slot to store the spill registers.
Commit: a96121089b9c94e08c6632f91f2dffc73c0ffa28
https://github.com/llvm/llvm-project/commit/a96121089b9c94e08c6632f91f2dffc73c0ffa28
Author: Nikita Popov <npopov at redhat.com>
Date: 2025-07-18 (Fri, 18 Jul 2025)
Changed paths:
M llvm/include/llvm/ADT/StringTable.h
M llvm/include/llvm/IR/RuntimeLibcalls.h
M llvm/lib/IR/RuntimeLibcalls.cpp
M llvm/lib/Object/IRSymtab.cpp
M llvm/utils/TableGen/Basic/RuntimeLibcallsEmitter.cpp
Log Message:
-----------
Revert "RuntimeLibcalls: Add methods to recognize libcall names (#149001)"
This reverts commit 45477add8dfe9851605697bd908b49f0ec244625.
This causes a significant LTO compile-time regression.
Commit: 8f3e78f9715cb7085d03686c7bd72e20ce248b04
https://github.com/llvm/llvm-project/commit/8f3e78f9715cb7085d03686c7bd72e20ce248b04
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2025-07-18 (Fri, 18 Jul 2025)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPU.h
M llvm/lib/Target/AMDGPU/AMDGPUPassRegistry.def
A llvm/lib/Target/AMDGPU/AMDGPUPrepareAGPRAlloc.cpp
A llvm/lib/Target/AMDGPU/AMDGPUPrepareAGPRAlloc.h
M llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
M llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.h
M llvm/lib/Target/AMDGPU/CMakeLists.txt
M llvm/lib/Target/AMDGPU/SIInstrInfo.h
M llvm/test/CodeGen/AMDGPU/agpr-remat.ll
A llvm/test/CodeGen/AMDGPU/amdgpu-prepare-agpr-alloc.mir
M llvm/test/CodeGen/AMDGPU/branch-folding-implicit-def-subreg.ll
M llvm/test/CodeGen/AMDGPU/llc-pipeline-npm.ll
M llvm/test/CodeGen/AMDGPU/llc-pipeline.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.mfma.ll
M llvm/test/CodeGen/AMDGPU/no-fold-accvgpr-mov.ll
M llvm/test/CodeGen/AMDGPU/no-fold-accvgpr-mov.mir
M llvm/test/CodeGen/AMDGPU/no-fold-accvgpr-read.mir
M llvm/test/CodeGen/AMDGPU/partial-regcopy-and-spill-missed-at-regalloc.ll
M llvm/test/CodeGen/AMDGPU/spill-vector-superclass.ll
Log Message:
-----------
AMDGPU: Add pass to replace constant materialize with AV pseudos (#149292)
If we have a v_mov_b32 or v_accvgpr_write_b32 with an inline immediate,
replace it with a pseudo which writes to the combined AV_* class. This
relaxes the operand constraints, which will allow the allocator to
inflate the register class to AV_* to potentially avoid spilling.
The allocator does not know how to replace an instruction to enable
the change of register class. I originally tried to do this by changing
all of the places we introduce v_mov_b32 with immediate, but it's along
tail of niche cases that require manual updating. Plus we can restrict
this to only run on functions where we know we will be allocating AGPRs.
Commit: 20fc297ce3c2a2151bf618cf515f2b1981d4821c
https://github.com/llvm/llvm-project/commit/20fc297ce3c2a2151bf618cf515f2b1981d4821c
Author: Nicholas Guy <nicholas.guy at arm.com>
Date: 2025-07-18 (Fri, 18 Jul 2025)
Changed paths:
M llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
M llvm/lib/Transforms/Vectorize/VPlanAnalysis.cpp
M llvm/lib/Transforms/Vectorize/VPlanAnalysis.h
A llvm/test/Transforms/LoopVectorize/AArch64/maxbandwidth-regpressure.ll
Log Message:
-----------
[LoopVectorizer] Only check register pressure for VFs that have been enabled via maxBandwidth (#149056)
Currently if MaxBandwidth is enabled, the register pressure is checked
for each VF. This changes that to only perform said check if the VF
would not have otherwise been considered by the LoopVectorizer if
maxBandwidth was not enabled.
Theoretically this allows for higher VFs to be considered than would
otherwise be deemed "safe" (from a regpressure perspective), but more
concretely this reduces the amount of work done at compile-time when
maxBandwidth is enabled.
Commit: 88721d63d482cf8f95deb66e74462b2cf583be8f
https://github.com/llvm/llvm-project/commit/88721d63d482cf8f95deb66e74462b2cf583be8f
Author: David Spickett <david.spickett at linaro.org>
Date: 2025-07-18 (Fri, 18 Jul 2025)
Changed paths:
M lldb/test/Shell/SymbolFile/PDB/Inputs/UdtLayoutTest.script
Log Message:
-----------
[lldb][test] Fix PDB UdtLayoutTest
https://github.com/llvm/llvm-project/pull/149282 changed
the max children depth and that caused one part of the
output to become `{...}`.
The original PR set a higher limit for a different test,
so I'm doing the same here.
Commit: 3ce06b8c2196be6368f0e06862ac1849379cce41
https://github.com/llvm/llvm-project/commit/3ce06b8c2196be6368f0e06862ac1849379cce41
Author: Simon Tatham <simon.tatham at arm.com>
Date: 2025-07-18 (Fri, 18 Jul 2025)
Changed paths:
M clang/lib/Driver/ToolChain.cpp
M clang/test/Driver/print-multi-selection-flags.c
Log Message:
-----------
[Clang][Driver] Expose relocation model as multilib flags (#149132)
If a multilib collection contains libraries built for different methods
of accessing global data (via absolute address, or via a GOT in -fPIC
style, or as an offset from a fixed register in Arm -frwpi style), then
`multilib.yaml` will need to know which relocation model an application
is using in order to select the right library.
Even if a multilib collection only supports one relocation model, it's
still useful for `multilib.yaml` to be able to tell if the user has
selected the right one, so as to give a useful error message if they
haven't, instead of silently selecting a library that won't work.
In this commit we determine the PIC / ROPI / RWPI status using the
existing logic in `ParsePICArgs`, and translate it back into a canonical
set of multilib selection flags.
Commit: 28208c8e2713cdbc3ad39314e1cbd5c9efbe48d7
https://github.com/llvm/llvm-project/commit/28208c8e2713cdbc3ad39314e1cbd5c9efbe48d7
Author: Jeremy Morse <jeremy.morse at sony.com>
Date: 2025-07-18 (Fri, 18 Jul 2025)
Changed paths:
M llvm/lib/Transforms/Coroutines/CoroFrame.cpp
M llvm/lib/Transforms/Coroutines/CoroInternal.h
M llvm/lib/Transforms/Coroutines/CoroSplit.cpp
Log Message:
-----------
[DebugInfo] Remove debug-intrinsic coroutine codepaths (#149068)
There are a few duplicate paths/facilities in the coroutine code to deal
with both intrinsics and debug-records; we can now delete the intrinsic
version.
Commit: d883d5fecf8aa7db6daa0b163599d42ca00c5808
https://github.com/llvm/llvm-project/commit/d883d5fecf8aa7db6daa0b163599d42ca00c5808
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2025-07-18 (Fri, 18 Jul 2025)
Changed paths:
A llvm/test/CodeGen/AMDGPU/bad-agpr-vgpr-regalloc-priority.mir
Log Message:
-----------
AMDGPU: Add testcase with bad regalloc behavior
This demonstrates poor allocation due to not ordering
AV classes relative to the A and V classes
Commit: 534b9cdddde2d4f11516a8f689c6ba23a29b8bdc
https://github.com/llvm/llvm-project/commit/534b9cdddde2d4f11516a8f689c6ba23a29b8bdc
Author: Nicholas Guy <nicholas.guy at arm.com>
Date: 2025-07-18 (Fri, 18 Jul 2025)
Changed paths:
M llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
Log Message:
-----------
[LoopVectorizer][NFC] Update comment regarding VF register pressure. (#149478)
Commit: df9a864b046bb716e56f81409f6a01a17f3181d6
https://github.com/llvm/llvm-project/commit/df9a864b046bb716e56f81409f6a01a17f3181d6
Author: Ross Brunton <ross at codeplay.com>
Date: 2025-07-18 (Fri, 18 Jul 2025)
Changed paths:
M offload/plugins-nextgen/amdgpu/src/rtl.cpp
M offload/unittests/OffloadAPI/common/Fixtures.hpp
M offload/unittests/OffloadAPI/event/olWaitEvent.cpp
Log Message:
-----------
[Offload] Implement event sync in amdgpu (#149300)
Commit: 3121cc31baa1aed697cc07c72d283891ffa529f6
https://github.com/llvm/llvm-project/commit/3121cc31baa1aed697cc07c72d283891ffa529f6
Author: Michael Buch <michaelbuch12 at gmail.com>
Date: 2025-07-18 (Fri, 18 Jul 2025)
Changed paths:
M lldb/test/API/functionalities/data-formatter/nsdictionarysynth/TestNSDictionarySynthetic.py
Log Message:
-----------
[lldb][test] TestNSDictionarySynthetic.py: adjust ptr depth in test
Fixes failure after we introduced a default limit in
https://github.com/llvm/llvm-project/pull/149282
We already did this test change on the Apple fork.
Commit: 0b7a95a6fd81b31634a3723a0bea6d9d91bbc230
https://github.com/llvm/llvm-project/commit/0b7a95a6fd81b31634a3723a0bea6d9d91bbc230
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2025-07-18 (Fri, 18 Jul 2025)
Changed paths:
M llvm/include/llvm/ADT/StringTable.h
M llvm/include/llvm/IR/RuntimeLibcalls.h
M llvm/lib/IR/RuntimeLibcalls.cpp
M llvm/utils/TableGen/Basic/RuntimeLibcallsEmitter.cpp
Log Message:
-----------
Partially Reapply "RuntimeLibcalls: Add methods to recognize libcall names (#149001)"
This partially reverts commit a96121089b9c94e08c6632f91f2dffc73c0ffa28.
Drop the IRSymtab changes for now
Commit: 3bb4355bb83692d9c859043076db16baa86431e1
https://github.com/llvm/llvm-project/commit/3bb4355bb83692d9c859043076db16baa86431e1
Author: Timm Baeder <tbaeder at redhat.com>
Date: 2025-07-18 (Fri, 18 Jul 2025)
Changed paths:
M clang/lib/AST/ByteCode/InterpBuiltin.cpp
M clang/lib/AST/ByteCode/InterpFrame.cpp
M clang/test/AST/ByteCode/unions.cpp
Log Message:
-----------
[clang][bytecode] Report mutable reads when copying unions (#149320)
Commit: b7660a54157fd45e6276acf35176851196f5df71
https://github.com/llvm/llvm-project/commit/b7660a54157fd45e6276acf35176851196f5df71
Author: Timm Baeder <tbaeder at redhat.com>
Date: 2025-07-18 (Fri, 18 Jul 2025)
Changed paths:
M clang/lib/AST/ByteCode/Descriptor.cpp
M clang/lib/AST/ByteCode/Descriptor.h
M clang/lib/AST/ByteCode/Disasm.cpp
M clang/lib/AST/ByteCode/Interp.cpp
M clang/lib/AST/ByteCode/Pointer.h
M clang/test/AST/ByteCode/mutable.cpp
Log Message:
-----------
[clang][bytecode] Fix const-in-mutable fields (#149286)
For mutable and const fields, we have two bits in InlineDescriptor,
which both get inherited down the hierarchy. When a field is both const
and mutable, we CAN read from it if it is a mutable-in-const field, but
we _can't_ read from it if it is a const-in-mutable field. We need
another bit to distinguish the two cases.
Commit: b5e3fffd20a72d3451e31ac37ca4930014044cd0
https://github.com/llvm/llvm-project/commit/b5e3fffd20a72d3451e31ac37ca4930014044cd0
Author: Nicholas Guy <nicholas.guy at arm.com>
Date: 2025-07-18 (Fri, 18 Jul 2025)
Changed paths:
M llvm/test/Transforms/LoopVectorize/AArch64/maxbandwidth-regpressure.ll
Log Message:
-----------
[LoopVectorizer][NFC] Require asserts on maxbandwidth-regpressure.ll (#149484)
Fix for buildbot failure:
https://lab.llvm.org/buildbot/#/builders/11/builds/19837
Commit: ee8756e8551bc9ae5bf60e1ff16abaa95d61c234
https://github.com/llvm/llvm-project/commit/ee8756e8551bc9ae5bf60e1ff16abaa95d61c234
Author: Lucas Ramirez <11032120+lucas-rami at users.noreply.github.com>
Date: 2025-07-18 (Fri, 18 Jul 2025)
Changed paths:
M llvm/include/llvm/CodeGen/MachineBlockFrequencyInfo.h
M llvm/lib/CodeGen/MachineBlockFrequencyInfo.cpp
Log Message:
-----------
[LLVM] Make `MachineBlockFrequencyInfo`'s constructor arguments const (NFC) (#149279)
This avoids having to call `MachineBlockFrequencyInfo::calculate`
manually if one of the parameters is const.
Commit: 9e0c06d708a40bb3c8bd08acd982836cce718135
https://github.com/llvm/llvm-project/commit/9e0c06d708a40bb3c8bd08acd982836cce718135
Author: Antonio Frighetto <me at antoniofrighetto.com>
Date: 2025-07-18 (Fri, 18 Jul 2025)
Changed paths:
M clang/lib/CodeGen/CGCall.cpp
M clang/test/CodeGen/64bit-swiftcall.c
M clang/test/CodeGen/AArch64/byval-temp.c
M clang/test/CodeGen/AArch64/pure-scalable-args-empty-union.c
M clang/test/CodeGen/AArch64/pure-scalable-args.c
M clang/test/CodeGen/AArch64/struct-coerce-using-ptr.cpp
M clang/test/CodeGen/AArch64/sve-acle-__ARM_FEATURE_SVE_VECTOR_OPERATORS.c
M clang/test/CodeGen/AArch64/sve-acle-__ARM_FEATURE_SVE_VECTOR_OPERATORS.cpp
M clang/test/CodeGen/LoongArch/bitint.c
M clang/test/CodeGen/PowerPC/ppc64-vector.c
M clang/test/CodeGen/RISCV/riscv-abi.cpp
M clang/test/CodeGen/RISCV/riscv-vector-callingconv-llvm-ir.c
M clang/test/CodeGen/RISCV/riscv-vector-callingconv-llvm-ir.cpp
M clang/test/CodeGen/RISCV/riscv32-abi.c
M clang/test/CodeGen/RISCV/riscv32-vararg.c
M clang/test/CodeGen/RISCV/riscv64-abi.c
M clang/test/CodeGen/RISCV/riscv64-vararg.c
M clang/test/CodeGen/SystemZ/systemz-abi-vector.c
M clang/test/CodeGen/SystemZ/systemz-abi.c
M clang/test/CodeGen/SystemZ/systemz-inline-asm.c
M clang/test/CodeGen/X86/cx-complex-range.c
M clang/test/CodeGen/X86/x86_32-arguments-win32.c
M clang/test/CodeGen/X86/x86_64-arguments-win32.c
M clang/test/CodeGen/aapcs64-align.cpp
M clang/test/CodeGen/arm-aapcs-vfp.c
M clang/test/CodeGen/arm-abi-vector.c
M clang/test/CodeGen/arm-swiftcall.c
M clang/test/CodeGen/arm64-abi-vector.c
M clang/test/CodeGen/arm64-arguments.c
M clang/test/CodeGen/arm64-microsoft-arguments.cpp
M clang/test/CodeGen/armv7k-abi.c
M clang/test/CodeGen/atomic-arm64.c
M clang/test/CodeGen/attr-noundef.cpp
M clang/test/CodeGen/cx-complex-range.c
M clang/test/CodeGen/ext-int-cc.c
M clang/test/CodeGen/isfpclass.c
M clang/test/CodeGen/math-libcalls-tbaa-indirect-args.c
M clang/test/CodeGen/mingw-long-double.c
M clang/test/CodeGen/ms_abi.c
M clang/test/CodeGen/pass-by-value-noalias.c
M clang/test/CodeGen/ptrauth-in-c-struct.c
M clang/test/CodeGen/regcall.c
M clang/test/CodeGen/regcall2.c
M clang/test/CodeGen/regcall4.c
M clang/test/CodeGen/sparcv9-abi.c
M clang/test/CodeGen/vectorcall.c
M clang/test/CodeGen/win-fp128.c
M clang/test/CodeGen/win64-i128.c
M clang/test/CodeGen/windows-swiftcall.c
M clang/test/CodeGenCXX/aarch64-mangle-sve-vectors.cpp
M clang/test/CodeGenCXX/arm-cc.cpp
M clang/test/CodeGenCXX/attr-target-mv-inalloca.cpp
M clang/test/CodeGenCXX/copy-initialization.cpp
M clang/test/CodeGenCXX/debug-info.cpp
M clang/test/CodeGenCXX/empty-nontrivially-copyable.cpp
M clang/test/CodeGenCXX/fastcall.cpp
M clang/test/CodeGenCXX/homogeneous-aggregates.cpp
M clang/test/CodeGenCXX/inalloca-lambda.cpp
M clang/test/CodeGenCXX/inalloca-overaligned.cpp
M clang/test/CodeGenCXX/inalloca-vector.cpp
M clang/test/CodeGenCXX/inheriting-constructor.cpp
M clang/test/CodeGenCXX/member-function-pointer-calls.cpp
M clang/test/CodeGenCXX/microsoft-abi-arg-order.cpp
M clang/test/CodeGenCXX/microsoft-abi-byval-thunks.cpp
M clang/test/CodeGenCXX/microsoft-abi-member-pointers.cpp
M clang/test/CodeGenCXX/microsoft-abi-sret-and-byval.cpp
M clang/test/CodeGenCXX/microsoft-abi-unknown-arch.cpp
M clang/test/CodeGenCXX/ms-property.cpp
M clang/test/CodeGenCXX/nrvo.cpp
M clang/test/CodeGenCXX/pass-by-value-noalias.cpp
M clang/test/CodeGenCXX/ptrauth-qualifier-struct.cpp
M clang/test/CodeGenCXX/regparm.cpp
M clang/test/CodeGenCXX/trivial_abi.cpp
M clang/test/CodeGenCXX/uncopyable-args.cpp
M clang/test/CodeGenCXX/wasm-args-returns.cpp
M clang/test/CodeGenCXX/windows-x86-swiftcall.cpp
M clang/test/CodeGenObjC/nontrivial-c-struct-exception.m
M clang/test/CodeGenObjC/pass-by-value-noalias.m
M clang/test/CodeGenObjC/weak-in-c-struct.m
M clang/test/CodeGenObjCXX/objc-struct-cxx-abi.mm
M clang/test/CodeGenObjCXX/property-objects.mm
M clang/test/CodeGenObjCXX/ptrauth-struct-cxx-abi.mm
M clang/test/Headers/stdarg.cpp
M clang/test/OpenMP/for_firstprivate_codegen.cpp
M clang/test/OpenMP/parallel_firstprivate_codegen.cpp
M clang/test/OpenMP/sections_firstprivate_codegen.cpp
M clang/test/OpenMP/single_firstprivate_codegen.cpp
M clang/test/OpenMP/target_teams_distribute_firstprivate_codegen.cpp
M clang/test/OpenMP/target_teams_distribute_parallel_for_firstprivate_codegen.cpp
M clang/test/OpenMP/teams_distribute_firstprivate_codegen.cpp
M clang/test/OpenMP/teams_distribute_parallel_for_firstprivate_codegen.cpp
M clang/test/OpenMP/teams_firstprivate_codegen.cpp
Log Message:
-----------
[clang][CodeGen] Set `dead_on_return` when passing arguments indirectly
Let Clang emit `dead_on_return` attribute on pointer arguments
that are passed indirectly, namely, large aggregates that the
ABI mandates be passed by value; thus, the parameter is destroyed
within the callee. Writes to such arguments are not observable by
the caller after the callee returns.
This should desirably enable further MemCpyOpt/DSE optimizations.
Previous discussion: https://discourse.llvm.org/t/rfc-add-dead-on-return-attribute/86871.
Commit: 4fbe88fc46989b5b4e3b8913a915c7a3cd188bdf
https://github.com/llvm/llvm-project/commit/4fbe88fc46989b5b4e3b8913a915c7a3cd188bdf
Author: Phoebe Wang <phoebe.wang at intel.com>
Date: 2025-07-18 (Fri, 18 Jul 2025)
Changed paths:
M llvm/lib/TargetParser/X86TargetParser.cpp
Log Message:
-----------
[NFC] Add parentheses around arithmetic operand (#149489)
Commit: c9d8b68676dbf51996a76475313088f750697343
https://github.com/llvm/llvm-project/commit/c9d8b68676dbf51996a76475313088f750697343
Author: Jeremy Morse <jeremy.morse at sony.com>
Date: 2025-07-18 (Fri, 18 Jul 2025)
Changed paths:
M llvm/include/llvm/Transforms/Utils/SSAUpdater.h
M llvm/lib/CodeGen/CodeGenPrepare.cpp
M llvm/lib/CodeGen/MachineDebugify.cpp
M llvm/lib/Transforms/Coroutines/SpillUtils.cpp
M llvm/lib/Transforms/IPO/MergeFunctions.cpp
M llvm/lib/Transforms/InstCombine/InstructionCombining.cpp
M llvm/lib/Transforms/Scalar/JumpThreading.cpp
M llvm/lib/Transforms/Scalar/LoopStrengthReduce.cpp
M llvm/lib/Transforms/Utils/Debugify.cpp
M llvm/lib/Transforms/Utils/Local.cpp
M llvm/lib/Transforms/Utils/LoopRotationUtils.cpp
M llvm/lib/Transforms/Utils/SSAUpdater.cpp
M llvm/tools/llvm-dis/llvm-dis.cpp
M llvm/unittests/CodeGen/LexicalScopesTest.cpp
M llvm/unittests/IR/DebugInfoTest.cpp
Log Message:
-----------
[DebugInfo] Suppress lots of users of DbgValueInst (#149476)
This is another prune of dead code -- we never generate debug intrinsics
nowadays, therefore there's no need for these codepaths to run.
---------
Co-authored-by: Nikita Popov <github at npopov.com>
Commit: 369f749dc434ec0339f5fb13376e1bc92e1d51d9
https://github.com/llvm/llvm-project/commit/369f749dc434ec0339f5fb13376e1bc92e1d51d9
Author: Nikita Popov <npopov at redhat.com>
Date: 2025-07-18 (Fri, 18 Jul 2025)
Changed paths:
M llvm/test/Transforms/SLPVectorizer/X86/split-node-reorder-node-with-ops.ll
Log Message:
-----------
[SLP] Remove lifetime.start on null pointer in test (NFC)
Commit: 6c63316ee17462c97c722a960680b2b45d2fff4d
https://github.com/llvm/llvm-project/commit/6c63316ee17462c97c722a960680b2b45d2fff4d
Author: Valentin Clement (バレンタイン クレメン) <clementval at gmail.com>
Date: 2025-07-18 (Fri, 18 Jul 2025)
Changed paths:
M flang/lib/Lower/ConvertVariable.cpp
M flang/test/Lower/CUDA/cuda-set-allocator.cuf
Log Message:
-----------
[flang][cuda] Support device component in a pointer or allocatable derived-type (#149418)
Commit: 4bbc70ed28a85036fb718e86424bb1d8a643005f
https://github.com/llvm/llvm-project/commit/4bbc70ed28a85036fb718e86424bb1d8a643005f
Author: Nico Weber <thakis at chromium.org>
Date: 2025-07-18 (Fri, 18 Jul 2025)
Changed paths:
M llvm/utils/gn/secondary/llvm/test/BUILD.gn
A llvm/utils/gn/secondary/llvm/tools/llvm-ir2vec/BUILD.gn
Log Message:
-----------
[gn] port d994487db78 (llvm-ir2vec)
Commit: 8b068149547cb3043e4427899851dc70ca1eb885
https://github.com/llvm/llvm-project/commit/8b068149547cb3043e4427899851dc70ca1eb885
Author: LLVM GN Syncbot <llvmgnsyncbot at gmail.com>
Date: 2025-07-18 (Fri, 18 Jul 2025)
Changed paths:
M llvm/utils/gn/secondary/llvm/lib/Target/AMDGPU/BUILD.gn
Log Message:
-----------
[gn build] Port 8f3e78f9715c
Commit: 4c701956341ff88f580d240be072461a1ba6d7f5
https://github.com/llvm/llvm-project/commit/4c701956341ff88f580d240be072461a1ba6d7f5
Author: lonely eagle <2020382038 at qq.com>
Date: 2025-07-18 (Fri, 18 Jul 2025)
Changed paths:
M mlir/docs/Tutorials/transform/Ch2.md
Log Message:
-----------
[mlir][transform] Fix ch2 and additional documentation (#148407)
Fixed error code in example.In addition to this, the content in the documentation has been improved by adding links to the code repository.
Commit: a9f81430725cb3d9a776d9b743078a452cd8e3aa
https://github.com/llvm/llvm-project/commit/a9f81430725cb3d9a776d9b743078a452cd8e3aa
Author: Sjoerd Meijer <smeijer at nvidia.com>
Date: 2025-07-18 (Fri, 18 Jul 2025)
Changed paths:
M llvm/lib/Transforms/Scalar/LoopInterchange.cpp
A llvm/test/Transforms/LoopInterchange/force-interchange.ll
Log Message:
-----------
[LoopInterchange] Ignore the cost-model, force interchange if legal (#148858)
This is and has been proven useful for testing purposes, to get more
test coverage.
Commit: 602d43cfd1fe7cc47146b6327d8df6e5e0ec47ae
https://github.com/llvm/llvm-project/commit/602d43cfd1fe7cc47146b6327d8df6e5e0ec47ae
Author: Shilei Tian <i at tianshilei.me>
Date: 2025-07-18 (Fri, 18 Jul 2025)
Changed paths:
M clang/include/clang/Basic/BuiltinsAMDGPU.def
M clang/lib/CodeGen/TargetBuiltins/AMDGPU.cpp
M clang/test/CodeGenOpenCL/builtins-amdgcn-gfx1250.cl
Log Message:
-----------
[Clang][AMDGPU] Add the missing builtin `__builtin_amdgcn_sqrt_bf16` (#149447)
Co-authored-by: Mekhanoshin, Stanislav <Stanislav.Mekhanoshin at amd.com>
Commit: 311847be4ca911e191c67245799fafe2e4d8ba73
https://github.com/llvm/llvm-project/commit/311847be4ca911e191c67245799fafe2e4d8ba73
Author: Ross Brunton <ross at codeplay.com>
Date: 2025-07-18 (Fri, 18 Jul 2025)
Changed paths:
M offload/plugins-nextgen/amdgpu/src/rtl.cpp
M offload/plugins-nextgen/common/include/PluginInterface.h
M offload/plugins-nextgen/cuda/src/rtl.cpp
Log Message:
-----------
[Offload] Allow "tagging" device info entries with offload keys (#147317)
When generating the device info tree, nodes can be marked with an
offload Device Info value. The nodes can also look up children based
on this value.
Commit: 03b7766dba2f63ee7c9e67f915ea8394f6426f9a
https://github.com/llvm/llvm-project/commit/03b7766dba2f63ee7c9e67f915ea8394f6426f9a
Author: Michael Buch <michaelbuch12 at gmail.com>
Date: 2025-07-18 (Fri, 18 Jul 2025)
Changed paths:
M lldb/source/Expression/IRExecutionUnit.cpp
Log Message:
-----------
[lldb][Expression][NFC] Make LoadAddressResolver::m_target a reference (#149490)
The only place that passes a target to `LoadAddressResolver` already
checks for pointer validity. And inside of the resolver we have been
dereferencing the target anyway without nullptr checks. So codify the
non-nullness of `m_target` by making it a reference.
Commit: 6112ebde0cdd31694536d0ac20a38e5f70f6185a
https://github.com/llvm/llvm-project/commit/6112ebde0cdd31694536d0ac20a38e5f70f6185a
Author: Sergei Barannikov <barannikov88 at gmail.com>
Date: 2025-07-18 (Fri, 18 Jul 2025)
Changed paths:
M llvm/lib/Target/RISCV/RISCVFrameLowering.cpp
M llvm/test/CodeGen/RISCV/short-forward-branch-opt.ll
M llvm/test/CodeGen/RISCV/zdinx-spill.ll
Log Message:
-----------
[RISCV] Guard CFI emission code with MF.needsFrameMoves() (#136060)
Currently, AsmPrinter skips CFI instructions created by a backend if
they are not needed. I'd like to change that so that it always
prints/encodes CFI instructions if a backend created them.
This change should slightly (perhaps negligibly) improve compile time as
post-PEI passes no longer need to skip over these instructions in
no-exceptions no-debug builds, and will allow to simplify convoluted
logic in AsmPrinter once other targets stop emitting CFI instructions
when they are not needed (that's my final goal).
The changes in a test seem to be caused by slightly different post-RA
scheduling in the absence of CFI instructions.
Commit: 7b541c931e975840c0ef86d8ebd16856d17c0c85
https://github.com/llvm/llvm-project/commit/7b541c931e975840c0ef86d8ebd16856d17c0c85
Author: Aiden Grossman <aidengrossman at google.com>
Date: 2025-07-18 (Fri, 18 Jul 2025)
Changed paths:
M .github/workflows/build-ci-container-windows.yml
M .github/workflows/build-ci-container.yml
Log Message:
-----------
[Github] Build CI Containers in Stacked PRs (#149346)
Currently the pull_request event on the build CI container workflows are
restricted to main. This prevents building them on stacked PRs. This is
a bit annoying because we do not get the CI to test that everything is
working until all of the base PRs have landed and the target branch
becomes main.
Commit: 5f531827a4b90f6e0051056fffd8642ae1c677e6
https://github.com/llvm/llvm-project/commit/5f531827a4b90f6e0051056fffd8642ae1c677e6
Author: Nikita Popov <npopov at redhat.com>
Date: 2025-07-18 (Fri, 18 Jul 2025)
Changed paths:
M llvm/lib/Transforms/Scalar/LoopStrengthReduce.cpp
A llvm/test/Transforms/LoopStrengthReduce/X86/lifetime-use.ll
Log Message:
-----------
[LSR] Do not consider uses in lifetime intrinsics (#149492)
We should ignore uses of pointers in lifetime intrinsics, as these are
not actually materialized in the final code, so don't affect register
pressure or anything else LSR needs to model.
Handling these only results in peculiar rewrites where additional
intermediate GEPs are introduced.
Commit: 22076644645a7731f0ec7a81fe78168cf5c2ed63
https://github.com/llvm/llvm-project/commit/22076644645a7731f0ec7a81fe78168cf5c2ed63
Author: bd1976bris <Ben.Dunbobbin at sony.com>
Date: 2025-07-18 (Fri, 18 Jul 2025)
Changed paths:
M clang/test/Sema/dllexport.c
Log Message:
-----------
[Clang][Test] Add PS5 and WI cases to clang/test/Sema/dllexport.c (#148818)
Windows Itanium and PS5 are both Itanium C++ ABI variants which have the
goal of semantic compatibility with Microsoft C++ code that uses
dllimport/export.
This patch adds Windows Itanium and PS5 triple testing to
clang/test/Sema/dllexport.c. We have this testing in our downstream
toolchain - for some reason it was not added upstream when the work for
supporting dllimport/export was done.
Commit: 44cd5027f826d1bc82e5e851d1012cc321806d12
https://github.com/llvm/llvm-project/commit/44cd5027f826d1bc82e5e851d1012cc321806d12
Author: Paul Walker <paul.walker at arm.com>
Date: 2025-07-18 (Fri, 18 Jul 2025)
Changed paths:
M llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
M llvm/test/CodeGen/AArch64/sve-intrinsics-ldst-ext.ll
Log Message:
-----------
[LLVM][CodeGen][SVE] List MVTs that are desirable for extending loads. (#149153)
Extend AArch64TargetLowering::isVectorLoadExtDesirable to specify the
set of MVT for which load extension is desirable.
Fixes https://github.com/llvm/llvm-project/issues/148939
Commit: 37ea9d88a3b8224ffa3b117749a74b1f2f1cfb53
https://github.com/llvm/llvm-project/commit/37ea9d88a3b8224ffa3b117749a74b1f2f1cfb53
Author: lntue <lntue at google.com>
Date: 2025-07-18 (Fri, 18 Jul 2025)
Changed paths:
M libc/cmake/modules/LLVMLibCTestRules.cmake
Log Message:
-----------
[libc] Fix tests' linking flags accidentally modified by #147931. (#149453)
https://github.com/llvm/llvm-project/pull/147931
Commit: 95b69e0e7014fd6eac98f53125857fddda022a62
https://github.com/llvm/llvm-project/commit/95b69e0e7014fd6eac98f53125857fddda022a62
Author: Shilei Tian <i at tianshilei.me>
Date: 2025-07-18 (Fri, 18 Jul 2025)
Changed paths:
M clang/test/CodeGenOpenCL/builtins-amdgcn-gfx1250.cl
M llvm/lib/Target/AMDGPU/VOP1Instructions.td
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.prng.ll
M llvm/test/MC/AMDGPU/gfx1250_asm_vop1-fake16.s
M llvm/test/MC/AMDGPU/gfx1250_asm_vop1.s
M llvm/test/MC/AMDGPU/gfx1250_asm_vop1_dpp16-fake16.s
M llvm/test/MC/AMDGPU/gfx1250_asm_vop1_dpp16.s
M llvm/test/MC/AMDGPU/gfx1250_asm_vop1_dpp8-fake16.s
M llvm/test/MC/AMDGPU/gfx1250_asm_vop1_dpp8.s
M llvm/test/MC/AMDGPU/gfx1250_asm_vop3_from_vop1-fake16.s
M llvm/test/MC/AMDGPU/gfx1250_asm_vop3_from_vop1.s
M llvm/test/MC/AMDGPU/gfx1250_asm_vop3_from_vop1_dpp16-fake16.s
M llvm/test/MC/AMDGPU/gfx1250_asm_vop3_from_vop1_dpp16.s
M llvm/test/MC/AMDGPU/gfx1250_asm_vop3_from_vop1_dpp8-fake16.s
M llvm/test/MC/AMDGPU/gfx1250_asm_vop3_from_vop1_dpp8.s
M llvm/test/MC/Disassembler/AMDGPU/gfx1250_dasm_vop1.txt
M llvm/test/MC/Disassembler/AMDGPU/gfx1250_dasm_vop1_dpp16.txt
M llvm/test/MC/Disassembler/AMDGPU/gfx1250_dasm_vop1_dpp8.txt
M llvm/test/MC/Disassembler/AMDGPU/gfx1250_dasm_vop3_from_vop1.txt
M llvm/test/MC/Disassembler/AMDGPU/gfx1250_dasm_vop3_from_vop1_dpp16.txt
M llvm/test/MC/Disassembler/AMDGPU/gfx1250_dasm_vop3_from_vop1_dpp8.txt
Log Message:
-----------
[AMDGPU] Add support for `v_prng_b32` on gfx1250 (#149450)
Co-authored-by: Mekhanoshin, Stanislav <Stanislav.Mekhanoshin at amd.com>
Commit: de959569f7ae468736b5f98ae3ce69b9eb3825ec
https://github.com/llvm/llvm-project/commit/de959569f7ae468736b5f98ae3ce69b9eb3825ec
Author: Nikita Popov <npopov at redhat.com>
Date: 2025-07-18 (Fri, 18 Jul 2025)
Changed paths:
M llvm/test/Instrumentation/AddressSanitizer/lifetime.ll
Log Message:
-----------
[AddressSanitizer] Generate test checks (NFC)
Commit: 6c705d11365b74b8207dc92f5c94ee7eb682a11b
https://github.com/llvm/llvm-project/commit/6c705d11365b74b8207dc92f5c94ee7eb682a11b
Author: Pengying Xu <xpy66swsry at gmail.com>
Date: 2025-07-18 (Fri, 18 Jul 2025)
Changed paths:
M lld/ELF/BPSectionOrderer.cpp
M lld/test/ELF/bp-section-orderer.s
Log Message:
-----------
[lld][elf] Skip BP ordering input sections with null data (#149265)
Commit: fd12e9aed889e4b546a2d5c4d3c0c10582fe9148
https://github.com/llvm/llvm-project/commit/fd12e9aed889e4b546a2d5c4d3c0c10582fe9148
Author: Paul Kirth <paulkirth at google.com>
Date: 2025-07-18 (Fri, 18 Jul 2025)
Changed paths:
M libcxx/test/libcxx/fuzzing/random.pass.cpp
M libcxx/test/std/depr/depr.c.headers/math_h.pass.cpp
M libcxx/test/std/numerics/c.math/cmath.pass.cpp
Log Message:
-----------
[libc++][tests] Update XFAIL annotations for some tests on Windows (#149124)
These tests still fail on Windows with clang-22, as reported in #70225.
This started failing due to the version bump to Clang 22.
Commit: fdce69a462101e1dce225014ee545858e363e4e2
https://github.com/llvm/llvm-project/commit/fdce69a462101e1dce225014ee545858e363e4e2
Author: Kazu Hirata <kazu at google.com>
Date: 2025-07-18 (Fri, 18 Jul 2025)
Changed paths:
M llvm/docs/CodingStandards.rst
Log Message:
-----------
[llvm] Improve grammar and punctuation of LLVM Coding Standards (#149463)
Commit: 151fffccf1340d8a2800664cbcaaa579ba772a4c
https://github.com/llvm/llvm-project/commit/151fffccf1340d8a2800664cbcaaa579ba772a4c
Author: Kazu Hirata <kazu at google.com>
Date: 2025-07-18 (Fri, 18 Jul 2025)
Changed paths:
M flang/lib/Lower/Bridge.cpp
M flang/lib/Lower/ConvertConstant.cpp
M flang/lib/Lower/ConvertExpr.cpp
M flang/lib/Lower/Runtime.cpp
M flang/lib/Lower/VectorSubscripts.cpp
M flang/lib/Optimizer/Builder/FIRBuilder.cpp
M flang/lib/Optimizer/Builder/Runtime/Intrinsics.cpp
M flang/lib/Optimizer/Builder/Runtime/Stop.cpp
M flang/lib/Optimizer/HLFIR/Transforms/LowerHLFIROrderedAssignments.cpp
M flang/lib/Optimizer/Transforms/MemoryUtils.cpp
M flang/lib/Optimizer/Transforms/PolymorphicOpConversion.cpp
M flang/lib/Optimizer/Transforms/SimplifyFIROperations.cpp
M flang/unittests/Optimizer/FortranVariableTest.cpp
Log Message:
-----------
[flang] Migrate away from ArrayRef(std::nullopt_t) (#149454)
ArrayRef(std::nullopt_t) has been deprecated. This patch replaces
std::nullopt with mlir::TypeRange{} or mlir::ValueRange{} as
appropriate.
Commit: 724cfce5801829340b240ba62e82a7e7199e971d
https://github.com/llvm/llvm-project/commit/724cfce5801829340b240ba62e82a7e7199e971d
Author: Corentin Jabot <corentinjabot at gmail.com>
Date: 2025-07-18 (Fri, 18 Jul 2025)
Changed paths:
M clang/include/clang/Sema/Overload.h
M clang/lib/Sema/SemaOverload.cpp
M clang/test/SemaCXX/overload-resolution-deferred-templates.cpp
Log Message:
-----------
[Clang] Do not assume a perfect match is a better match than a non-template non-perfect match (#149504)
This fixes a regression introduced by the "perfect match" overload
resolution mechanism introduced in 8c5a307.
[This does regress the performance noticeably (-0.7% for a stage 2
build)](https://llvm-compile-time-tracker.com/compare.php?from=42d2ae1034b287eb60563c370dbf52c59b66db20&to=82303bbc3e003c937ded498ac9f94f49a3fc3d90&stat=instructions:u),
however, the original patch had a +4% performance impact, so we are only
losing some of the gain, and this has
the benefit of being correct and more robust.
Fixes #147374
Commit: 55305db90a3f329bdf7917d1c8bf36b318e33c72
https://github.com/llvm/llvm-project/commit/55305db90a3f329bdf7917d1c8bf36b318e33c72
Author: RolandF77 <froese at ca.ibm.com>
Date: 2025-07-18 (Fri, 18 Jul 2025)
Changed paths:
M llvm/Maintainers.md
Log Message:
-----------
[PowerPC] Update maintainers (#149171)
Update PowerPC BE maintainers.
Commit: 0e4069580413f3869e94ec1f0f84a085b639226e
https://github.com/llvm/llvm-project/commit/0e4069580413f3869e94ec1f0f84a085b639226e
Author: Louis Dionne <ldionne.2 at gmail.com>
Date: 2025-07-18 (Fri, 18 Jul 2025)
Changed paths:
M libcxx/include/__config_site.in
M llvm/utils/gn/secondary/libcxx/include/BUILD.gn
Log Message:
-----------
[libc++] Remove unused _LIBCPP_HAS_NO_STD_MODULES macro from __config_site (#148902)
Since 1d6b6132f, that macro isn't used anywhere anymore.
Commit: f73e163278fd6e50fc7855e52625ddf2e537c912
https://github.com/llvm/llvm-project/commit/f73e163278fd6e50fc7855e52625ddf2e537c912
Author: Alex MacLean <amaclean at nvidia.com>
Date: 2025-07-18 (Fri, 18 Jul 2025)
Changed paths:
M llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
M llvm/test/CodeGen/NVPTX/i8x4-instructions.ll
A llvm/test/CodeGen/NVPTX/trunc-tofp.ll
Log Message:
-----------
[DAGCombiner] Fold [us]itofp of truncate (#149391)
Commit: e73cb43b44ddd7aeae7217aa1c9e7f8364a5e6df
https://github.com/llvm/llvm-project/commit/e73cb43b44ddd7aeae7217aa1c9e7f8364a5e6df
Author: Adam Siemieniuk <adam.siemieniuk at intel.com>
Date: 2025-07-18 (Fri, 18 Jul 2025)
Changed paths:
M mlir/include/mlir/Conversion/VectorToXeGPU/VectorToXeGPU.h
Log Message:
-----------
[mlir][xegpu] Remove unused custom pass declaration (#149278)
Removes unused declaration for pass creation.
Only the create function auto-generated from tablegen should be used.
Commit: ff5f3ae02aeac848dbb80ad9c652eae3ec107201
https://github.com/llvm/llvm-project/commit/ff5f3ae02aeac848dbb80ad9c652eae3ec107201
Author: Kelvin Li <kli at ca.ibm.com>
Date: 2025-07-18 (Fri, 18 Jul 2025)
Changed paths:
M flang/test/Semantics/PowerPC/ppc-vector-types01.f90
M flang/test/Semantics/PowerPC/ppc-vector-types02.f90
Log Message:
-----------
[flang] convert program name to upper case (NFC) (#149508)
Commit: 5f001294b1d42a0b4146e0b08ccae72667de6a5d
https://github.com/llvm/llvm-project/commit/5f001294b1d42a0b4146e0b08ccae72667de6a5d
Author: Brad Smith <brad at comstyle.com>
Date: 2025-07-18 (Fri, 18 Jul 2025)
Changed paths:
M libc/src/__support/macros/properties/architectures.h
M libcxx/include/__config
M libcxx/include/limits
M libcxx/src/random.cpp
M libcxx/test/std/language.support/support.limits/limits/numeric.limits.members/traps.pass.cpp
M llvm/tools/llvm-readobj/ELFDumper.cpp
Log Message:
-----------
Remove last few bits for Native Client support (#148983)
Commit: 32f0fc597f92f98f1be81abbd07f5164377668ef
https://github.com/llvm/llvm-project/commit/32f0fc597f92f98f1be81abbd07f5164377668ef
Author: David Spickett <david.spickett at linaro.org>
Date: 2025-07-18 (Fri, 18 Jul 2025)
Changed paths:
M lldb/source/DataFormatters/ValueObjectPrinter.cpp
M lldb/test/API/lang/cpp/frame-var-depth-and-elem-count/TestFrameVarDepthAndElemCount.py
Log Message:
-----------
[lldb] Correct spacing of = {...} when depth limit is hit (#149480)
In some places it was printing "= {...}" and some "={...}" with no
space. I think the space looks nicer so do that in both cases.
Commit: ac7ceb3dabfac548caa993e7b77bbadc78af4464
https://github.com/llvm/llvm-project/commit/ac7ceb3dabfac548caa993e7b77bbadc78af4464
Author: quic-areg <aregmi at quicinc.com>
Date: 2025-07-18 (Fri, 18 Jul 2025)
Changed paths:
M lld/test/ELF/hexagon-plt.s
M lld/test/ELF/hexagon-shared.s
M lld/test/ELF/hexagon-tls-gd-xform.s
M llvm/include/llvm/MC/MCDisassembler/MCDisassembler.h
M llvm/lib/Target/Hexagon/Disassembler/HexagonDisassembler.cpp
M llvm/lib/Target/Hexagon/MCTargetDesc/HexagonInstPrinter.cpp
M llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCTargetDesc.cpp
M llvm/test/MC/Hexagon/two_ext.s
A llvm/test/tools/llvm-objdump/ELF/Hexagon/hexagon-bundles.s
M llvm/tools/llvm-mc/Disassembler.cpp
M llvm/tools/llvm-objdump/llvm-objdump.cpp
Log Message:
-----------
[Hexagon][llvm-objdump] Improve disassembly of Hexagon bundles (#145807)
Hexagon instructions are VLIW "bundles" of up to four instruction words
encoded as a single MCInst with operands for each sub-instruction.
Previously, the disassembler's getInstruction() returned the full
bundle, which made it difficult to work with llvm-objdump.
For example, since all instructions are bundles, and bundles do not
branch, branch targets could not be printed.
This patch modifies the Hexagon disassembler to return individual
sub-instructions instead of entire bundles, enabling correct printing of
branch targets and relocations. It also introduces
`MCDisassembler::getInstructionBundle` for cases where the full bundle
is still needed.
By default, llvm-objdump separates instructions with newlines. However,
this does not work well for Hexagon syntax:
{ inst1
inst2
inst3
inst4 <branch> } :endloop0
Instructions may be followed by a closing brace, a closing brace with
`:endloop`, or a newline. Branches must appear within the braces.
To address this, `PrettyPrinter::getInstructionSeparator()` is added and
overridden for Hexagon.
Commit: a676ecd83fad9b04d315c4e667742d25679cbc9f
https://github.com/llvm/llvm-project/commit/a676ecd83fad9b04d315c4e667742d25679cbc9f
Author: lntue <lntue at google.com>
Date: 2025-07-18 (Fri, 18 Jul 2025)
Changed paths:
M libc/include/llvm-libc-macros/math-macros.h
M libc/test/include/CMakeLists.txt
A libc/test/include/math_constants_test.c
Log Message:
-----------
[libc][math] Add POSIX math constants to math.h header. (#149150)
https://pubs.opengroup.org/onlinepubs/9799919799/basedefs/math.h.html
Commit: d737fe2c91391a41a5b5ee8e3062d78a01936c61
https://github.com/llvm/llvm-project/commit/d737fe2c91391a41a5b5ee8e3062d78a01936c61
Author: Louis Dionne <ldionne.2 at gmail.com>
Date: 2025-07-18 (Fri, 18 Jul 2025)
Changed paths:
M libcxx/docs/ReleaseNotes/21.rst
Log Message:
-----------
[libc++][NFC] Fix typos in the libc++ 21 release notes (#149536)
Commit: 148fd6ed0a21aaa540ad443b8108456b191dd485
https://github.com/llvm/llvm-project/commit/148fd6ed0a21aaa540ad443b8108456b191dd485
Author: Annu Singh <annu4444.as at gmail.com>
Date: 2025-07-18 (Fri, 18 Jul 2025)
Changed paths:
M llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
M llvm/test/CodeGen/AArch64/freeze.ll
Log Message:
-----------
[DAG] Adding abdu/abds to canCreateUndefOrPoison (#149017)
Fixes #147695
- [Alive2 test - freeze abdu](https://alive2.llvm.org/ce/z/aafeJs)
- [Alive 2 test - freeze abds](https://alive2.llvm.org/ce/z/XrSmP4)
---------
Co-authored-by: Simon Pilgrim <llvm-dev at redking.me.uk>
Commit: c244c3b2d95a1605337b1156fad412ee2c9cd8c9
https://github.com/llvm/llvm-project/commit/c244c3b2d95a1605337b1156fad412ee2c9cd8c9
Author: Jonathan Peyton <jonathan.l.peyton at intel.com>
Date: 2025-07-18 (Fri, 18 Jul 2025)
Changed paths:
M openmp/runtime/src/kmp.h
M openmp/runtime/src/kmp_tasking.cpp
Log Message:
-----------
[OpenMP] [NFC] Remove dead code: building task stack (#143589)
This code hasn't been enabled since the first code changes were
introduced. Remove the dead code.
Commit: a9147e64aa751caaa106953fded2d0f7223bb167
https://github.com/llvm/llvm-project/commit/a9147e64aa751caaa106953fded2d0f7223bb167
Author: Peter Rong <peterrong96 at gmail.com>
Date: 2025-07-18 (Fri, 18 Jul 2025)
Changed paths:
M llvm/lib/DWARFLinker/Classic/DWARFLinker.cpp
Log Message:
-----------
Revert "[DWARFLinker] Use different addresses to distinguish invalid … (#149422)
…DW_AT_LLVM_stmt_sequence offset (#149376)"
This reverts commit b0c6148584854af3d7ed2425034c3b5252f6b769.
Commit: 92e2d4e9e1ad7a8d66d481b4df3f971450f829f5
https://github.com/llvm/llvm-project/commit/92e2d4e9e1ad7a8d66d481b4df3f971450f829f5
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2025-07-18 (Fri, 18 Jul 2025)
Changed paths:
M llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
Log Message:
-----------
[DAG] visitFREEZE - remove unused HadMaybePoisonOperands check. NFC. (#149517)
Redundant since #145939
Commit: 7d040d4675baf6881cf50c4dba78cc18af85f9ef
https://github.com/llvm/llvm-project/commit/7d040d4675baf6881cf50c4dba78cc18af85f9ef
Author: Han-Chung Wang <hanhan0912 at gmail.com>
Date: 2025-07-18 (Fri, 18 Jul 2025)
Changed paths:
M mlir/lib/Dialect/Linalg/Transforms/TilingInterfaceImpl.cpp
M mlir/test/Interfaces/TilingInterface/tile-and-fuse-consumer.mlir
Log Message:
-----------
[mlir][linalg] Handle outer_dims_perm in linalg.pack consumer fusion. (#149426)
Signed-off-by: hanhanW <hanhan0912 at gmail.com>
Commit: 0c75e093813c86a1c99b75d2a46f56db7ab516dd
https://github.com/llvm/llvm-project/commit/0c75e093813c86a1c99b75d2a46f56db7ab516dd
Author: Shaoce SUN <sunshaoce at outlook.com>
Date: 2025-07-19 (Sat, 19 Jul 2025)
Changed paths:
M llvm/utils/TableGen/Common/CodeGenSchedule.cpp
Log Message:
-----------
[TableGen] Add `getName()` to error messages for better debugging (#149531)
Including the name helps quickly locate the corresponding Instruction
that caused the issue.
Commit: 01213141357e4a79d2d97187ff0cb89d8d173634
https://github.com/llvm/llvm-project/commit/01213141357e4a79d2d97187ff0cb89d8d173634
Author: Nikita Popov <npopov at redhat.com>
Date: 2025-07-18 (Fri, 18 Jul 2025)
Changed paths:
M llvm/lib/Transforms/Utils/MemoryTaggingSupport.cpp
Log Message:
-----------
[MemoryTaggingSupport] Remove unnecessary bitcast (NFC)
As the comment indicates, this is no longer necessary with
opaque pointers.
Commit: 73e4b589ba9526c72f495ca6898ed18d730d2db4
https://github.com/llvm/llvm-project/commit/73e4b589ba9526c72f495ca6898ed18d730d2db4
Author: Fangrui Song <i at maskray.me>
Date: 2025-07-18 (Fri, 18 Jul 2025)
Changed paths:
M llvm/include/llvm/MC/MCObjectStreamer.h
M llvm/include/llvm/MC/MCSection.h
M llvm/include/llvm/MC/MCStreamer.h
M llvm/lib/MC/MCObjectStreamer.cpp
M llvm/lib/MC/MCParser/MCTargetAsmParser.cpp
M llvm/lib/MC/MCStreamer.cpp
M llvm/test/MC/RISCV/Relocations/mc-dump.s
Log Message:
-----------
MC: Simplify fragment reuse determination
First, avoid checking MCSubtargetInfo by reducing unnecessary overhead
introduced in https://reviews.llvm.org/D44928 . That change passed STI
to both FT_Data and FT_Relaxable fragments, but STI is only necessary
for FT_Relaxable.
The use of STI in FT_Data was added for:
* Bundle alignment mode, which has been removed (#148781).
* ARM, which inappropriately uses STI in `ARMAsmBackend::applyFixup` due
to tech debt, unlike other targets. All tests passed even without the
`copySTI` change.
To ensure safety, `copySTI` now starts a new fragment to prevent mixed
STI values.
Second, avoid checking LinkerRelaxable by eagerly starting a new
fragment when a FT_Data/FT_Align fragment is marked linker-relaxable.
There is currently an extra empty FT_Data if an alignment immediately
follows a linker-relaxable fragment, which will be improved in the
future when FT_Align information is moved to the variable-tail.
Pull Request: https://github.com/llvm/llvm-project/pull/149471
Commit: 5138b61a25f11eb8675d0031712c1ee6b4cb8be4
https://github.com/llvm/llvm-project/commit/5138b61a25f11eb8675d0031712c1ee6b4cb8be4
Author: Brox Chen <guochen2 at amd.com>
Date: 2025-07-18 (Fri, 18 Jul 2025)
Changed paths:
M llvm/lib/Target/AMDGPU/SIInstructions.td
M llvm/test/CodeGen/AMDGPU/add.v2i16.ll
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.1024bit.ll
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.128bit.ll
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.16bit.ll
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.256bit.ll
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.320bit.ll
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.32bit.ll
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.48bit.ll
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.512bit.ll
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.64bit.ll
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.96bit.ll
A llvm/test/CodeGen/AMDGPU/atomicrmw-bf16-gfx11plus.ll
M llvm/test/CodeGen/AMDGPU/bf16.ll
M llvm/test/CodeGen/AMDGPU/buffer-fat-pointer-atomicrmw-fadd.ll
M llvm/test/CodeGen/AMDGPU/buffer-fat-pointer-atomicrmw-fmax.ll
M llvm/test/CodeGen/AMDGPU/buffer-fat-pointer-atomicrmw-fmin.ll
M llvm/test/CodeGen/AMDGPU/calling-conventions.ll
M llvm/test/CodeGen/AMDGPU/cvt_f32_ubyte.ll
M llvm/test/CodeGen/AMDGPU/dagcombine-fmul-sel.ll
M llvm/test/CodeGen/AMDGPU/divergence-driven-buildvector.ll
M llvm/test/CodeGen/AMDGPU/fabs.bf16.ll
M llvm/test/CodeGen/AMDGPU/flat-atomicrmw-fadd.ll
M llvm/test/CodeGen/AMDGPU/flat-atomicrmw-fmax.ll
M llvm/test/CodeGen/AMDGPU/flat-atomicrmw-fmin.ll
M llvm/test/CodeGen/AMDGPU/flat-atomicrmw-fsub.ll
M llvm/test/CodeGen/AMDGPU/fmax3-maximumnum.ll
M llvm/test/CodeGen/AMDGPU/fmed3.bf16.ll
M llvm/test/CodeGen/AMDGPU/fmin3-minimumnum.ll
M llvm/test/CodeGen/AMDGPU/function-args.ll
M llvm/test/CodeGen/AMDGPU/gfx-callable-argument-types.ll
M llvm/test/CodeGen/AMDGPU/global-atomicrmw-fadd.ll
M llvm/test/CodeGen/AMDGPU/global-atomicrmw-fmax.ll
M llvm/test/CodeGen/AMDGPU/global-atomicrmw-fmin.ll
M llvm/test/CodeGen/AMDGPU/global-atomicrmw-fsub.ll
M llvm/test/CodeGen/AMDGPU/global-saddr-load.ll
M llvm/test/CodeGen/AMDGPU/idot4u.ll
M llvm/test/CodeGen/AMDGPU/isel-amdgpu-cs-chain-preserve-cc.ll
M llvm/test/CodeGen/AMDGPU/llvm.exp2.bf16.ll
M llvm/test/CodeGen/AMDGPU/llvm.log.ll
M llvm/test/CodeGen/AMDGPU/llvm.log10.ll
M llvm/test/CodeGen/AMDGPU/llvm.log2.ll
M llvm/test/CodeGen/AMDGPU/mad-mix-hi.ll
M llvm/test/CodeGen/AMDGPU/maximumnum.bf16.ll
M llvm/test/CodeGen/AMDGPU/minimumnum.bf16.ll
M llvm/test/CodeGen/AMDGPU/sub.v2i16.ll
M llvm/test/CodeGen/AMDGPU/vector-reduce-umax.ll
Log Message:
-----------
[AMDGPU][True16][Codegen] remove packed build_vector pattern from true16 (#148715)
Some of the packed build_vector use vgpr_32 for i16/f16/bf16.
In gfx11, bf16 arithmetic get promoted to f32 and this is done via v2i16
pack. In true16 mode this v2i16 pack is selected to a
build_vector/v_lshlrev pattern which only accepts VGPR32. This causes
isel to insert an illegal copy "vgpr32 = copy vgpr16" between def and
use. In the end this illegal copy confuses cse pass and trigger wrong
code elimination.
Remove the packed build_vector pattern from true16. After removal, ISel
will use vgpr16 build_vector patterns instead.
Commit: 2c2567da95c64ee1ed9104ee2539894242922b83
https://github.com/llvm/llvm-project/commit/2c2567da95c64ee1ed9104ee2539894242922b83
Author: Eugene Epshteyn <eepshteyn at nvidia.com>
Date: 2025-07-18 (Fri, 18 Jul 2025)
Changed paths:
M flang/lib/Semantics/check-do-forall.cpp
M flang/test/Semantics/resolve40.f90
Log Message:
-----------
[flang] Fixed a crash with undeclared variable in implicit-do loop (#149513)
Fixed a crash in the following example:
```
subroutine sub()
implicit none
print *, (i, i = 1, 2) ! Problem: using undefined var in implied-do loop
end subroutine sub
```
The error message was already generated, but the compiler crashed before
it could display it.
Commit: 10518c76de091bf23e72a8761c1eff561ce6e074
https://github.com/llvm/llvm-project/commit/10518c76de091bf23e72a8761c1eff561ce6e074
Author: Mohammadreza Ameri Mahabadian <mohammadreza.amerimahabadian at arm.com>
Date: 2025-07-18 (Fri, 18 Jul 2025)
Changed paths:
M mlir/include/mlir/Dialect/SPIRV/Transforms/Passes.td
M mlir/lib/Dialect/SPIRV/Transforms/CMakeLists.txt
A mlir/lib/Dialect/SPIRV/Transforms/ConvertToReplicatedConstantCompositePass.cpp
A mlir/test/Dialect/SPIRV/Transforms/replicated-const-composites.mlir
Log Message:
-----------
[mlir][spirv] Add conversion pass to rewrite splat constant composite… (#148910)
…s to replicated form
This adds a new SPIR-V dialect-level conversion pass
`ConversionToReplicatedConstantCompositePass`. This pass looks for splat
composite `spirv.Constant` or `spirv.SpecConstantComposite` and rewrites
them into `spirv.EXT.ConstantCompositeReplicate` or
`spirv.EXT.SpecConstantCompositeReplicate`, respectively.
---------
Signed-off-by: Mohammadreza Ameri Mahabadian <mohammadreza.amerimahabadian at arm.com>
Commit: 7e0ae019f854c99ae0d6a220aba7fcd5407f2494
https://github.com/llvm/llvm-project/commit/7e0ae019f854c99ae0d6a220aba7fcd5407f2494
Author: Muhammad Bassiouni <60100307+bassiounix at users.noreply.github.com>
Date: 2025-07-18 (Fri, 18 Jul 2025)
Changed paths:
M libc/shared/math.h
A libc/shared/math/exp10f16.h
M libc/src/__support/math/CMakeLists.txt
A libc/src/__support/math/exp10_float16_constants.h
A libc/src/__support/math/exp10f16.h
A libc/src/__support/math/exp10f16_utils.h
M libc/src/math/generic/CMakeLists.txt
M libc/src/math/generic/exp10f16.cpp
M libc/src/math/generic/exp10m1f16.cpp
M libc/src/math/generic/expxf16.h
M utils/bazel/llvm-project-overlay/libc/BUILD.bazel
Log Message:
-----------
[libc][math] Refactor exp10f16 implementation to header-only in src/__support/math folder. (#148408)
Part of #147386
in preparation for:
https://discourse.llvm.org/t/rfc-make-clang-builtin-math-functions-constexpr-with-llvm-libc-to-support-c-23-constexpr-math-functions/86450
Commit: e11d28faee10dfb5ae6b8aaadadfd2ea1a2a446a
https://github.com/llvm/llvm-project/commit/e11d28faee10dfb5ae6b8aaadadfd2ea1a2a446a
Author: Shilei Tian <i at tianshilei.me>
Date: 2025-07-18 (Fri, 18 Jul 2025)
Changed paths:
M clang/test/CodeGenOpenCL/builtins-amdgcn-gfx1250.cl
M llvm/lib/Target/AMDGPU/VOP1Instructions.td
M llvm/lib/Target/AMDGPU/VOPInstructions.td
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.permlane16.swap.ll
M llvm/test/MC/AMDGPU/gfx1250_asm_vop1-fake16.s
M llvm/test/MC/AMDGPU/gfx1250_asm_vop1.s
M llvm/test/MC/AMDGPU/gfx1250_asm_vop3_from_vop1-fake16.s
M llvm/test/MC/AMDGPU/gfx1250_asm_vop3_from_vop1.s
Log Message:
-----------
[AMDGPU] Add support for `v_permlane16_swap_b32` on gfx1250 (#149518)
Co-authored-by: Mekhanoshin, Stanislav <Stanislav.Mekhanoshin at amd.com>
Commit: 2c50e4cac2c50dbbc9eb3ed78bc0178bfa26d23f
https://github.com/llvm/llvm-project/commit/2c50e4cac2c50dbbc9eb3ed78bc0178bfa26d23f
Author: Shilei Tian <i at tianshilei.me>
Date: 2025-07-18 (Fri, 18 Jul 2025)
Changed paths:
M clang/include/clang/Basic/BuiltinsAMDGPU.def
M clang/test/CodeGenOpenCL/builtins-amdgcn-gfx1250.cl
M llvm/include/llvm/IR/IntrinsicsAMDGPU.td
M llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp
M llvm/lib/Target/AMDGPU/SIInstrInfo.td
M llvm/lib/Target/AMDGPU/VOP1Instructions.td
A llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.sat.pk.ll
M llvm/test/MC/AMDGPU/gfx1250_asm_vop1-fake16.s
M llvm/test/MC/AMDGPU/gfx1250_asm_vop1.s
M llvm/test/MC/AMDGPU/gfx1250_asm_vop1_dpp16-fake16.s
M llvm/test/MC/AMDGPU/gfx1250_asm_vop1_dpp16.s
M llvm/test/MC/AMDGPU/gfx1250_asm_vop1_dpp8-fake16.s
M llvm/test/MC/AMDGPU/gfx1250_asm_vop1_dpp8.s
M llvm/test/MC/AMDGPU/gfx1250_asm_vop3_from_vop1-fake16.s
M llvm/test/MC/AMDGPU/gfx1250_asm_vop3_from_vop1.s
M llvm/test/MC/AMDGPU/gfx1250_asm_vop3_from_vop1_dpp16-fake16.s
M llvm/test/MC/AMDGPU/gfx1250_asm_vop3_from_vop1_dpp16.s
M llvm/test/MC/AMDGPU/gfx1250_asm_vop3_from_vop1_dpp8-fake16.s
M llvm/test/MC/AMDGPU/gfx1250_asm_vop3_from_vop1_dpp8.s
M llvm/test/MC/Disassembler/AMDGPU/gfx1250_dasm_vop1.txt
M llvm/test/MC/Disassembler/AMDGPU/gfx1250_dasm_vop1_dpp16.txt
M llvm/test/MC/Disassembler/AMDGPU/gfx1250_dasm_vop1_dpp8.txt
M llvm/test/MC/Disassembler/AMDGPU/gfx1250_dasm_vop3_from_vop1.txt
M llvm/test/MC/Disassembler/AMDGPU/gfx1250_dasm_vop3_from_vop1_dpp16.txt
M llvm/test/MC/Disassembler/AMDGPU/gfx1250_dasm_vop3_from_vop1_dpp8.txt
Log Message:
-----------
[AMDGPU] Add support for `v_sat_pk4_i4_[i8,u8]` on gfx1250 (#149528)
Co-authored-by: Mekhanoshin, Stanislav <Stanislav.Mekhanoshin at amd.com>
Co-authored-by: Foad, Jay <Jay.Foad at amd.com>
Commit: ff225b5d88647448be8bbba54aaac3977a5485b5
https://github.com/llvm/llvm-project/commit/ff225b5d88647448be8bbba54aaac3977a5485b5
Author: Alexey Bataev <a.bataev at outlook.com>
Date: 2025-07-18 (Fri, 18 Jul 2025)
Changed paths:
M llvm/test/Transforms/SLPVectorizer/RISCV/reordered-buildvector-scalars.ll
Log Message:
-----------
[SLP][NFC]Add a run line for the test, NFC
Commit: 7fd91bb6e89be39a130e04058a01d41ae5d600cb
https://github.com/llvm/llvm-project/commit/7fd91bb6e89be39a130e04058a01d41ae5d600cb
Author: Jaden Angella <ajaden at google.com>
Date: 2025-07-18 (Fri, 18 Jul 2025)
Changed paths:
M mlir/lib/Conversion/MemRefToEmitC/MemRefToEmitC.cpp
M mlir/test/Conversion/MemRefToEmitC/memref-to-emitc.mlir
Log Message:
-----------
[mlir][EmitC]Expand the MemRefToEmitC pass - Adding scalars (#148055)
This aims to expand the the MemRefToEmitC pass so that it can accept
global scalars.
From:
```
memref.global "private" constant @__constant_xi32 : memref<i32> = dense<-1>
func.func @globals() {
memref.get_global @__constant_xi32 : memref<i32>
}
```
To:
```
emitc.global static const @__constant_xi32 : i32 = -1
emitc.func @globals() {
%0 = get_global @__constant_xi32 : !emitc.lvalue<i32>
%1 = apply "&"(%0) : (!emitc.lvalue<i32>) -> !emitc.ptr<i32>
return
}
```
Commit: 87c2adbb589d4cd0b6dfb374fce24d29c6bafac0
https://github.com/llvm/llvm-project/commit/87c2adbb589d4cd0b6dfb374fce24d29c6bafac0
Author: Philip Reames <preames at rivosinc.com>
Date: 2025-07-18 (Fri, 18 Jul 2025)
Changed paths:
M llvm/test/CodeGen/RISCV/rvv/vector-deinterleave-load.ll
Log Message:
-----------
[RISCV][IA] Precommit tests for deinterleaveN of masked.load
Commit: 3ea6da59ecda0708d85f78f1feb4090a8551ce90
https://github.com/llvm/llvm-project/commit/3ea6da59ecda0708d85f78f1feb4090a8551ce90
Author: Han-Chung Wang <hanhan0912 at gmail.com>
Date: 2025-07-18 (Fri, 18 Jul 2025)
Changed paths:
M mlir/lib/Dialect/Linalg/Transforms/TilingInterfaceImpl.cpp
M mlir/test/Interfaces/TilingInterface/tile-and-fuse-consumer.mlir
Log Message:
-----------
[mlir][linalg] Allow pack consumer fusion if the tile size is greater than dimension size. (#149438)
This happens only when you use larger tile size, which is greater than
or equal to the dimension size. In this case, it is a full slice, so it
is fusible.
The IR can be generated during the TileAndFuse process. It is hard to
fix in such driver, so we enable the naive fusion for the case.
---------
Signed-off-by: hanhanW <hanhan0912 at gmail.com>
Commit: 796d5a89a12407fb0fdf74ea063259b6ca7333d9
https://github.com/llvm/llvm-project/commit/796d5a89a12407fb0fdf74ea063259b6ca7333d9
Author: Kazu Hirata <kazu at google.com>
Date: 2025-07-18 (Fri, 18 Jul 2025)
Changed paths:
M llvm/include/llvm/ADT/CombinationGenerator.h
Log Message:
-----------
[ADT] Use a range-based for loop instead of llvm::for_each (NFC) (#149542)
LLVM Coding Standards discourages llvm::for_each unless we already
have a callable.
Commit: b5e71d727b6624c160c9186b52d73bdb635770ed
https://github.com/llvm/llvm-project/commit/b5e71d727b6624c160c9186b52d73bdb635770ed
Author: Peter Collingbourne <peter at pcc.me.uk>
Date: 2025-07-18 (Fri, 18 Jul 2025)
Changed paths:
M llvm/docs/Extensions.rst
M llvm/include/llvm/BinaryFormat/ELF.h
M llvm/lib/MC/MCParser/ELFAsmParser.cpp
M llvm/lib/MC/MCSectionELF.cpp
M llvm/lib/Object/ELF.cpp
M llvm/test/MC/AsmParser/llvm_section_types.s
Log Message:
-----------
Add section type to support CFI jump table relaxation.
For context see main pull request: #147424.
Reviewers: MaskRay
Reviewed By: MaskRay
Pull Request: https://github.com/llvm/llvm-project/pull/149259
Commit: f6641e2f233b809958e4f558f5ad2514bc812cb8
https://github.com/llvm/llvm-project/commit/f6641e2f233b809958e4f558f5ad2514bc812cb8
Author: Philip Reames <preames at rivosinc.com>
Date: 2025-07-18 (Fri, 18 Jul 2025)
Changed paths:
M llvm/lib/Target/RISCV/RISCVInterleavedAccess.cpp
Log Message:
-----------
[RISCV][IA] Factor out code for extracting operands from mem insts [nfc] (#149344)
We're going to end up repeating the operand extraction four times once
all of the routines have been updated to support both plain load/store
and vp.load/vp.store. I plan to add masked.load/masked.store in the near
future, and we'd need to add that to each of the four cases. Instead,
factor out a single copy of the operand normalization.
Commit: 4bf4e87576688c942b7b337f24fb098247dc4642
https://github.com/llvm/llvm-project/commit/4bf4e87576688c942b7b337f24fb098247dc4642
Author: Daniel Chen <cdchen at ca.ibm.com>
Date: 2025-07-18 (Fri, 18 Jul 2025)
Changed paths:
M flang-rt/lib/runtime/descriptor.cpp
Log Message:
-----------
Static_cast std::size_t to build flang_rt in 32-bit. (#149529)
Commit: 10b0dee97dd7e5a122116f7ccb26a19b081db9fd
https://github.com/llvm/llvm-project/commit/10b0dee97dd7e5a122116f7ccb26a19b081db9fd
Author: Tobias Decking <Tobias.Decking at gmail.com>
Date: 2025-07-18 (Fri, 18 Jul 2025)
Changed paths:
M llvm/lib/Target/X86/X86ISelLowering.cpp
M llvm/test/CodeGen/X86/vector-bitreverse.ll
Log Message:
-----------
[X86] Ensure that bit reversals of byte vectors are properly lowered on pure GFNI targets (#148304)
Fixes #148238.
When GFNI is present, custom bit reversal lowerings for scalar integers
become active. They work by swapping the bytes in the scalar value and
then reversing bits in a vector of bytes. However, the custom bit
reversal lowering for a vector of bytes is disabled if GFNI is present
in isolation, resulting messed up code.
---------
Co-authored-by: Simon Pilgrim <llvm-dev at redking.me.uk>
Commit: 6acc6991f83409be3ca6315edf8c7f381ebe4d40
https://github.com/llvm/llvm-project/commit/6acc6991f83409be3ca6315edf8c7f381ebe4d40
Author: Krzysztof Parzyszek <Krzysztof.Parzyszek at amd.com>
Date: 2025-07-18 (Fri, 18 Jul 2025)
Changed paths:
M llvm/include/llvm/ADT/STLForwardCompat.h
M llvm/unittests/ADT/STLForwardCompatTest.cpp
Log Message:
-----------
[STLForwardCompat] Improve category handling in transformOptional (#149539)
The old version would prefer the "const &" overload over the "&&" one
unless the former was not allowed in the given situation. In particular,
if the function passed was "[](auto &&)" the argument would be "const &"
even if the value passed to transformOptional was an rvalue reference.
This version improves the handling of expression categories, and the
lambda argument category will reflect the argument category in the above
scenario.
Commit: 13f7786f72d13a84dfc3d49d87a70e6a05f21fd4
https://github.com/llvm/llvm-project/commit/13f7786f72d13a84dfc3d49d87a70e6a05f21fd4
Author: Roland McGrath <mcgrathr at google.com>
Date: 2025-07-18 (Fri, 18 Jul 2025)
Changed paths:
R libc/include/dirent.h.def
M libc/include/dirent.yaml
R libc/include/search.h.def
M libc/include/search.yaml
R libc/include/setjmp.h.def
M libc/include/setjmp.yaml
R libc/include/spawn.h.def
M libc/include/spawn.yaml
R libc/include/string.h.def
M libc/include/string.yaml
R libc/include/strings.h.def
M libc/include/strings.yaml
R libc/include/sys/sendfile.h.def
M libc/include/sys/sendfile.yaml
R libc/include/sys/statvfs.h.def
M libc/include/sys/statvfs.yaml
M libc/include/sys/types.yaml
R libc/include/sys/uio.h.def
M libc/include/sys/uio.yaml
R libc/include/sys/utsname.h.def
M libc/include/sys/utsname.yaml
R libc/include/threads.h.def
M libc/include/threads.yaml
R libc/include/uchar.h.def
M libc/include/uchar.yaml
Log Message:
-----------
[libc] Remove trivial .h.def files (#149466)
Remove all the .h.def files that already express nothing
whatsoever not already expressed in YAML. Clean up a few YAML
files without materially changing any generated header output.
Many more .h.def files remain that need a bit of conversion in
YAML to express macro requirements and such.
Commit: cfa918bec18c012a89a36b5a7ddceacb8e6c9ed7
https://github.com/llvm/llvm-project/commit/cfa918bec18c012a89a36b5a7ddceacb8e6c9ed7
Author: Stanislav Mekhanoshin <Stanislav.Mekhanoshin at amd.com>
Date: 2025-07-18 (Fri, 18 Jul 2025)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPUGISel.td
M llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp
M llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.h
M llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
M llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.h
M llvm/lib/Target/AMDGPU/FLATInstructions.td
A llvm/test/CodeGen/AMDGPU/flat-saddr-atomics.ll
Log Message:
-----------
[AMDGPU] Select flat GVS atomics on gfx1250 (#149554)
Commit: de59e7b86cd349f9f74b7561594aeae410477326
https://github.com/llvm/llvm-project/commit/de59e7b86cd349f9f74b7561594aeae410477326
Author: Joseph Huber <huberjn at outlook.com>
Date: 2025-07-18 (Fri, 18 Jul 2025)
Changed paths:
M libc/benchmarks/gpu/LibcGpuBenchmark.cpp
M libc/benchmarks/gpu/src/math/atan2_benchmark.cpp
A libc/benchmarks/gpu/src/math/platform.h
M libc/benchmarks/gpu/src/math/sin_benchmark.cpp
M libc/benchmarks/gpu/timing/amdgpu/timing.h
M libc/benchmarks/gpu/timing/nvptx/timing.h
Log Message:
-----------
[libc] Fix GPU benchmarking
Commit: 6a7f572ef9758f49fcf9e178ce1cb95aa3069415
https://github.com/llvm/llvm-project/commit/6a7f572ef9758f49fcf9e178ce1cb95aa3069415
Author: Jacob Lalonde <jalalonde at fb.com>
Date: 2025-07-18 (Fri, 18 Jul 2025)
Changed paths:
M lldb/bindings/interface/SBSaveCoreOptionsDocstrings.i
M lldb/include/lldb/API/SBMemoryRegionInfoList.h
M lldb/include/lldb/API/SBSaveCoreOptions.h
M lldb/include/lldb/Core/PluginManager.h
M lldb/include/lldb/Symbol/SaveCoreOptions.h
M lldb/source/API/SBProcess.cpp
M lldb/source/API/SBSaveCoreOptions.cpp
M lldb/source/Commands/CommandObjectProcess.cpp
M lldb/source/Core/PluginManager.cpp
M lldb/source/Plugins/ObjectFile/Minidump/MinidumpFileBuilder.cpp
M lldb/source/Symbol/SaveCoreOptions.cpp
A lldb/test/API/functionalities/process_save_core_minidump/TestProcessSaveCoreMinidump64b.py
M lldb/test/API/python_api/sbsavecoreoptions/TestSBSaveCoreOptions.py
Log Message:
-----------
[LLDB] Fix Memory64 BaseRVA, move all non-stack memory to Mem64. (#146777)
### Context
Over a year ago, I landed support for 64b Memory ranges in Minidump
(#95312). In this patch we added the Memory64 list stream, which is
effectively a Linked List on disk. The layout is a sixteen byte header
and then however many Memory descriptors.
### The Bug
This is a classic off-by one error, where I added 8 bytes instead of 16
for the header. This caused the first region to start 8 bytes before the
correct RVA, thus shifting all memory reads by 8 bytes. We are correctly
writing all the regions to disk correctly, with no physical corruption
but the RVA is defined wrong, meaning we were incorrectly reading memory
### Why wasn't this caught?
One problem we've had is forcing Minidump to actually use the 64b mode,
it would be a massive waste of resources to have a test that actually
wrote >4.2gb of IO to validate the 64b regions, and so almost all
validation has been manual. As a weakness of manual testing, this issue
is psuedo non-deterministic, as what regions end up in 64b or 32b is
handled greedily and iterated in the order it's laid out in
/proc/pid/maps. We often validated 64b was written correctly by
hexdumping the Minidump itself, which was not corrupted (other than the
BaseRVA)
### Why is this showing up now?
During internal usage, we had a bug report that the Minidump wasn't
displaying values. I was unable to repro the issue, but during my
investigation I saw the variables were in the 64b regions which resulted
in me identifying the bug.
### How do we prevent future regressions?
To prevent regressions, and honestly to save my sanity for figuring out
where 8 bytes magically came from, I've added a new API to
SBSaveCoreOptions.
```SBSaveCoreOptions::GetMemoryRegionsToSave()```
The ability to get the memory regions that we intend to include in the Coredump. I added this so we can compare what we intended to include versus what was actually included. Traditionally we've always had issues comparing regions because Minidump includes `/proc/pid/maps` and it can be difficult to know what memoryregion read failure was a genuine error or just a page that wasn't meant to be included.
We are also leveraging this API to choose the memory regions to be generated, as well as for testing what regions should be bytewise 1:1.
After much debate with @clayborg, I've moved all non-stack memory to the Memory64 List. This list doesn't incur us any meaningful overhead and Greg originally suggested doing this in the original 64b PR. This also means we're exercising the 64b path every single time we save a Minidump, preventing regressions on this feature from slipping through testing in the future.
Snippet produced by [minidump.py](https://github.com/clayborg/scripts)
```
MINIDUMP_MEMORY_LIST:
NumberOfMemoryRanges = 0x00000002
MemoryRanges[0] = [0x00007f61085ff9f0 - 0x00007f6108601000) @ 0x0003f655
MemoryRanges[1] = [0x00007ffe47e50910 - 0x00007ffe47e52000) @ 0x00040c65
MINIDUMP_MEMORY64_LIST:
NumberOfMemoryRanges = 0x000000000000002e
BaseRva = 0x0000000000042669
MemoryRanges[0] = [0x00005584162d8000 - 0x00005584162d9000)
MemoryRanges[1] = [0x00005584162d9000 - 0x00005584162db000)
MemoryRanges[2] = [0x00005584162db000 - 0x00005584162dd000)
MemoryRanges[3] = [0x00005584162dd000 - 0x00005584162ff000)
MemoryRanges[4] = [0x00007f6100000000 - 0x00007f6100021000)
MemoryRanges[5] = [0x00007f6108800000 - 0x00007f6108828000)
MemoryRanges[6] = [0x00007f6108828000 - 0x00007f610899d000)
MemoryRanges[7] = [0x00007f610899d000 - 0x00007f61089f9000)
MemoryRanges[8] = [0x00007f61089f9000 - 0x00007f6108a08000)
MemoryRanges[9] = [0x00007f6108bf5000 - 0x00007f6108bf7000)
```
### Misc
As a part of this fix I had to look at LLDB logs a lot, you'll notice I added `0x` to many of the PRIx64 `LLDB_LOGF`. This is so the user (or I) can directly copy paste the address in the logs instead of adding the hex prefix themselves.
Added some SBSaveCore tests for the new GetMemoryAPI, and Docstrings.
CC: @DavidSpickett, @da-viper @labath because we've been working together on save-core plugins, review it optional and I didn't tag you but figured you'd want to know
Commit: 4dc6dfd65397e65f62a453b65cd180639c3a8b9e
https://github.com/llvm/llvm-project/commit/4dc6dfd65397e65f62a453b65cd180639c3a8b9e
Author: Ellis Hoag <ellis.sparky.hoag at gmail.com>
Date: 2025-07-18 (Fri, 18 Jul 2025)
Changed paths:
M llvm/tools/llvm-profdata/llvm-profdata.cpp
Log Message:
-----------
[NFC][profdata] Apply lints and other format fixes (#149433)
Apply lints and other format fixes to
`llvm/tools/llvm-profdata/llvm-profdata.cpp`. This is intended to have
no functional change.
Commit: b846d8c3e26ef98c8d6936e7cad354f035d322d1
https://github.com/llvm/llvm-project/commit/b846d8c3e26ef98c8d6936e7cad354f035d322d1
Author: Hanumanth <hhanuman at mathworks.com>
Date: 2025-07-18 (Fri, 18 Jul 2025)
Changed paths:
M mlir/lib/Dialect/Tosa/Transforms/TosaReduceTransposes.cpp
Log Message:
-----------
[mlir][tosa] Fix tosa-reduce-transposes to handle large constants better (#148755)
This change addresses the performance issue in the **--tosa-reduce-transposes** implementation by working directly with the
raw tensor data, eliminating the need for creating the costly intermediate attributes that leads to bottleneck.
Commit: d64802d6d96ec5aff3739ce34f8143b935921809
https://github.com/llvm/llvm-project/commit/d64802d6d96ec5aff3739ce34f8143b935921809
Author: Chelsea Cassanova <chelsea_cassanova at apple.com>
Date: 2025-07-18 (Fri, 18 Jul 2025)
Changed paths:
M lldb/cmake/modules/LLDBFramework.cmake
M lldb/scripts/framework-header-fix.py
M lldb/scripts/version-header-fix.py
M lldb/source/API/CMakeLists.txt
M lldb/test/Shell/Scripts/TestFrameworkFixScript.test
M lldb/test/Shell/Scripts/TestRPCFrameworkFixScript.test
Log Message:
-----------
[lldb][framework] Glob headers from source for framework (#148736)
When gathering the headers to fix up and place in LLDB.framework, we
were previously globbing the header files from a location in the build
directory. This commit changes this to glob from the source directory
instead, as we were globbing from the build directory without ensuring
that the necessary files were actually in that location before globbing.
Commit: 9d9662e4bdffc109cc5a7d0fa7c522d27babfa31
https://github.com/llvm/llvm-project/commit/9d9662e4bdffc109cc5a7d0fa7c522d27babfa31
Author: Alex MacLean <amaclean at nvidia.com>
Date: 2025-07-18 (Fri, 18 Jul 2025)
Changed paths:
M llvm/test/CodeGen/NVPTX/trunc-tofp.ll
Log Message:
-----------
[NVPTX][test] fixup version for ptxas on trunc-tofp.ll (#149558)
Commit: 3c1a09d939f44cbe039ea178af5a77c40b2776a0
https://github.com/llvm/llvm-project/commit/3c1a09d939f44cbe039ea178af5a77c40b2776a0
Author: Kazu Hirata <kazu at google.com>
Date: 2025-07-18 (Fri, 18 Jul 2025)
Changed paths:
M lldb/source/Plugins/SymbolLocator/Debuginfod/SymbolLocatorDebuginfod.cpp
Log Message:
-----------
[lldb] Use a range-based for loop instead of llvm::for_each (NFC) (#149541)
LLVM Coding Standards discourages llvm::for_each unless we already
have a callable.
Commit: 36c78ec3c8641cb193ea66f49da01fa6f62280d7
https://github.com/llvm/llvm-project/commit/36c78ec3c8641cb193ea66f49da01fa6f62280d7
Author: Kazu Hirata <kazu at google.com>
Date: 2025-07-18 (Fri, 18 Jul 2025)
Changed paths:
M llvm/lib/DebugInfo/LogicalView/Core/LVScope.cpp
Log Message:
-----------
[DebugInfo] Use llvm::remove_if (NFC) (#149543)
We can pass a range to llvm::remove_if.
Commit: c98b05bd567c16d575bc241cd0602cdf6558d8db
https://github.com/llvm/llvm-project/commit/c98b05bd567c16d575bc241cd0602cdf6558d8db
Author: Kazu Hirata <kazu at google.com>
Date: 2025-07-18 (Fri, 18 Jul 2025)
Changed paths:
M mlir/include/mlir/IR/OperationSupport.h
M mlir/lib/AsmParser/Parser.cpp
M mlir/unittests/Debug/FileLineColLocBreakpointManagerTest.cpp
M mlir/unittests/IR/OperationSupportTest.cpp
M mlir/unittests/IR/ValueTest.cpp
M mlir/unittests/Transforms/DialectConversion.cpp
Log Message:
-----------
[mlir] Deprecate NamedAttrList(std::nullopt_t) (NFC) (#149544)
This patch deprecates NamedAttrList(std::nullopt_t) to avoid use of
std::nullopt outside the context of std::optional.
Commit: cb6370167fd26d61397c1a2555d4c8a5f116d1f6
https://github.com/llvm/llvm-project/commit/cb6370167fd26d61397c1a2555d4c8a5f116d1f6
Author: Kazu Hirata <kazu at google.com>
Date: 2025-07-18 (Fri, 18 Jul 2025)
Changed paths:
M mlir/include/mlir/IR/OpDefinition.h
M mlir/include/mlir/IR/Operation.h
M mlir/include/mlir/IR/OperationSupport.h
Log Message:
-----------
[mlir] Deprecate OpPrintingFlags(std::nullopt_t) (NFC) (#149546)
This patch deprecates OpPrintingFlags(std::nullopt_t) to avoid use of
std::nullopt outside the context of std::optional.
Commit: c5f0c4ad378803f449f37730601b7d95059600a4
https://github.com/llvm/llvm-project/commit/c5f0c4ad378803f449f37730601b7d95059600a4
Author: Philip Reames <preames at rivosinc.com>
Date: 2025-07-18 (Fri, 18 Jul 2025)
Changed paths:
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-interleaved-access.ll
Log Message:
-----------
[RISCV][IA] Add test coverage for vp.store of interleaveN with one active
Commit: 9878ef3abd2a48fcfb81357d581dac292b52ddb3
https://github.com/llvm/llvm-project/commit/9878ef3abd2a48fcfb81357d581dac292b52ddb3
Author: Peter Collingbourne <peter at pcc.me.uk>
Date: 2025-07-18 (Fri, 18 Jul 2025)
Changed paths:
M llvm/lib/CodeGen/MachineFunction.cpp
A llvm/test/CodeGen/X86/function-align.ll
Log Message:
-----------
CodeGen: Respect function align attribute if less than preferred alignment.
Reviewers: arsenm, efriedma-quic
Reviewed By: arsenm
Pull Request: https://github.com/llvm/llvm-project/pull/149444
Commit: 97a8476068bad449c0340021398b0356a44857aa
https://github.com/llvm/llvm-project/commit/97a8476068bad449c0340021398b0356a44857aa
Author: Peter Klausler <pklausler at nvidia.com>
Date: 2025-07-18 (Fri, 18 Jul 2025)
Changed paths:
M flang-rt/lib/runtime/assign.cpp
Log Message:
-----------
[flang][runtime] Further work on speeding up work queue operations (#149189)
This patch avoids a trip through the work queue engine for cases on a
CPU where finalization and destruction actions during assignment were
handled without enqueueing another task.
Commit: 680b8dd7073cce6606006ae723899444521aa496
https://github.com/llvm/llvm-project/commit/680b8dd7073cce6606006ae723899444521aa496
Author: Peter Klausler <pklausler at nvidia.com>
Date: 2025-07-18 (Fri, 18 Jul 2025)
Changed paths:
M flang-rt/lib/runtime/edit-input.cpp
M flang-rt/unittests/Runtime/NumericalFormatTest.cpp
Log Message:
-----------
[flang][runtime] Handle spaces before ')' in alternative list-directe… (#149384)
…d complex input
List-directed reads of complex values that can't go through the usual
fast path (as in this bug's test case, which uses DECIMAL='COMMA')
didn't skip spaces before the closing right parenthesis correctly.
Fixes https://github.com/llvm/llvm-project/issues/149164.
Commit: 9e5b2fbe86ed9b303eff779fff012d6a96574f3d
https://github.com/llvm/llvm-project/commit/9e5b2fbe86ed9b303eff779fff012d6a96574f3d
Author: Peter Klausler <pklausler at nvidia.com>
Date: 2025-07-18 (Fri, 18 Jul 2025)
Changed paths:
M flang-rt/include/flang-rt/runtime/descriptor.h
M flang-rt/lib/runtime/descriptor.cpp
M flang-rt/lib/runtime/pointer.cpp
M flang/include/flang/Lower/Runtime.h
M flang/include/flang/Optimizer/Builder/Runtime/Intrinsics.h
M flang/include/flang/Runtime/pointer.h
M flang/lib/Lower/Bridge.cpp
M flang/lib/Lower/Runtime.cpp
M flang/test/Lower/polymorphic.f90
Log Message:
-----------
[flang][runtime] Preserve type when remapping monomorphic pointers (#149427)
Pointer remappings unconditionally update the element byte size and
derived type of the pointer's descriptor. This is okay when the pointer
is polymorphic, but not when a pointer is associated with an extended
type.
To communicate this monomorphic case to the runtime, add a new entry
point so as to not break forward binary compatibility.
Commit: b6ea04a37b2a41e24bb999e5a9b6a7bd2b576085
https://github.com/llvm/llvm-project/commit/b6ea04a37b2a41e24bb999e5a9b6a7bd2b576085
Author: Peter Klausler <pklausler at nvidia.com>
Date: 2025-07-18 (Fri, 18 Jul 2025)
Changed paths:
M flang/lib/Semantics/resolve-labels.cpp
Log Message:
-----------
[flang][NFC] Fix build-time warning (#149549)
Don't increment the LHS variable of an assignment that also uses that
variable on the RHS.
Commit: abdd4536ce0fc75c7a4ddcc1da5913ec5e028091
https://github.com/llvm/llvm-project/commit/abdd4536ce0fc75c7a4ddcc1da5913ec5e028091
Author: Andre Kuhlenschmidt <andre.kuhlenschmidt at gmail.com>
Date: 2025-07-18 (Fri, 18 Jul 2025)
Changed paths:
M flang/lib/Semantics/resolve-directives.cpp
M flang/test/Lower/OpenACC/acc-loop.f90
M flang/test/Semantics/OpenACC/acc-kernels-loop.f90
Log Message:
-----------
[flang][openacc] fix bugs with default(none) checking (#149220)
A report of the following code not generating an error led to fixing two bugs in directive checking.
- We should treat CombinedConstructs as OpenACC Constructs
- We should treat DoConstruct index variables as private.
```fortran
subroutine sub(nn)
integer :: nn, ii
!$acc serial loop default(none)
do ii = 1, nn
end do
!$acc end serial loop
end subroutine
```
Here `nn` should be flagged as needing a data clause while `ii` should
still get one implicitly.
Commit: 695660cdfd1ca65cd6e02e6950d10c990dfa0036
https://github.com/llvm/llvm-project/commit/695660cdfd1ca65cd6e02e6950d10c990dfa0036
Author: Jeffrey Byrnes <jeffrey.byrnes at amd.com>
Date: 2025-07-18 (Fri, 18 Jul 2025)
Changed paths:
M llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.cpp
A llvm/test/CodeGen/AMDGPU/llvm.amdgcn.mfma.form.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.mfma.gfx950.ll
Log Message:
-----------
[AMDGPU] Provide control to force VGPR MFMA form (#148079)
This gives an override to the user to force select VGPR form of MFMA.
Eventually we will drop this in favor of compiler making better
decisions, but this provides a mechanism for users to address the cases
where MayNeedAGPRs favors the AGPR form and performance is degraded due
to poor RA.
Commit: 004c67ea257039e4e98abc26dd4ac6e8f3d7a171
https://github.com/llvm/llvm-project/commit/004c67ea257039e4e98abc26dd4ac6e8f3d7a171
Author: Florian Hahn <flo at fhahn.com>
Date: 2025-07-18 (Fri, 18 Jul 2025)
Changed paths:
M llvm/include/llvm/Analysis/IVDescriptors.h
M llvm/lib/Analysis/IVDescriptors.cpp
M llvm/lib/Transforms/Utils/LoopUtils.cpp
M llvm/lib/Transforms/Vectorize/LoopVectorizationPlanner.h
M llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
M llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
M llvm/lib/Transforms/Vectorize/VPlanAnalysis.cpp
M llvm/lib/Transforms/Vectorize/VPlanConstruction.cpp
M llvm/lib/Transforms/Vectorize/VPlanRecipes.cpp
M llvm/lib/Transforms/Vectorize/VPlanTransforms.h
M llvm/test/Transforms/LoopVectorize/AArch64/fmax-without-fast-math-flags.ll
M llvm/test/Transforms/LoopVectorize/AArch64/fmin-without-fast-math-flags.ll
M llvm/test/Transforms/LoopVectorize/fmax-without-fast-math-flags-interleave.ll
M llvm/test/Transforms/LoopVectorize/fmax-without-fast-math-flags.ll
M llvm/test/Transforms/LoopVectorize/fmin-without-fast-math-flags.ll
M llvm/test/Transforms/LoopVectorize/minmax_reduction.ll
Log Message:
-----------
[LV] Vectorize maxnum/minnum w/o fast-math flags. (#148239)
Update LV to vectorize maxnum/minnum reductions without fast-math flags,
by adding an extra check in the loop if any inputs to maxnum/minnum are
NaN, due to maxnum/minnum behavior w.r.t to signaling NaNs. Signed-zeros
are already handled consistently by maxnum/minnum.
If any input is NaN,
*exit the vector loop,
*compute the reduction result up to the vector iteration that contained
NaN inputs and
* resume in the scalar loop
New recurrence kinds are added for reductions using maxnum/minnum
without fast-math flags.
PR: https://github.com/llvm/llvm-project/pull/148239
Commit: fb5c94e712e683e8b7c3cd04b3e47584c226d751
https://github.com/llvm/llvm-project/commit/fb5c94e712e683e8b7c3cd04b3e47584c226d751
Author: Ellis Hoag <ellis.sparky.hoag at gmail.com>
Date: 2025-07-18 (Fri, 18 Jul 2025)
Changed paths:
M llvm/test/tools/llvm-profdata/c-general.test
A llvm/test/tools/llvm-profdata/show-hot.proftext
M llvm/tools/llvm-profdata/llvm-profdata.cpp
Log Message:
-----------
[profdata] Use --hot-func-list to show all hot functions (#149428)
The `--hot-func-list` flag is used for sample profiles to dump the list
of hot functions. Add support to dump hot functions for IRPGO profiles
as well.
This also removes a `priority_queue` used for `--topn`. We can instead
store all functions and sort at the end before dumping. Since we are
storing `StringRef`s, I believe this won't consume too much memory.
Commit: ffb453989b0e95d85b6cfa543b65fec23b65649d
https://github.com/llvm/llvm-project/commit/ffb453989b0e95d85b6cfa543b65fec23b65649d
Author: Shilei Tian <i at tianshilei.me>
Date: 2025-07-18 (Fri, 18 Jul 2025)
Changed paths:
M llvm/test/MC/AMDGPU/gfx1250_asm_vop1.s
M llvm/test/MC/AMDGPU/gfx1250_asm_vop3_from_vop1-fake16.s
M llvm/test/MC/AMDGPU/gfx1250_asm_vop3_from_vop1.s
M llvm/test/MC/AMDGPU/gfx1250_asm_vop3_from_vop1_dpp8-fake16.s
M llvm/test/MC/AMDGPU/gfx1250_asm_vop3_from_vop1_dpp8.s
M llvm/test/MC/Disassembler/AMDGPU/gfx1250_dasm_vop1.txt
M llvm/test/MC/Disassembler/AMDGPU/gfx1250_dasm_vop3_from_vop1.txt
M llvm/test/MC/Disassembler/AMDGPU/gfx1250_dasm_vop3_from_vop1_dpp16.txt
M llvm/test/MC/Disassembler/AMDGPU/gfx1250_dasm_vop3_from_vop1_dpp8.txt
Log Message:
-----------
[NFC][AMDGPU] Align all gfx1250 VOP1 MC tests with downstream (#149567)
This PR adds all VOP1 tests that haven't yet been upstreamed by copying
the relevant test files directly from downstream. Afterward, the
auto-generation script is run with the `--unique` option to deduplicate
any redundant tests that may have been introduced during the downstream
merge.
Co-authored-by: Mekhanoshin, Stanislav <Stanislav.Mekhanoshin at amd.com>
Co-authored-by: Mekhanoshin, Stanislav <Stanislav.Mekhanoshin at amd.com>
Commit: d46de86ca4060fe2c631c08728af7c48ce9458fd
https://github.com/llvm/llvm-project/commit/d46de86ca4060fe2c631c08728af7c48ce9458fd
Author: Shilei Tian <i at tianshilei.me>
Date: 2025-07-18 (Fri, 18 Jul 2025)
Changed paths:
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.rcp.bf16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.rsq.bf16.ll
M llvm/test/CodeGen/AMDGPU/llvm.sqrt.bf16.ll
Log Message:
-----------
[NFC][AMDGPU] Re-enable two tests previously disabled due to missing upstream features (#149568)
This PR re-enables two tests that were previously disabled because they
depended on features not yet upstreamed.
Commit: 3be44e25804e776d3ff071740a60ae6d2f3ef4a7
https://github.com/llvm/llvm-project/commit/3be44e25804e776d3ff071740a60ae6d2f3ef4a7
Author: Jay Foad <jay.foad at amd.com>
Date: 2025-07-18 (Fri, 18 Jul 2025)
Changed paths:
M llvm/utils/TableGen/Common/CodeGenRegisters.cpp
M llvm/utils/TableGen/Common/CodeGenRegisters.h
Log Message:
-----------
[TableGen] Add some -time-phases support in CodeGenRegisters (#149309)
Commit: d63ab5467dcae0492e2f4def336ddbb73ce10dc5
https://github.com/llvm/llvm-project/commit/d63ab5467dcae0492e2f4def336ddbb73ce10dc5
Author: Princeton Ferro <pferro at nvidia.com>
Date: 2025-07-18 (Fri, 18 Jul 2025)
Changed paths:
M llvm/lib/Target/NVPTX/NVPTXISelLowering.cpp
M llvm/test/CodeGen/NVPTX/f16x2-instructions.ll
M llvm/test/CodeGen/NVPTX/f32x2-instructions.ll
M llvm/test/CodeGen/NVPTX/i16x2-instructions.ll
M llvm/test/CodeGen/NVPTX/i8x4-instructions.ll
A llvm/test/CodeGen/NVPTX/pr126337.ll
M llvm/test/CodeGen/NVPTX/reduction-intrinsics.ll
Log Message:
-----------
[NVPTX] don't erase CopyToRegs when folding movs into loads (#149393)
We may still need to keep CopyToReg even after folding uses into vector
loads, since the original register may be used in other blocks.
Partially reverts 1fdbe6984976d9e85ab3b1a93e8de434a85c5646
Commit: b02787d33f24d83f1d5814c578b7b0fce7156382
https://github.com/llvm/llvm-project/commit/b02787d33f24d83f1d5814c578b7b0fce7156382
Author: Andres-Salamanca <andrealebarbaritos at gmail.com>
Date: 2025-07-18 (Fri, 18 Jul 2025)
Changed paths:
M clang/include/clang/CIR/Dialect/IR/CIROps.td
M clang/lib/CIR/CodeGen/CIRGenBuilder.h
M clang/lib/CIR/CodeGen/CIRGenExpr.cpp
M clang/lib/CIR/Lowering/DirectToLLVM/LowerToLLVM.cpp
M clang/test/CIR/CodeGen/bitfields.c
M clang/test/CIR/CodeGen/bitfields.cpp
M clang/test/CIR/CodeGen/bitfields_be.c
Log Message:
-----------
[CIR] Fix alignment when lowering set/get bitfield operations (#148999)
This PR fixes incorrect alignment when lowering `set` and `getBitField`
operations to LLVM IR. The issue occurred because during lowering, the
function was being called with an alignment of 0, which caused it to
default to the alignment of the packed member. For example, if the
bitfield was packed inside a `u64i`, it would use an alignment of 8.
With this change, the generated code now matches what the classic
codegen produces.
In the assembly format, I changed to be similar to how it's done in
loadOp. If there's a better approach, please feel free to point it out.
Commit: 965b68e8f26ea51202adfd2ab6429a68e8ce63c3
https://github.com/llvm/llvm-project/commit/965b68e8f26ea51202adfd2ab6429a68e8ce63c3
Author: Alex MacLean <amaclean at nvidia.com>
Date: 2025-07-18 (Fri, 18 Jul 2025)
Changed paths:
M llvm/lib/Target/NVPTX/NVPTXISelLowering.cpp
M llvm/test/CodeGen/NVPTX/bf16x2-instructions.ll
M llvm/test/CodeGen/NVPTX/f16x2-instructions.ll
M llvm/test/CodeGen/NVPTX/f32x2-instructions.ll
Log Message:
-----------
[NVPTX] Prevent fptrunc of v2f32 from being folded into store (#149571)
Commit: 3641448e08961d8b8621fafa01167f96d948ee9e
https://github.com/llvm/llvm-project/commit/3641448e08961d8b8621fafa01167f96d948ee9e
Author: Jonas Devlieghere <jonas at devlieghere.com>
Date: 2025-07-18 (Fri, 18 Jul 2025)
Changed paths:
M lldb/source/Target/Thread.cpp
Log Message:
-----------
[lldb] Use StopInfoSP instead of StopInfo* (NFC)
Don't make assumptions about the lifetime of the underlying object and
use the shared_ptr to participate in reference counting and extend the
lifetime of the object to the end of the lexical scope.
Commit: 1b8a136a09bfed49ae008a354946804230055153
https://github.com/llvm/llvm-project/commit/1b8a136a09bfed49ae008a354946804230055153
Author: Florian Mayer <fmayer at google.com>
Date: 2025-07-18 (Fri, 18 Jul 2025)
Changed paths:
M clang/lib/CodeGen/CGDebugInfo.cpp
Log Message:
-----------
[Sanitizer] remove array-bounds-pseudofn (#149430)
This has been replaced by -fsanitize-annotate-debug-info
Commit: 6d8e53d4afe46608f47bcb014387c053829cdcf1
https://github.com/llvm/llvm-project/commit/6d8e53d4afe46608f47bcb014387c053829cdcf1
Author: Stanislav Mekhanoshin <Stanislav.Mekhanoshin at amd.com>
Date: 2025-07-18 (Fri, 18 Jul 2025)
Changed paths:
M llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
M llvm/lib/Target/AMDGPU/BUFInstructions.td
M llvm/lib/Target/AMDGPU/FLATInstructions.td
M llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.cpp
M llvm/lib/Target/AMDGPU/SIDefines.h
M llvm/lib/Target/AMDGPU/SIInstrFormats.td
M llvm/lib/Target/AMDGPU/SMInstructions.td
A llvm/test/MC/AMDGPU/gfx1250_asm_smem.s
A llvm/test/MC/AMDGPU/gfx1250_asm_vbuffer_mubuf.s
M llvm/test/MC/AMDGPU/gfx1250_asm_vflat.s
A llvm/test/MC/Disassembler/AMDGPU/gfx1250_dasm_smem.txt
A llvm/test/MC/Disassembler/AMDGPU/gfx1250_dasm_vbuffer_mubuf.txt
M llvm/test/MC/Disassembler/AMDGPU/gfx1250_dasm_vflat.txt
Log Message:
-----------
[AMDGPU] Support nv memory instructions modifier on gfx1250 (#149582)
Commit: 921c6dbecaf49e3ed24b94802f094cd7f61f1873
https://github.com/llvm/llvm-project/commit/921c6dbecaf49e3ed24b94802f094cd7f61f1873
Author: Prabhu Rajasekaran <prabhukr at google.com>
Date: 2025-07-18 (Fri, 18 Jul 2025)
Changed paths:
A llvm/docs/CalleeTypeMetadata.rst
M llvm/docs/LangRef.rst
M llvm/docs/Reference.rst
M llvm/include/llvm/IR/FixedMetadataKinds.def
M llvm/include/llvm/IR/Metadata.h
M llvm/lib/IR/Metadata.cpp
M llvm/lib/IR/Verifier.cpp
M llvm/lib/Transforms/InstCombine/InstCombineCalls.cpp
M llvm/lib/Transforms/Utils/Local.cpp
M llvm/lib/Transforms/Utils/ValueMapper.cpp
A llvm/test/Assembler/callee-type-metadata.ll
A llvm/test/Transforms/Inline/drop-callee-type-metadata.ll
A llvm/test/Transforms/InstCombine/drop-callee-type-metadata.ll
A llvm/test/Transforms/SimplifyCFG/merge-callee-type-metadata.ll
A llvm/test/Verifier/callee-type-metadata.ll
Log Message:
-----------
[llvm] Introduce callee_type metadata
Introduce `callee_type` metadata which will be attached to the indirect
call instructions.
The `callee_type` metadata will be used to generate `.callgraph` section
described in this RFC:
https://lists.llvm.org/pipermail/llvm-dev/2021-July/151739.html
Reviewers: morehouse, petrhosek, nikic, ilovepi
Reviewed By: nikic, ilovepi
Pull Request: https://github.com/llvm/llvm-project/pull/87573
Commit: c99c213e725adee22c386d2059118a49f0c57054
https://github.com/llvm/llvm-project/commit/c99c213e725adee22c386d2059118a49f0c57054
Author: Diego Caballero <dieg0ca6aller0 at gmail.com>
Date: 2025-07-18 (Fri, 18 Jul 2025)
Changed paths:
M flang/include/flang/Optimizer/Support/InitFIR.h
M flang/lib/Optimizer/Builder/PPCIntrinsicCall.cpp
M flang/lib/Optimizer/CodeGen/CMakeLists.txt
M flang/lib/Optimizer/CodeGen/CodeGen.cpp
Log Message:
-----------
[mlir][Flang][NFC] Replace use of `vector.insertelement/extractelement` (#143272)
This PR is part of the last step to remove `vector.extractelement` and
`vector.insertelement` ops (RFC:
https://discourse.llvm.org/t/rfc-psa-remove-vector-extractelement-and-vector-insertelement-ops-in-favor-of-vector-extract-and-vector-insert-ops).
It replaces `vector.insertelement` and `vector.extractelement` with
`vector.insert` and `vector.extract` in Flang. It looks like no lit
tests are impacted?
Commit: 2e67dcfdcd023df2f06e0823eeea23990ce41534
https://github.com/llvm/llvm-project/commit/2e67dcfdcd023df2f06e0823eeea23990ce41534
Author: Kelvin Li <kli at ca.ibm.com>
Date: 2025-07-18 (Fri, 18 Jul 2025)
Changed paths:
M flang/test/Lower/PowerPC/ppc-vec-extract-elem-order.f90
M flang/test/Lower/PowerPC/ppc-vec-extract.f90
M flang/test/Lower/PowerPC/ppc-vec-insert-elem-order.f90
M flang/test/Lower/PowerPC/ppc-vec-insert.f90
M flang/test/Lower/PowerPC/ppc-vec-splat-elem-order.f90
M flang/test/Lower/PowerPC/ppc-vec-splat.f90
Log Message:
-----------
[flang] update ppc lit tests after using vector.insert and vector.extract (NFC) (#148775)
See https://github.com/llvm/llvm-project/pull/143272
Commit: c9f6c5cda69f0d3cd6ec3f041c4f770dc37150ae
https://github.com/llvm/llvm-project/commit/c9f6c5cda69f0d3cd6ec3f041c4f770dc37150ae
Author: Necip Fazil Yildiran <necip at google.com>
Date: 2025-07-18 (Fri, 18 Jul 2025)
Changed paths:
M .github/workflows/build-ci-container-windows.yml
M .github/workflows/build-ci-container.yml
M clang-tools-extra/clangd/unittests/FindTargetTests.cpp
M clang-tools-extra/clangd/unittests/HoverTests.cpp
M clang-tools-extra/docs/clang-tidy/Contributing.rst
M clang/docs/ReleaseNotes.rst
M clang/include/clang/AST/ASTContext.h
M clang/include/clang/AST/FormatString.h
M clang/include/clang/AST/RecursiveASTVisitor.h
M clang/include/clang/AST/Type.h
M clang/include/clang/AST/TypeLoc.h
M clang/include/clang/AST/TypeProperties.td
M clang/include/clang/Basic/BuiltinsAMDGPU.def
M clang/include/clang/Basic/TypeNodes.td
M clang/include/clang/CIR/Dialect/IR/CIROps.td
M clang/include/clang/Sema/Overload.h
M clang/include/clang/Serialization/TypeBitCodes.def
M clang/include/clang/StaticAnalyzer/Core/PathSensitive/ExprEngine.h
M clang/lib/AST/ASTContext.cpp
M clang/lib/AST/ASTImporter.cpp
M clang/lib/AST/ASTStructuralEquivalence.cpp
M clang/lib/AST/ByteCode/Descriptor.cpp
M clang/lib/AST/ByteCode/Descriptor.h
M clang/lib/AST/ByteCode/Disasm.cpp
M clang/lib/AST/ByteCode/Interp.cpp
M clang/lib/AST/ByteCode/InterpBlock.h
M clang/lib/AST/ByteCode/InterpBuiltin.cpp
M clang/lib/AST/ByteCode/InterpFrame.cpp
M clang/lib/AST/ByteCode/Pointer.h
M clang/lib/AST/FormatString.cpp
M clang/lib/AST/ItaniumMangle.cpp
M clang/lib/AST/PrintfFormatString.cpp
M clang/lib/AST/ScanfFormatString.cpp
M clang/lib/AST/Type.cpp
M clang/lib/AST/TypePrinter.cpp
M clang/lib/CIR/CodeGen/CIRGenBuilder.h
M clang/lib/CIR/CodeGen/CIRGenExpr.cpp
M clang/lib/CIR/Lowering/DirectToLLVM/LowerToLLVM.cpp
M clang/lib/CodeGen/CGCall.cpp
M clang/lib/CodeGen/CGCoroutine.cpp
M clang/lib/CodeGen/CGDebugInfo.cpp
M clang/lib/CodeGen/CGObjCMac.cpp
M clang/lib/CodeGen/CodeGenFunction.cpp
M clang/lib/CodeGen/TargetBuiltins/AMDGPU.cpp
M clang/lib/Driver/ToolChain.cpp
M clang/lib/Format/TokenAnnotator.cpp
M clang/lib/Sema/SemaChecking.cpp
M clang/lib/Sema/SemaConcept.cpp
M clang/lib/Sema/SemaExpr.cpp
M clang/lib/Sema/SemaExprCXX.cpp
M clang/lib/Sema/SemaOverload.cpp
M clang/lib/Sema/TreeTransform.h
M clang/lib/Serialization/ASTReader.cpp
M clang/lib/Serialization/ASTWriter.cpp
M clang/lib/StaticAnalyzer/Checkers/MallocChecker.cpp
M clang/lib/StaticAnalyzer/Checkers/StdLibraryFunctionsChecker.cpp
M clang/lib/StaticAnalyzer/Checkers/VLASizeChecker.cpp
M clang/lib/StaticAnalyzer/Core/ExprEngine.cpp
M clang/lib/StaticAnalyzer/Core/ExprEngineC.cpp
M clang/test/AST/ByteCode/mutable.cpp
M clang/test/AST/ByteCode/unions.cpp
M clang/test/AST/HLSL/is_structured_resource_element_compatible_concept.hlsl
M clang/test/AST/ast-dump-array.cpp
M clang/test/AST/ast-dump-expr-json.c
M clang/test/AST/ast-dump-expr-json.cpp
M clang/test/AST/ast-dump-expr.c
M clang/test/AST/ast-dump-expr.cpp
M clang/test/AST/ast-dump-openmp-distribute-parallel-for-simd.c
M clang/test/AST/ast-dump-openmp-distribute-parallel-for.c
M clang/test/AST/ast-dump-openmp-target-teams-distribute-parallel-for-simd.c
M clang/test/AST/ast-dump-openmp-target-teams-distribute-parallel-for.c
M clang/test/AST/ast-dump-openmp-teams-distribute-parallel-for-simd.c
M clang/test/AST/ast-dump-openmp-teams-distribute-parallel-for.c
M clang/test/AST/ast-dump-stmt-json.cpp
M clang/test/AST/ast-dump-stmt.cpp
M clang/test/AST/ast-dump-traits.cpp
M clang/test/AST/ast-dump-types-errors-json.cpp
M clang/test/Analysis/cfg.cpp
A clang/test/Analysis/div-zero-cxx20.cpp
M clang/test/Analysis/div-zero.cpp
M clang/test/Analysis/explain-svals.cpp
M clang/test/Analysis/std-c-library-functions-arg-weakdeps.c
M clang/test/Analysis/std-c-library-functions-lookup.c
M clang/test/Analysis/std-c-library-functions-vs-stream-checker.c
M clang/test/Analysis/std-c-library-functions.c
M clang/test/CIR/CodeGen/bitfields.c
M clang/test/CIR/CodeGen/bitfields.cpp
M clang/test/CIR/CodeGen/bitfields_be.c
M clang/test/CXX/drs/cwg2xx.cpp
M clang/test/CXX/lex/lex.literal/lex.ext/p2.cpp
M clang/test/CXX/lex/lex.literal/lex.ext/p5.cpp
M clang/test/CXX/lex/lex.literal/lex.ext/p7.cpp
M clang/test/CodeGen/64bit-swiftcall.c
M clang/test/CodeGen/AArch64/byval-temp.c
M clang/test/CodeGen/AArch64/pure-scalable-args-empty-union.c
M clang/test/CodeGen/AArch64/pure-scalable-args.c
M clang/test/CodeGen/AArch64/struct-coerce-using-ptr.cpp
M clang/test/CodeGen/AArch64/sve-acle-__ARM_FEATURE_SVE_VECTOR_OPERATORS.c
M clang/test/CodeGen/AArch64/sve-acle-__ARM_FEATURE_SVE_VECTOR_OPERATORS.cpp
M clang/test/CodeGen/LoongArch/bitint.c
M clang/test/CodeGen/PowerPC/ppc64-vector.c
M clang/test/CodeGen/RISCV/riscv-abi.cpp
M clang/test/CodeGen/RISCV/riscv-vector-callingconv-llvm-ir.c
M clang/test/CodeGen/RISCV/riscv-vector-callingconv-llvm-ir.cpp
M clang/test/CodeGen/RISCV/riscv32-abi.c
M clang/test/CodeGen/RISCV/riscv32-vararg.c
M clang/test/CodeGen/RISCV/riscv64-abi.c
M clang/test/CodeGen/RISCV/riscv64-vararg.c
M clang/test/CodeGen/SystemZ/systemz-abi-vector.c
M clang/test/CodeGen/SystemZ/systemz-abi.c
M clang/test/CodeGen/SystemZ/systemz-inline-asm.c
M clang/test/CodeGen/X86/cx-complex-range.c
M clang/test/CodeGen/X86/x86_32-arguments-win32.c
M clang/test/CodeGen/X86/x86_64-arguments-win32.c
M clang/test/CodeGen/aapcs64-align.cpp
M clang/test/CodeGen/arm-aapcs-vfp.c
M clang/test/CodeGen/arm-abi-vector.c
M clang/test/CodeGen/arm-swiftcall.c
M clang/test/CodeGen/arm64-abi-vector.c
M clang/test/CodeGen/arm64-arguments.c
M clang/test/CodeGen/arm64-microsoft-arguments.cpp
M clang/test/CodeGen/armv7k-abi.c
M clang/test/CodeGen/atomic-arm64.c
M clang/test/CodeGen/attr-noundef.cpp
M clang/test/CodeGen/cx-complex-range.c
M clang/test/CodeGen/ext-int-cc.c
M clang/test/CodeGen/isfpclass.c
M clang/test/CodeGen/math-libcalls-tbaa-indirect-args.c
M clang/test/CodeGen/mingw-long-double.c
M clang/test/CodeGen/ms_abi.c
M clang/test/CodeGen/pass-by-value-noalias.c
M clang/test/CodeGen/ptrauth-in-c-struct.c
M clang/test/CodeGen/regcall.c
M clang/test/CodeGen/regcall2.c
M clang/test/CodeGen/regcall4.c
M clang/test/CodeGen/sparcv9-abi.c
M clang/test/CodeGen/vectorcall.c
M clang/test/CodeGen/win-fp128.c
M clang/test/CodeGen/win64-i128.c
M clang/test/CodeGen/windows-swiftcall.c
M clang/test/CodeGenCXX/aarch64-mangle-sve-vectors.cpp
M clang/test/CodeGenCXX/arm-cc.cpp
M clang/test/CodeGenCXX/attr-target-mv-inalloca.cpp
M clang/test/CodeGenCXX/copy-initialization.cpp
M clang/test/CodeGenCXX/debug-info.cpp
M clang/test/CodeGenCXX/empty-nontrivially-copyable.cpp
M clang/test/CodeGenCXX/fastcall.cpp
M clang/test/CodeGenCXX/homogeneous-aggregates.cpp
M clang/test/CodeGenCXX/inalloca-lambda.cpp
M clang/test/CodeGenCXX/inalloca-overaligned.cpp
M clang/test/CodeGenCXX/inalloca-vector.cpp
M clang/test/CodeGenCXX/inheriting-constructor.cpp
M clang/test/CodeGenCXX/member-function-pointer-calls.cpp
M clang/test/CodeGenCXX/microsoft-abi-arg-order.cpp
M clang/test/CodeGenCXX/microsoft-abi-byval-thunks.cpp
M clang/test/CodeGenCXX/microsoft-abi-member-pointers.cpp
M clang/test/CodeGenCXX/microsoft-abi-sret-and-byval.cpp
M clang/test/CodeGenCXX/microsoft-abi-unknown-arch.cpp
M clang/test/CodeGenCXX/ms-property.cpp
M clang/test/CodeGenCXX/nrvo.cpp
M clang/test/CodeGenCXX/pass-by-value-noalias.cpp
M clang/test/CodeGenCXX/ptrauth-qualifier-struct.cpp
M clang/test/CodeGenCXX/regparm.cpp
M clang/test/CodeGenCXX/trivial_abi.cpp
M clang/test/CodeGenCXX/uncopyable-args.cpp
M clang/test/CodeGenCXX/wasm-args-returns.cpp
M clang/test/CodeGenCXX/windows-x86-swiftcall.cpp
M clang/test/CodeGenObjC/nontrivial-c-struct-exception.m
M clang/test/CodeGenObjC/pass-by-value-noalias.m
M clang/test/CodeGenObjC/weak-in-c-struct.m
M clang/test/CodeGenObjCXX/objc-struct-cxx-abi.mm
M clang/test/CodeGenObjCXX/property-objects.mm
M clang/test/CodeGenObjCXX/ptrauth-struct-cxx-abi.mm
M clang/test/CodeGenOpenCL/builtins-amdgcn-gfx1250.cl
M clang/test/Driver/print-multi-selection-flags.c
M clang/test/FixIt/fixit-format-ios-nopedantic.m
M clang/test/FixIt/format.m
M clang/test/Headers/stdarg.cpp
M clang/test/OpenMP/for_firstprivate_codegen.cpp
M clang/test/OpenMP/parallel_firstprivate_codegen.cpp
M clang/test/OpenMP/sections_firstprivate_codegen.cpp
M clang/test/OpenMP/single_firstprivate_codegen.cpp
M clang/test/OpenMP/target_teams_distribute_firstprivate_codegen.cpp
M clang/test/OpenMP/target_teams_distribute_parallel_for_firstprivate_codegen.cpp
M clang/test/OpenMP/teams_distribute_firstprivate_codegen.cpp
M clang/test/OpenMP/teams_distribute_parallel_for_firstprivate_codegen.cpp
M clang/test/OpenMP/teams_firstprivate_codegen.cpp
M clang/test/Sema/dllexport.c
M clang/test/Sema/format-strings-fixit-ssize_t.c
M clang/test/Sema/format-strings-int-typedefs.c
M clang/test/Sema/format-strings-scanf.c
M clang/test/Sema/format-strings-size_t.c
M clang/test/Sema/matrix-type-builtins.c
M clang/test/Sema/ptrauth-atomic-ops.c
M clang/test/Sema/ptrauth.c
M clang/test/SemaCXX/cxx2c-trivially-relocatable.cpp
M clang/test/SemaCXX/enum-scoped.cpp
M clang/test/SemaCXX/microsoft-varargs-diagnostics.cpp
M clang/test/SemaCXX/new-delete.cpp
M clang/test/SemaCXX/overload-resolution-deferred-templates.cpp
M clang/test/SemaCXX/static-assert-cxx26.cpp
M clang/test/SemaCXX/type-aware-new-delete-basic-free-declarations.cpp
M clang/test/SemaCXX/unavailable_aligned_allocation.cpp
M clang/test/SemaHLSL/Language/AssignArray.hlsl
M clang/test/SemaHLSL/Language/InitListAST.hlsl
M clang/test/SemaObjC/format-size-spec-nsinteger.m
M clang/test/SemaObjC/matrix-type-builtins.m
M clang/test/SemaOpenCL/cl20-device-side-enqueue.cl
M clang/test/SemaTemplate/concepts-using-decl.cpp
M clang/test/SemaTemplate/type_pack_element.cpp
M clang/tools/libclang/CIndex.cpp
M clang/unittests/Format/TokenAnnotatorTest.cpp
M flang-rt/include/flang-rt/runtime/descriptor.h
M flang-rt/lib/runtime/assign.cpp
M flang-rt/lib/runtime/descriptor.cpp
M flang-rt/lib/runtime/edit-input.cpp
M flang-rt/lib/runtime/pointer.cpp
M flang-rt/unittests/Runtime/NumericalFormatTest.cpp
M flang/include/flang/Lower/Runtime.h
M flang/include/flang/Optimizer/Builder/Runtime/Intrinsics.h
M flang/include/flang/Optimizer/Support/InitFIR.h
M flang/include/flang/Runtime/pointer.h
M flang/lib/Lower/Bridge.cpp
M flang/lib/Lower/ConvertConstant.cpp
M flang/lib/Lower/ConvertExpr.cpp
M flang/lib/Lower/ConvertVariable.cpp
M flang/lib/Lower/Runtime.cpp
M flang/lib/Lower/VectorSubscripts.cpp
M flang/lib/Optimizer/Builder/FIRBuilder.cpp
M flang/lib/Optimizer/Builder/PPCIntrinsicCall.cpp
M flang/lib/Optimizer/Builder/Runtime/Intrinsics.cpp
M flang/lib/Optimizer/Builder/Runtime/Stop.cpp
M flang/lib/Optimizer/CodeGen/CMakeLists.txt
M flang/lib/Optimizer/CodeGen/CodeGen.cpp
M flang/lib/Optimizer/HLFIR/Transforms/LowerHLFIROrderedAssignments.cpp
M flang/lib/Optimizer/Transforms/MemoryUtils.cpp
M flang/lib/Optimizer/Transforms/PolymorphicOpConversion.cpp
M flang/lib/Optimizer/Transforms/SimplifyFIROperations.cpp
M flang/lib/Semantics/check-do-forall.cpp
M flang/lib/Semantics/resolve-directives.cpp
M flang/lib/Semantics/resolve-labels.cpp
M flang/test/Fir/alloc-32.fir
M flang/test/Fir/alloc.fir
M flang/test/Fir/arrexp.fir
M flang/test/Fir/convert-to-llvm.fir
M flang/test/Lower/CUDA/cuda-set-allocator.cuf
M flang/test/Lower/OpenACC/acc-loop.f90
M flang/test/Lower/PowerPC/ppc-vec-extract-elem-order.f90
M flang/test/Lower/PowerPC/ppc-vec-extract.f90
M flang/test/Lower/PowerPC/ppc-vec-insert-elem-order.f90
M flang/test/Lower/PowerPC/ppc-vec-insert.f90
M flang/test/Lower/PowerPC/ppc-vec-splat-elem-order.f90
M flang/test/Lower/PowerPC/ppc-vec-splat.f90
M flang/test/Lower/forall/character-1.f90
M flang/test/Lower/polymorphic.f90
M flang/test/Semantics/OpenACC/acc-kernels-loop.f90
M flang/test/Semantics/PowerPC/ppc-vector-types01.f90
M flang/test/Semantics/PowerPC/ppc-vector-types02.f90
M flang/test/Semantics/resolve40.f90
M flang/unittests/Optimizer/FortranVariableTest.cpp
M libc/benchmarks/gpu/LibcGpuBenchmark.cpp
M libc/benchmarks/gpu/src/math/atan2_benchmark.cpp
A libc/benchmarks/gpu/src/math/platform.h
M libc/benchmarks/gpu/src/math/sin_benchmark.cpp
M libc/benchmarks/gpu/timing/amdgpu/timing.h
M libc/benchmarks/gpu/timing/nvptx/timing.h
M libc/cmake/modules/LLVMLibCTestRules.cmake
R libc/include/dirent.h.def
M libc/include/dirent.yaml
M libc/include/llvm-libc-macros/math-macros.h
R libc/include/search.h.def
M libc/include/search.yaml
R libc/include/setjmp.h.def
M libc/include/setjmp.yaml
R libc/include/spawn.h.def
M libc/include/spawn.yaml
R libc/include/string.h.def
M libc/include/string.yaml
R libc/include/strings.h.def
M libc/include/strings.yaml
R libc/include/sys/sendfile.h.def
M libc/include/sys/sendfile.yaml
R libc/include/sys/statvfs.h.def
M libc/include/sys/statvfs.yaml
M libc/include/sys/types.yaml
R libc/include/sys/uio.h.def
M libc/include/sys/uio.yaml
R libc/include/sys/utsname.h.def
M libc/include/sys/utsname.yaml
R libc/include/threads.h.def
M libc/include/threads.yaml
R libc/include/uchar.h.def
M libc/include/uchar.yaml
M libc/shared/math.h
A libc/shared/math/exp10f16.h
M libc/src/__support/macros/properties/architectures.h
M libc/src/__support/math/CMakeLists.txt
A libc/src/__support/math/exp10_float16_constants.h
A libc/src/__support/math/exp10f16.h
A libc/src/__support/math/exp10f16_utils.h
M libc/src/math/generic/CMakeLists.txt
M libc/src/math/generic/exp10f16.cpp
M libc/src/math/generic/exp10m1f16.cpp
M libc/src/math/generic/expxf16.h
M libc/test/include/CMakeLists.txt
A libc/test/include/math_constants_test.c
M libcxx/docs/ReleaseNotes/21.rst
M libcxx/include/__config
M libcxx/include/__config_site.in
M libcxx/include/limits
M libcxx/src/random.cpp
M libcxx/test/libcxx/containers/sequences/deque/spare_block_handling.pass.cpp
M libcxx/test/libcxx/fuzzing/random.pass.cpp
M libcxx/test/std/depr/depr.c.headers/math_h.pass.cpp
M libcxx/test/std/language.support/support.limits/limits/numeric.limits.members/traps.pass.cpp
M libcxx/test/std/numerics/c.math/cmath.pass.cpp
M lld/ELF/BPSectionOrderer.cpp
M lld/test/ELF/bp-section-orderer.s
M lld/test/ELF/hexagon-plt.s
M lld/test/ELF/hexagon-shared.s
M lld/test/ELF/hexagon-tls-gd-xform.s
M lldb/bindings/interface/SBSaveCoreOptionsDocstrings.i
M lldb/cmake/modules/LLDBFramework.cmake
M lldb/include/lldb/API/SBMemoryRegionInfoList.h
M lldb/include/lldb/API/SBSaveCoreOptions.h
M lldb/include/lldb/Core/PluginManager.h
M lldb/include/lldb/Symbol/SaveCoreOptions.h
M lldb/scripts/framework-header-fix.py
M lldb/scripts/version-header-fix.py
M lldb/source/API/CMakeLists.txt
M lldb/source/API/SBProcess.cpp
M lldb/source/API/SBSaveCoreOptions.cpp
M lldb/source/Commands/CommandObjectProcess.cpp
M lldb/source/Core/PluginManager.cpp
M lldb/source/DataFormatters/ValueObjectPrinter.cpp
M lldb/source/Expression/IRExecutionUnit.cpp
M lldb/source/Plugins/ObjectFile/Minidump/MinidumpFileBuilder.cpp
M lldb/source/Plugins/SymbolLocator/Debuginfod/SymbolLocatorDebuginfod.cpp
M lldb/source/Plugins/TypeSystem/Clang/TypeSystemClang.cpp
M lldb/source/Symbol/SaveCoreOptions.cpp
M lldb/source/Target/Thread.cpp
M lldb/test/API/functionalities/data-formatter/nsdictionarysynth/TestNSDictionarySynthetic.py
A lldb/test/API/functionalities/process_save_core_minidump/TestProcessSaveCoreMinidump64b.py
M lldb/test/API/lang/cpp/frame-var-depth-and-elem-count/TestFrameVarDepthAndElemCount.py
M lldb/test/API/python_api/sbsavecoreoptions/TestSBSaveCoreOptions.py
M lldb/test/Shell/Scripts/TestFrameworkFixScript.test
M lldb/test/Shell/Scripts/TestRPCFrameworkFixScript.test
M lldb/test/Shell/SymbolFile/PDB/Inputs/UdtLayoutTest.script
M lldb/tools/lldb-dap/DAP.cpp
M llvm/Maintainers.md
M llvm/docs/CodingStandards.rst
M llvm/docs/Extensions.rst
M llvm/include/llvm/ADT/CombinationGenerator.h
M llvm/include/llvm/ADT/STLForwardCompat.h
M llvm/include/llvm/Analysis/IVDescriptors.h
M llvm/include/llvm/BinaryFormat/ELF.h
M llvm/include/llvm/CodeGen/MachineBlockFrequencyInfo.h
M llvm/include/llvm/CodeGen/MachineFunctionAnalysis.h
M llvm/include/llvm/IR/DebugInfo.h
M llvm/include/llvm/IR/DebugInfoMetadata.h
M llvm/include/llvm/IR/IntrinsicsAMDGPU.td
M llvm/include/llvm/IR/PassManager.h
M llvm/include/llvm/MC/MCDisassembler/MCDisassembler.h
M llvm/include/llvm/MC/MCObjectStreamer.h
M llvm/include/llvm/MC/MCSection.h
M llvm/include/llvm/MC/MCStreamer.h
M llvm/include/llvm/Passes/CodeGenPassBuilder.h
M llvm/include/llvm/Transforms/Utils/SSAUpdater.h
M llvm/lib/Analysis/IVDescriptors.cpp
M llvm/lib/CodeGen/AsmPrinter/AsmPrinter.cpp
M llvm/lib/CodeGen/CodeGenPrepare.cpp
M llvm/lib/CodeGen/MachineBlockFrequencyInfo.cpp
M llvm/lib/CodeGen/MachineDebugify.cpp
M llvm/lib/CodeGen/MachineFunction.cpp
M llvm/lib/CodeGen/MachineFunctionAnalysis.cpp
M llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
M llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
M llvm/lib/DWARFLinker/Classic/DWARFLinker.cpp
M llvm/lib/DebugInfo/LogicalView/Core/LVScope.cpp
M llvm/lib/IR/DebugInfo.cpp
M llvm/lib/IR/DebugInfoMetadata.cpp
M llvm/lib/MC/MCObjectStreamer.cpp
M llvm/lib/MC/MCParser/ELFAsmParser.cpp
M llvm/lib/MC/MCParser/MCTargetAsmParser.cpp
M llvm/lib/MC/MCSectionELF.cpp
M llvm/lib/MC/MCStreamer.cpp
M llvm/lib/Object/ELF.cpp
M llvm/lib/Object/IRSymtab.cpp
M llvm/lib/Passes/PassRegistry.def
M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
M llvm/lib/Target/AMDGPU/AMDGPU.h
M llvm/lib/Target/AMDGPU/AMDGPUGISel.td
M llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp
M llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.h
M llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
M llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.h
M llvm/lib/Target/AMDGPU/AMDGPUPassRegistry.def
A llvm/lib/Target/AMDGPU/AMDGPUPrepareAGPRAlloc.cpp
A llvm/lib/Target/AMDGPU/AMDGPUPrepareAGPRAlloc.h
M llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp
M llvm/lib/Target/AMDGPU/AMDGPUResourceUsageAnalysis.cpp
M llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
M llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.h
M llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
M llvm/lib/Target/AMDGPU/BUFInstructions.td
M llvm/lib/Target/AMDGPU/CMakeLists.txt
M llvm/lib/Target/AMDGPU/FLATInstructions.td
M llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.cpp
M llvm/lib/Target/AMDGPU/SIDefines.h
M llvm/lib/Target/AMDGPU/SIFixSGPRCopies.cpp
M llvm/lib/Target/AMDGPU/SIISelLowering.cpp
M llvm/lib/Target/AMDGPU/SIInstrFormats.td
M llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
M llvm/lib/Target/AMDGPU/SIInstrInfo.h
M llvm/lib/Target/AMDGPU/SIInstrInfo.td
M llvm/lib/Target/AMDGPU/SIInstructions.td
M llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.cpp
M llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
M llvm/lib/Target/AMDGPU/SIRegisterInfo.h
M llvm/lib/Target/AMDGPU/SMInstructions.td
M llvm/lib/Target/AMDGPU/VOP1Instructions.td
M llvm/lib/Target/AMDGPU/VOPInstructions.td
M llvm/lib/Target/Hexagon/Disassembler/HexagonDisassembler.cpp
M llvm/lib/Target/Hexagon/MCTargetDesc/HexagonInstPrinter.cpp
M llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCTargetDesc.cpp
M llvm/lib/Target/LoongArch/LoongArchFrameLowering.cpp
M llvm/lib/Target/NVPTX/NVPTXISelLowering.cpp
M llvm/lib/Target/RISCV/RISCVFrameLowering.cpp
M llvm/lib/Target/RISCV/RISCVInterleavedAccess.cpp
M llvm/lib/Target/RISCV/RISCVVectorMaskDAGMutation.cpp
M llvm/lib/Target/X86/X86CallingConv.cpp
M llvm/lib/Target/X86/X86ISelLowering.cpp
M llvm/lib/TargetParser/X86TargetParser.cpp
M llvm/lib/Transforms/Coroutines/CoroFrame.cpp
M llvm/lib/Transforms/Coroutines/CoroInternal.h
M llvm/lib/Transforms/Coroutines/CoroSplit.cpp
M llvm/lib/Transforms/Coroutines/SpillUtils.cpp
M llvm/lib/Transforms/IPO/MergeFunctions.cpp
M llvm/lib/Transforms/InstCombine/InstCombineInternal.h
M llvm/lib/Transforms/InstCombine/InstructionCombining.cpp
M llvm/lib/Transforms/Scalar/ConstraintElimination.cpp
M llvm/lib/Transforms/Scalar/DeadStoreElimination.cpp
M llvm/lib/Transforms/Scalar/GVN.cpp
M llvm/lib/Transforms/Scalar/JumpThreading.cpp
M llvm/lib/Transforms/Scalar/LoopInterchange.cpp
M llvm/lib/Transforms/Scalar/LoopStrengthReduce.cpp
M llvm/lib/Transforms/Utils/CodeExtractor.cpp
M llvm/lib/Transforms/Utils/Debugify.cpp
M llvm/lib/Transforms/Utils/InlineFunction.cpp
M llvm/lib/Transforms/Utils/Local.cpp
M llvm/lib/Transforms/Utils/LoopRotationUtils.cpp
M llvm/lib/Transforms/Utils/LoopUtils.cpp
M llvm/lib/Transforms/Utils/MemoryTaggingSupport.cpp
M llvm/lib/Transforms/Utils/PromoteMemoryToRegister.cpp
M llvm/lib/Transforms/Utils/SSAUpdater.cpp
M llvm/lib/Transforms/Utils/SimplifyCFG.cpp
M llvm/lib/Transforms/Vectorize/LoopVectorizationPlanner.h
M llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
M llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
M llvm/lib/Transforms/Vectorize/VPlanAnalysis.cpp
M llvm/lib/Transforms/Vectorize/VPlanAnalysis.h
M llvm/lib/Transforms/Vectorize/VPlanConstruction.cpp
M llvm/lib/Transforms/Vectorize/VPlanRecipes.cpp
M llvm/lib/Transforms/Vectorize/VPlanTransforms.h
M llvm/test/CodeGen/AArch64/freeze.ll
M llvm/test/CodeGen/AArch64/sve-intrinsics-ldst-ext.ll
M llvm/test/CodeGen/AMDGPU/accvgpr-copy.mir
M llvm/test/CodeGen/AMDGPU/add.v2i16.ll
M llvm/test/CodeGen/AMDGPU/agpr-remat.ll
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.1024bit.ll
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.128bit.ll
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.16bit.ll
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.256bit.ll
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.320bit.ll
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.32bit.ll
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.48bit.ll
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.512bit.ll
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.64bit.ll
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.96bit.ll
M llvm/test/CodeGen/AMDGPU/amdgpu-codegenprepare-idiv.ll
A llvm/test/CodeGen/AMDGPU/amdgpu-prepare-agpr-alloc.mir
A llvm/test/CodeGen/AMDGPU/atomicrmw-bf16-gfx11plus.ll
A llvm/test/CodeGen/AMDGPU/bad-agpr-vgpr-regalloc-priority.mir
M llvm/test/CodeGen/AMDGPU/bf16.ll
M llvm/test/CodeGen/AMDGPU/branch-folding-implicit-def-subreg.ll
M llvm/test/CodeGen/AMDGPU/buffer-fat-pointer-atomicrmw-fadd.ll
M llvm/test/CodeGen/AMDGPU/buffer-fat-pointer-atomicrmw-fmax.ll
M llvm/test/CodeGen/AMDGPU/buffer-fat-pointer-atomicrmw-fmin.ll
M llvm/test/CodeGen/AMDGPU/buffer-fat-pointers-memcpy.ll
M llvm/test/CodeGen/AMDGPU/calling-conventions.ll
M llvm/test/CodeGen/AMDGPU/cvt_f32_ubyte.ll
M llvm/test/CodeGen/AMDGPU/dagcombine-fmul-sel.ll
M llvm/test/CodeGen/AMDGPU/div_i128.ll
M llvm/test/CodeGen/AMDGPU/divergence-driven-buildvector.ll
M llvm/test/CodeGen/AMDGPU/fabs.bf16.ll
M llvm/test/CodeGen/AMDGPU/flat-atomicrmw-fadd.ll
M llvm/test/CodeGen/AMDGPU/flat-atomicrmw-fmax.ll
M llvm/test/CodeGen/AMDGPU/flat-atomicrmw-fmin.ll
M llvm/test/CodeGen/AMDGPU/flat-atomicrmw-fsub.ll
A llvm/test/CodeGen/AMDGPU/flat-saddr-atomics.ll
M llvm/test/CodeGen/AMDGPU/fmax3-maximumnum.ll
M llvm/test/CodeGen/AMDGPU/fmed3.bf16.ll
M llvm/test/CodeGen/AMDGPU/fmin3-minimumnum.ll
M llvm/test/CodeGen/AMDGPU/freeze.ll
M llvm/test/CodeGen/AMDGPU/function-args.ll
M llvm/test/CodeGen/AMDGPU/gfx-callable-argument-types.ll
M llvm/test/CodeGen/AMDGPU/global-atomicrmw-fadd.ll
M llvm/test/CodeGen/AMDGPU/global-atomicrmw-fmax.ll
M llvm/test/CodeGen/AMDGPU/global-atomicrmw-fmin.ll
M llvm/test/CodeGen/AMDGPU/global-atomicrmw-fsub.ll
M llvm/test/CodeGen/AMDGPU/global-saddr-load.ll
M llvm/test/CodeGen/AMDGPU/idot4u.ll
M llvm/test/CodeGen/AMDGPU/inflate-av-remat-imm.mir
M llvm/test/CodeGen/AMDGPU/inflated-reg-class-snippet-copy-use-after-free.mir
M llvm/test/CodeGen/AMDGPU/isel-amdgpu-cs-chain-preserve-cc.ll
M llvm/test/CodeGen/AMDGPU/llc-pipeline-npm.ll
M llvm/test/CodeGen/AMDGPU/llc-pipeline.ll
A llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.sat.pk.ll
A llvm/test/CodeGen/AMDGPU/llvm.amdgcn.mfma.form.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.mfma.gfx950.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.mfma.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.permlane16.swap.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.prng.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.rcp.bf16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.rsq.bf16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.tanh.ll
M llvm/test/CodeGen/AMDGPU/llvm.exp2.bf16.ll
M llvm/test/CodeGen/AMDGPU/llvm.log.ll
M llvm/test/CodeGen/AMDGPU/llvm.log10.ll
M llvm/test/CodeGen/AMDGPU/llvm.log2.ll
M llvm/test/CodeGen/AMDGPU/llvm.rint.f64.ll
M llvm/test/CodeGen/AMDGPU/llvm.round.f64.ll
M llvm/test/CodeGen/AMDGPU/llvm.sqrt.bf16.ll
M llvm/test/CodeGen/AMDGPU/mad-mix-hi.ll
M llvm/test/CodeGen/AMDGPU/maximumnum.bf16.ll
M llvm/test/CodeGen/AMDGPU/minimumnum.bf16.ll
M llvm/test/CodeGen/AMDGPU/no-fold-accvgpr-mov.ll
M llvm/test/CodeGen/AMDGPU/no-fold-accvgpr-mov.mir
M llvm/test/CodeGen/AMDGPU/no-fold-accvgpr-read.mir
M llvm/test/CodeGen/AMDGPU/partial-regcopy-and-spill-missed-at-regalloc.ll
M llvm/test/CodeGen/AMDGPU/ptradd-sdag-optimizations.ll
M llvm/test/CodeGen/AMDGPU/regalloc-undef-copy-fold.mir
M llvm/test/CodeGen/AMDGPU/rem_i128.ll
M llvm/test/CodeGen/AMDGPU/select-undef.ll
A llvm/test/CodeGen/AMDGPU/sgpr-to-vreg1-copy.ll
A llvm/test/CodeGen/AMDGPU/sgpr-to-vreg1-copy.mir
M llvm/test/CodeGen/AMDGPU/spill-agpr.mir
M llvm/test/CodeGen/AMDGPU/spill-vector-superclass.ll
M llvm/test/CodeGen/AMDGPU/srem.ll
M llvm/test/CodeGen/AMDGPU/srem64.ll
M llvm/test/CodeGen/AMDGPU/sub.v2i16.ll
M llvm/test/CodeGen/AMDGPU/swdev502267-use-after-free-last-chance-recoloring-alloc-succeeds.mir
M llvm/test/CodeGen/AMDGPU/vector-reduce-smax.ll
M llvm/test/CodeGen/AMDGPU/vector-reduce-smin.ll
M llvm/test/CodeGen/AMDGPU/vector-reduce-umax.ll
M llvm/test/CodeGen/AMDGPU/vector-reduce-umin.ll
M llvm/test/CodeGen/LoongArch/calling-conv-common.ll
M llvm/test/CodeGen/LoongArch/calling-conv-half.ll
M llvm/test/CodeGen/LoongArch/can-not-realign-stack.ll
M llvm/test/CodeGen/LoongArch/emergency-spill-slot.ll
M llvm/test/CodeGen/LoongArch/frame.ll
M llvm/test/CodeGen/LoongArch/intrinsic-memcpy.ll
M llvm/test/CodeGen/LoongArch/lasx/fpowi.ll
M llvm/test/CodeGen/LoongArch/lasx/ir-instruction/extractelement.ll
M llvm/test/CodeGen/LoongArch/lasx/ir-instruction/insertelement.ll
M llvm/test/CodeGen/LoongArch/llvm.sincos.ll
A llvm/test/CodeGen/LoongArch/lsx/pr146455.ll
M llvm/test/CodeGen/LoongArch/stack-realignment-with-variable-sized-objects.ll
M llvm/test/CodeGen/LoongArch/stack-realignment.ll
M llvm/test/CodeGen/LoongArch/unaligned-memcpy-inline.ll
M llvm/test/CodeGen/LoongArch/vararg.ll
M llvm/test/CodeGen/MIR/X86/call-site-info-ambiguous-indirect-call-typeid.mir
M llvm/test/CodeGen/MIR/X86/call-site-info-direct-calls-typeid.mir
M llvm/test/CodeGen/MIR/X86/call-site-info-typeid.mir
M llvm/test/CodeGen/NVPTX/bf16x2-instructions.ll
M llvm/test/CodeGen/NVPTX/f16x2-instructions.ll
M llvm/test/CodeGen/NVPTX/f32x2-instructions.ll
M llvm/test/CodeGen/NVPTX/i16x2-instructions.ll
M llvm/test/CodeGen/NVPTX/i8x4-instructions.ll
A llvm/test/CodeGen/NVPTX/pr126337.ll
M llvm/test/CodeGen/NVPTX/reduction-intrinsics.ll
A llvm/test/CodeGen/NVPTX/trunc-tofp.ll
M llvm/test/CodeGen/RISCV/rvv/combine-reduce-add-to-vcpop.ll
M llvm/test/CodeGen/RISCV/rvv/extractelt-i1.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-extract-i1.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-interleaved-access.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-deinterleave.ll
A llvm/test/CodeGen/RISCV/rvv/reproducer-pr146855.ll
M llvm/test/CodeGen/RISCV/rvv/vector-deinterleave-load.ll
M llvm/test/CodeGen/RISCV/rvv/vscale-vw-web-simplification.ll
M llvm/test/CodeGen/RISCV/rvv/vselect-fp.ll
M llvm/test/CodeGen/RISCV/short-forward-branch-opt.ll
M llvm/test/CodeGen/RISCV/zdinx-spill.ll
A llvm/test/CodeGen/X86/function-align.ll
M llvm/test/CodeGen/X86/vector-bitreverse.ll
M llvm/test/Instrumentation/AddressSanitizer/lifetime.ll
A llvm/test/MC/AMDGPU/gfx1250_asm_smem.s
A llvm/test/MC/AMDGPU/gfx1250_asm_vbuffer_mubuf.s
M llvm/test/MC/AMDGPU/gfx1250_asm_vflat.s
M llvm/test/MC/AMDGPU/gfx1250_asm_vop1-fake16.s
M llvm/test/MC/AMDGPU/gfx1250_asm_vop1.s
M llvm/test/MC/AMDGPU/gfx1250_asm_vop1_dpp16-fake16.s
M llvm/test/MC/AMDGPU/gfx1250_asm_vop1_dpp16.s
M llvm/test/MC/AMDGPU/gfx1250_asm_vop1_dpp8-fake16.s
M llvm/test/MC/AMDGPU/gfx1250_asm_vop1_dpp8.s
M llvm/test/MC/AMDGPU/gfx1250_asm_vop3_from_vop1-fake16.s
M llvm/test/MC/AMDGPU/gfx1250_asm_vop3_from_vop1.s
M llvm/test/MC/AMDGPU/gfx1250_asm_vop3_from_vop1_dpp16-fake16.s
M llvm/test/MC/AMDGPU/gfx1250_asm_vop3_from_vop1_dpp16.s
M llvm/test/MC/AMDGPU/gfx1250_asm_vop3_from_vop1_dpp8-fake16.s
M llvm/test/MC/AMDGPU/gfx1250_asm_vop3_from_vop1_dpp8.s
M llvm/test/MC/AsmParser/llvm_section_types.s
A llvm/test/MC/Disassembler/AMDGPU/gfx1250_dasm_smem.txt
A llvm/test/MC/Disassembler/AMDGPU/gfx1250_dasm_vbuffer_mubuf.txt
M llvm/test/MC/Disassembler/AMDGPU/gfx1250_dasm_vflat.txt
M llvm/test/MC/Disassembler/AMDGPU/gfx1250_dasm_vop1.txt
M llvm/test/MC/Disassembler/AMDGPU/gfx1250_dasm_vop1_dpp16.txt
M llvm/test/MC/Disassembler/AMDGPU/gfx1250_dasm_vop1_dpp8.txt
M llvm/test/MC/Disassembler/AMDGPU/gfx1250_dasm_vop3_from_vop1.txt
M llvm/test/MC/Disassembler/AMDGPU/gfx1250_dasm_vop3_from_vop1_dpp16.txt
M llvm/test/MC/Disassembler/AMDGPU/gfx1250_dasm_vop3_from_vop1_dpp8.txt
M llvm/test/MC/Hexagon/two_ext.s
M llvm/test/MC/RISCV/Relocations/mc-dump.s
M llvm/test/MC/X86/verify-callgraph-section.s
M llvm/test/Transforms/DeadStoreElimination/zeroed-missing.ll
A llvm/test/Transforms/LoopInterchange/force-interchange.ll
A llvm/test/Transforms/LoopInterchange/fp-reductions.ll
M llvm/test/Transforms/LoopInterchange/reductions-non-wrapped-operations.ll
A llvm/test/Transforms/LoopStrengthReduce/X86/lifetime-use.ll
M llvm/test/Transforms/LoopUnroll/AArch64/apple-unrolling.ll
A llvm/test/Transforms/LoopUnroll/partial-unroll-reductions.ll
A llvm/test/Transforms/LoopUnroll/runtime-unroll-reductions.ll
M llvm/test/Transforms/LoopVectorize/AArch64/fmax-without-fast-math-flags.ll
M llvm/test/Transforms/LoopVectorize/AArch64/fmin-without-fast-math-flags.ll
A llvm/test/Transforms/LoopVectorize/AArch64/maxbandwidth-regpressure.ll
M llvm/test/Transforms/LoopVectorize/fmax-without-fast-math-flags-interleave.ll
M llvm/test/Transforms/LoopVectorize/fmax-without-fast-math-flags.ll
M llvm/test/Transforms/LoopVectorize/fmin-without-fast-math-flags.ll
M llvm/test/Transforms/LoopVectorize/minmax_reduction.ll
M llvm/test/Transforms/SLPVectorizer/RISCV/reordered-buildvector-scalars.ll
M llvm/test/Transforms/SLPVectorizer/X86/split-node-reorder-node-with-ops.ll
M llvm/test/Transforms/SimplifyCFG/switch-dup-bbs.ll
M llvm/test/Transforms/SimplifyCFG/switch-range-to-icmp.ll
M llvm/test/tools/llc/new-pm/start-stop.ll
A llvm/test/tools/llvm-objdump/ELF/Hexagon/hexagon-bundles.s
M llvm/test/tools/llvm-profdata/c-general.test
A llvm/test/tools/llvm-profdata/show-hot.proftext
M llvm/tools/llvm-dis/llvm-dis.cpp
M llvm/tools/llvm-mc/Disassembler.cpp
M llvm/tools/llvm-objdump/llvm-objdump.cpp
M llvm/tools/llvm-profdata/llvm-profdata.cpp
M llvm/tools/llvm-readobj/ELFDumper.cpp
M llvm/unittests/ADT/STLForwardCompatTest.cpp
M llvm/unittests/CodeGen/LexicalScopesTest.cpp
M llvm/unittests/IR/DebugInfoTest.cpp
M llvm/unittests/Transforms/Utils/DebugifyTest.cpp
M llvm/unittests/Transforms/Utils/LocalTest.cpp
M llvm/utils/TableGen/Common/CodeGenRegisters.cpp
M llvm/utils/TableGen/Common/CodeGenRegisters.h
M llvm/utils/TableGen/Common/CodeGenSchedule.cpp
M llvm/utils/gn/secondary/libcxx/include/BUILD.gn
M llvm/utils/gn/secondary/llvm/lib/Target/AMDGPU/BUILD.gn
M llvm/utils/gn/secondary/llvm/test/BUILD.gn
A llvm/utils/gn/secondary/llvm/tools/llvm-ir2vec/BUILD.gn
M mlir/docs/Tutorials/transform/Ch2.md
M mlir/include/mlir/Conversion/VectorToXeGPU/VectorToXeGPU.h
M mlir/include/mlir/Dialect/SPIRV/Transforms/Passes.td
M mlir/include/mlir/IR/OpDefinition.h
M mlir/include/mlir/IR/Operation.h
M mlir/include/mlir/IR/OperationSupport.h
M mlir/lib/AsmParser/Parser.cpp
M mlir/lib/Conversion/MemRefToEmitC/MemRefToEmitC.cpp
M mlir/lib/Dialect/Linalg/Transforms/TilingInterfaceImpl.cpp
M mlir/lib/Dialect/SPIRV/Transforms/CMakeLists.txt
A mlir/lib/Dialect/SPIRV/Transforms/ConvertToReplicatedConstantCompositePass.cpp
M mlir/lib/Dialect/Tosa/Transforms/TosaReduceTransposes.cpp
M mlir/test/Conversion/MemRefToEmitC/memref-to-emitc.mlir
A mlir/test/Dialect/SPIRV/Transforms/replicated-const-composites.mlir
M mlir/test/Interfaces/TilingInterface/tile-and-fuse-consumer.mlir
M mlir/unittests/Debug/FileLineColLocBreakpointManagerTest.cpp
M mlir/unittests/IR/OperationSupportTest.cpp
M mlir/unittests/IR/ValueTest.cpp
M mlir/unittests/Transforms/DialectConversion.cpp
M offload/plugins-nextgen/amdgpu/src/rtl.cpp
M offload/plugins-nextgen/common/include/PluginInterface.h
M offload/plugins-nextgen/cuda/src/rtl.cpp
M offload/unittests/OffloadAPI/common/Fixtures.hpp
M offload/unittests/OffloadAPI/event/olWaitEvent.cpp
M openmp/runtime/src/kmp.h
M openmp/runtime/src/kmp_tasking.cpp
M utils/bazel/llvm-project-overlay/libc/BUILD.bazel
Log Message:
-----------
[𝘀𝗽𝗿] changes introduced through rebase
Created using spr 1.3.6-beta.1
[skip ci]
Commit: 959263125e5d47d255b38afc6df750fdb7fcff4c
https://github.com/llvm/llvm-project/commit/959263125e5d47d255b38afc6df750fdb7fcff4c
Author: prabhukr <prabhukr at google.com>
Date: 2025-07-18 (Fri, 18 Jul 2025)
Changed paths:
M .github/workflows/build-ci-container-windows.yml
M .github/workflows/build-ci-container.yml
M clang-tools-extra/clangd/unittests/FindTargetTests.cpp
M clang-tools-extra/clangd/unittests/HoverTests.cpp
M clang-tools-extra/docs/clang-tidy/Contributing.rst
M clang/docs/ReleaseNotes.rst
M clang/include/clang/AST/ASTContext.h
M clang/include/clang/AST/FormatString.h
M clang/include/clang/AST/RecursiveASTVisitor.h
M clang/include/clang/AST/Type.h
M clang/include/clang/AST/TypeLoc.h
M clang/include/clang/AST/TypeProperties.td
M clang/include/clang/Basic/BuiltinsAMDGPU.def
M clang/include/clang/Basic/TypeNodes.td
M clang/include/clang/CIR/Dialect/IR/CIROps.td
M clang/include/clang/Sema/Overload.h
M clang/include/clang/Serialization/TypeBitCodes.def
M clang/include/clang/StaticAnalyzer/Core/PathSensitive/ExprEngine.h
M clang/lib/AST/ASTContext.cpp
M clang/lib/AST/ASTImporter.cpp
M clang/lib/AST/ASTStructuralEquivalence.cpp
M clang/lib/AST/ByteCode/Descriptor.cpp
M clang/lib/AST/ByteCode/Descriptor.h
M clang/lib/AST/ByteCode/Disasm.cpp
M clang/lib/AST/ByteCode/Interp.cpp
M clang/lib/AST/ByteCode/InterpBlock.h
M clang/lib/AST/ByteCode/InterpBuiltin.cpp
M clang/lib/AST/ByteCode/InterpFrame.cpp
M clang/lib/AST/ByteCode/Pointer.h
M clang/lib/AST/FormatString.cpp
M clang/lib/AST/ItaniumMangle.cpp
M clang/lib/AST/PrintfFormatString.cpp
M clang/lib/AST/ScanfFormatString.cpp
M clang/lib/AST/Type.cpp
M clang/lib/AST/TypePrinter.cpp
M clang/lib/CIR/CodeGen/CIRGenBuilder.h
M clang/lib/CIR/CodeGen/CIRGenExpr.cpp
M clang/lib/CIR/Lowering/DirectToLLVM/LowerToLLVM.cpp
M clang/lib/CodeGen/CGCall.cpp
M clang/lib/CodeGen/CGCoroutine.cpp
M clang/lib/CodeGen/CGDebugInfo.cpp
M clang/lib/CodeGen/CGObjCMac.cpp
M clang/lib/CodeGen/CodeGenFunction.cpp
M clang/lib/CodeGen/TargetBuiltins/AMDGPU.cpp
M clang/lib/Driver/ToolChain.cpp
M clang/lib/Format/TokenAnnotator.cpp
M clang/lib/Sema/SemaChecking.cpp
M clang/lib/Sema/SemaConcept.cpp
M clang/lib/Sema/SemaExpr.cpp
M clang/lib/Sema/SemaExprCXX.cpp
M clang/lib/Sema/SemaOverload.cpp
M clang/lib/Sema/TreeTransform.h
M clang/lib/Serialization/ASTReader.cpp
M clang/lib/Serialization/ASTWriter.cpp
M clang/lib/StaticAnalyzer/Checkers/MallocChecker.cpp
M clang/lib/StaticAnalyzer/Checkers/StdLibraryFunctionsChecker.cpp
M clang/lib/StaticAnalyzer/Checkers/VLASizeChecker.cpp
M clang/lib/StaticAnalyzer/Core/ExprEngine.cpp
M clang/lib/StaticAnalyzer/Core/ExprEngineC.cpp
M clang/test/AST/ByteCode/mutable.cpp
M clang/test/AST/ByteCode/unions.cpp
M clang/test/AST/HLSL/is_structured_resource_element_compatible_concept.hlsl
M clang/test/AST/ast-dump-array.cpp
M clang/test/AST/ast-dump-expr-json.c
M clang/test/AST/ast-dump-expr-json.cpp
M clang/test/AST/ast-dump-expr.c
M clang/test/AST/ast-dump-expr.cpp
M clang/test/AST/ast-dump-openmp-distribute-parallel-for-simd.c
M clang/test/AST/ast-dump-openmp-distribute-parallel-for.c
M clang/test/AST/ast-dump-openmp-target-teams-distribute-parallel-for-simd.c
M clang/test/AST/ast-dump-openmp-target-teams-distribute-parallel-for.c
M clang/test/AST/ast-dump-openmp-teams-distribute-parallel-for-simd.c
M clang/test/AST/ast-dump-openmp-teams-distribute-parallel-for.c
M clang/test/AST/ast-dump-stmt-json.cpp
M clang/test/AST/ast-dump-stmt.cpp
M clang/test/AST/ast-dump-traits.cpp
M clang/test/AST/ast-dump-types-errors-json.cpp
M clang/test/Analysis/cfg.cpp
A clang/test/Analysis/div-zero-cxx20.cpp
M clang/test/Analysis/div-zero.cpp
M clang/test/Analysis/explain-svals.cpp
M clang/test/Analysis/std-c-library-functions-arg-weakdeps.c
M clang/test/Analysis/std-c-library-functions-lookup.c
M clang/test/Analysis/std-c-library-functions-vs-stream-checker.c
M clang/test/Analysis/std-c-library-functions.c
M clang/test/CIR/CodeGen/bitfields.c
M clang/test/CIR/CodeGen/bitfields.cpp
M clang/test/CIR/CodeGen/bitfields_be.c
M clang/test/CXX/drs/cwg2xx.cpp
M clang/test/CXX/lex/lex.literal/lex.ext/p2.cpp
M clang/test/CXX/lex/lex.literal/lex.ext/p5.cpp
M clang/test/CXX/lex/lex.literal/lex.ext/p7.cpp
M clang/test/CodeGen/64bit-swiftcall.c
M clang/test/CodeGen/AArch64/byval-temp.c
M clang/test/CodeGen/AArch64/pure-scalable-args-empty-union.c
M clang/test/CodeGen/AArch64/pure-scalable-args.c
M clang/test/CodeGen/AArch64/struct-coerce-using-ptr.cpp
M clang/test/CodeGen/AArch64/sve-acle-__ARM_FEATURE_SVE_VECTOR_OPERATORS.c
M clang/test/CodeGen/AArch64/sve-acle-__ARM_FEATURE_SVE_VECTOR_OPERATORS.cpp
M clang/test/CodeGen/LoongArch/bitint.c
M clang/test/CodeGen/PowerPC/ppc64-vector.c
M clang/test/CodeGen/RISCV/riscv-abi.cpp
M clang/test/CodeGen/RISCV/riscv-vector-callingconv-llvm-ir.c
M clang/test/CodeGen/RISCV/riscv-vector-callingconv-llvm-ir.cpp
M clang/test/CodeGen/RISCV/riscv32-abi.c
M clang/test/CodeGen/RISCV/riscv32-vararg.c
M clang/test/CodeGen/RISCV/riscv64-abi.c
M clang/test/CodeGen/RISCV/riscv64-vararg.c
M clang/test/CodeGen/SystemZ/systemz-abi-vector.c
M clang/test/CodeGen/SystemZ/systemz-abi.c
M clang/test/CodeGen/SystemZ/systemz-inline-asm.c
M clang/test/CodeGen/X86/cx-complex-range.c
M clang/test/CodeGen/X86/x86_32-arguments-win32.c
M clang/test/CodeGen/X86/x86_64-arguments-win32.c
M clang/test/CodeGen/aapcs64-align.cpp
M clang/test/CodeGen/arm-aapcs-vfp.c
M clang/test/CodeGen/arm-abi-vector.c
M clang/test/CodeGen/arm-swiftcall.c
M clang/test/CodeGen/arm64-abi-vector.c
M clang/test/CodeGen/arm64-arguments.c
M clang/test/CodeGen/arm64-microsoft-arguments.cpp
M clang/test/CodeGen/armv7k-abi.c
M clang/test/CodeGen/atomic-arm64.c
M clang/test/CodeGen/attr-noundef.cpp
M clang/test/CodeGen/cx-complex-range.c
M clang/test/CodeGen/ext-int-cc.c
M clang/test/CodeGen/isfpclass.c
M clang/test/CodeGen/math-libcalls-tbaa-indirect-args.c
M clang/test/CodeGen/mingw-long-double.c
M clang/test/CodeGen/ms_abi.c
M clang/test/CodeGen/pass-by-value-noalias.c
M clang/test/CodeGen/ptrauth-in-c-struct.c
M clang/test/CodeGen/regcall.c
M clang/test/CodeGen/regcall2.c
M clang/test/CodeGen/regcall4.c
M clang/test/CodeGen/sparcv9-abi.c
M clang/test/CodeGen/vectorcall.c
M clang/test/CodeGen/win-fp128.c
M clang/test/CodeGen/win64-i128.c
M clang/test/CodeGen/windows-swiftcall.c
M clang/test/CodeGenCXX/aarch64-mangle-sve-vectors.cpp
M clang/test/CodeGenCXX/arm-cc.cpp
M clang/test/CodeGenCXX/attr-target-mv-inalloca.cpp
M clang/test/CodeGenCXX/copy-initialization.cpp
M clang/test/CodeGenCXX/debug-info.cpp
M clang/test/CodeGenCXX/empty-nontrivially-copyable.cpp
M clang/test/CodeGenCXX/fastcall.cpp
M clang/test/CodeGenCXX/homogeneous-aggregates.cpp
M clang/test/CodeGenCXX/inalloca-lambda.cpp
M clang/test/CodeGenCXX/inalloca-overaligned.cpp
M clang/test/CodeGenCXX/inalloca-vector.cpp
M clang/test/CodeGenCXX/inheriting-constructor.cpp
M clang/test/CodeGenCXX/member-function-pointer-calls.cpp
M clang/test/CodeGenCXX/microsoft-abi-arg-order.cpp
M clang/test/CodeGenCXX/microsoft-abi-byval-thunks.cpp
M clang/test/CodeGenCXX/microsoft-abi-member-pointers.cpp
M clang/test/CodeGenCXX/microsoft-abi-sret-and-byval.cpp
M clang/test/CodeGenCXX/microsoft-abi-unknown-arch.cpp
M clang/test/CodeGenCXX/ms-property.cpp
M clang/test/CodeGenCXX/nrvo.cpp
M clang/test/CodeGenCXX/pass-by-value-noalias.cpp
M clang/test/CodeGenCXX/ptrauth-qualifier-struct.cpp
M clang/test/CodeGenCXX/regparm.cpp
M clang/test/CodeGenCXX/trivial_abi.cpp
M clang/test/CodeGenCXX/uncopyable-args.cpp
M clang/test/CodeGenCXX/wasm-args-returns.cpp
M clang/test/CodeGenCXX/windows-x86-swiftcall.cpp
M clang/test/CodeGenObjC/nontrivial-c-struct-exception.m
M clang/test/CodeGenObjC/pass-by-value-noalias.m
M clang/test/CodeGenObjC/weak-in-c-struct.m
M clang/test/CodeGenObjCXX/objc-struct-cxx-abi.mm
M clang/test/CodeGenObjCXX/property-objects.mm
M clang/test/CodeGenObjCXX/ptrauth-struct-cxx-abi.mm
M clang/test/CodeGenOpenCL/builtins-amdgcn-gfx1250.cl
M clang/test/Driver/print-multi-selection-flags.c
M clang/test/FixIt/fixit-format-ios-nopedantic.m
M clang/test/FixIt/format.m
M clang/test/Headers/stdarg.cpp
M clang/test/OpenMP/for_firstprivate_codegen.cpp
M clang/test/OpenMP/parallel_firstprivate_codegen.cpp
M clang/test/OpenMP/sections_firstprivate_codegen.cpp
M clang/test/OpenMP/single_firstprivate_codegen.cpp
M clang/test/OpenMP/target_teams_distribute_firstprivate_codegen.cpp
M clang/test/OpenMP/target_teams_distribute_parallel_for_firstprivate_codegen.cpp
M clang/test/OpenMP/teams_distribute_firstprivate_codegen.cpp
M clang/test/OpenMP/teams_distribute_parallel_for_firstprivate_codegen.cpp
M clang/test/OpenMP/teams_firstprivate_codegen.cpp
M clang/test/Sema/dllexport.c
M clang/test/Sema/format-strings-fixit-ssize_t.c
M clang/test/Sema/format-strings-int-typedefs.c
M clang/test/Sema/format-strings-scanf.c
M clang/test/Sema/format-strings-size_t.c
M clang/test/Sema/matrix-type-builtins.c
M clang/test/Sema/ptrauth-atomic-ops.c
M clang/test/Sema/ptrauth.c
M clang/test/SemaCXX/cxx2c-trivially-relocatable.cpp
M clang/test/SemaCXX/enum-scoped.cpp
M clang/test/SemaCXX/microsoft-varargs-diagnostics.cpp
M clang/test/SemaCXX/new-delete.cpp
M clang/test/SemaCXX/overload-resolution-deferred-templates.cpp
M clang/test/SemaCXX/static-assert-cxx26.cpp
M clang/test/SemaCXX/type-aware-new-delete-basic-free-declarations.cpp
M clang/test/SemaCXX/unavailable_aligned_allocation.cpp
M clang/test/SemaHLSL/Language/AssignArray.hlsl
M clang/test/SemaHLSL/Language/InitListAST.hlsl
M clang/test/SemaObjC/format-size-spec-nsinteger.m
M clang/test/SemaObjC/matrix-type-builtins.m
M clang/test/SemaOpenCL/cl20-device-side-enqueue.cl
M clang/test/SemaTemplate/concepts-using-decl.cpp
M clang/test/SemaTemplate/type_pack_element.cpp
M clang/tools/libclang/CIndex.cpp
M clang/unittests/Format/TokenAnnotatorTest.cpp
M flang-rt/include/flang-rt/runtime/descriptor.h
M flang-rt/lib/runtime/assign.cpp
M flang-rt/lib/runtime/descriptor.cpp
M flang-rt/lib/runtime/edit-input.cpp
M flang-rt/lib/runtime/pointer.cpp
M flang-rt/unittests/Runtime/NumericalFormatTest.cpp
M flang/include/flang/Lower/Runtime.h
M flang/include/flang/Optimizer/Builder/Runtime/Intrinsics.h
M flang/include/flang/Optimizer/Support/InitFIR.h
M flang/include/flang/Runtime/pointer.h
M flang/lib/Lower/Bridge.cpp
M flang/lib/Lower/ConvertConstant.cpp
M flang/lib/Lower/ConvertExpr.cpp
M flang/lib/Lower/ConvertVariable.cpp
M flang/lib/Lower/Runtime.cpp
M flang/lib/Lower/VectorSubscripts.cpp
M flang/lib/Optimizer/Builder/FIRBuilder.cpp
M flang/lib/Optimizer/Builder/PPCIntrinsicCall.cpp
M flang/lib/Optimizer/Builder/Runtime/Intrinsics.cpp
M flang/lib/Optimizer/Builder/Runtime/Stop.cpp
M flang/lib/Optimizer/CodeGen/CMakeLists.txt
M flang/lib/Optimizer/CodeGen/CodeGen.cpp
M flang/lib/Optimizer/HLFIR/Transforms/LowerHLFIROrderedAssignments.cpp
M flang/lib/Optimizer/Transforms/MemoryUtils.cpp
M flang/lib/Optimizer/Transforms/PolymorphicOpConversion.cpp
M flang/lib/Optimizer/Transforms/SimplifyFIROperations.cpp
M flang/lib/Semantics/check-do-forall.cpp
M flang/lib/Semantics/resolve-directives.cpp
M flang/lib/Semantics/resolve-labels.cpp
M flang/test/Fir/alloc-32.fir
M flang/test/Fir/alloc.fir
M flang/test/Fir/arrexp.fir
M flang/test/Fir/convert-to-llvm.fir
M flang/test/Lower/CUDA/cuda-set-allocator.cuf
M flang/test/Lower/OpenACC/acc-loop.f90
M flang/test/Lower/PowerPC/ppc-vec-extract-elem-order.f90
M flang/test/Lower/PowerPC/ppc-vec-extract.f90
M flang/test/Lower/PowerPC/ppc-vec-insert-elem-order.f90
M flang/test/Lower/PowerPC/ppc-vec-insert.f90
M flang/test/Lower/PowerPC/ppc-vec-splat-elem-order.f90
M flang/test/Lower/PowerPC/ppc-vec-splat.f90
M flang/test/Lower/forall/character-1.f90
M flang/test/Lower/polymorphic.f90
M flang/test/Semantics/OpenACC/acc-kernels-loop.f90
M flang/test/Semantics/PowerPC/ppc-vector-types01.f90
M flang/test/Semantics/PowerPC/ppc-vector-types02.f90
M flang/test/Semantics/resolve40.f90
M flang/unittests/Optimizer/FortranVariableTest.cpp
M libc/benchmarks/gpu/LibcGpuBenchmark.cpp
M libc/benchmarks/gpu/src/math/atan2_benchmark.cpp
A libc/benchmarks/gpu/src/math/platform.h
M libc/benchmarks/gpu/src/math/sin_benchmark.cpp
M libc/benchmarks/gpu/timing/amdgpu/timing.h
M libc/benchmarks/gpu/timing/nvptx/timing.h
M libc/cmake/modules/LLVMLibCTestRules.cmake
R libc/include/dirent.h.def
M libc/include/dirent.yaml
M libc/include/llvm-libc-macros/math-macros.h
R libc/include/search.h.def
M libc/include/search.yaml
R libc/include/setjmp.h.def
M libc/include/setjmp.yaml
R libc/include/spawn.h.def
M libc/include/spawn.yaml
R libc/include/string.h.def
M libc/include/string.yaml
R libc/include/strings.h.def
M libc/include/strings.yaml
R libc/include/sys/sendfile.h.def
M libc/include/sys/sendfile.yaml
R libc/include/sys/statvfs.h.def
M libc/include/sys/statvfs.yaml
M libc/include/sys/types.yaml
R libc/include/sys/uio.h.def
M libc/include/sys/uio.yaml
R libc/include/sys/utsname.h.def
M libc/include/sys/utsname.yaml
R libc/include/threads.h.def
M libc/include/threads.yaml
R libc/include/uchar.h.def
M libc/include/uchar.yaml
M libc/shared/math.h
A libc/shared/math/exp10f16.h
M libc/src/__support/macros/properties/architectures.h
M libc/src/__support/math/CMakeLists.txt
A libc/src/__support/math/exp10_float16_constants.h
A libc/src/__support/math/exp10f16.h
A libc/src/__support/math/exp10f16_utils.h
M libc/src/math/generic/CMakeLists.txt
M libc/src/math/generic/exp10f16.cpp
M libc/src/math/generic/exp10m1f16.cpp
M libc/src/math/generic/expxf16.h
M libc/test/include/CMakeLists.txt
A libc/test/include/math_constants_test.c
M libcxx/docs/ReleaseNotes/21.rst
M libcxx/include/__config
M libcxx/include/__config_site.in
M libcxx/include/limits
M libcxx/src/random.cpp
M libcxx/test/libcxx/containers/sequences/deque/spare_block_handling.pass.cpp
M libcxx/test/libcxx/fuzzing/random.pass.cpp
M libcxx/test/std/depr/depr.c.headers/math_h.pass.cpp
M libcxx/test/std/language.support/support.limits/limits/numeric.limits.members/traps.pass.cpp
M libcxx/test/std/numerics/c.math/cmath.pass.cpp
M lld/ELF/BPSectionOrderer.cpp
M lld/test/ELF/bp-section-orderer.s
M lld/test/ELF/hexagon-plt.s
M lld/test/ELF/hexagon-shared.s
M lld/test/ELF/hexagon-tls-gd-xform.s
M lldb/bindings/interface/SBSaveCoreOptionsDocstrings.i
M lldb/cmake/modules/LLDBFramework.cmake
M lldb/include/lldb/API/SBMemoryRegionInfoList.h
M lldb/include/lldb/API/SBSaveCoreOptions.h
M lldb/include/lldb/Core/PluginManager.h
M lldb/include/lldb/Symbol/SaveCoreOptions.h
M lldb/scripts/framework-header-fix.py
M lldb/scripts/version-header-fix.py
M lldb/source/API/CMakeLists.txt
M lldb/source/API/SBProcess.cpp
M lldb/source/API/SBSaveCoreOptions.cpp
M lldb/source/Commands/CommandObjectProcess.cpp
M lldb/source/Core/PluginManager.cpp
M lldb/source/DataFormatters/ValueObjectPrinter.cpp
M lldb/source/Expression/IRExecutionUnit.cpp
M lldb/source/Plugins/ObjectFile/Minidump/MinidumpFileBuilder.cpp
M lldb/source/Plugins/SymbolLocator/Debuginfod/SymbolLocatorDebuginfod.cpp
M lldb/source/Plugins/TypeSystem/Clang/TypeSystemClang.cpp
M lldb/source/Symbol/SaveCoreOptions.cpp
M lldb/source/Target/Thread.cpp
M lldb/test/API/functionalities/data-formatter/nsdictionarysynth/TestNSDictionarySynthetic.py
A lldb/test/API/functionalities/process_save_core_minidump/TestProcessSaveCoreMinidump64b.py
M lldb/test/API/lang/cpp/frame-var-depth-and-elem-count/TestFrameVarDepthAndElemCount.py
M lldb/test/API/python_api/sbsavecoreoptions/TestSBSaveCoreOptions.py
M lldb/test/Shell/Scripts/TestFrameworkFixScript.test
M lldb/test/Shell/Scripts/TestRPCFrameworkFixScript.test
M lldb/test/Shell/SymbolFile/PDB/Inputs/UdtLayoutTest.script
M lldb/tools/lldb-dap/DAP.cpp
M llvm/Maintainers.md
M llvm/docs/CodingStandards.rst
M llvm/docs/Extensions.rst
M llvm/include/llvm/ADT/CombinationGenerator.h
M llvm/include/llvm/ADT/STLForwardCompat.h
M llvm/include/llvm/Analysis/IVDescriptors.h
M llvm/include/llvm/BinaryFormat/ELF.h
M llvm/include/llvm/CodeGen/MachineBlockFrequencyInfo.h
M llvm/include/llvm/CodeGen/MachineFunctionAnalysis.h
M llvm/include/llvm/IR/DebugInfo.h
M llvm/include/llvm/IR/DebugInfoMetadata.h
M llvm/include/llvm/IR/IntrinsicsAMDGPU.td
M llvm/include/llvm/IR/PassManager.h
M llvm/include/llvm/MC/MCDisassembler/MCDisassembler.h
M llvm/include/llvm/MC/MCObjectStreamer.h
M llvm/include/llvm/MC/MCSection.h
M llvm/include/llvm/MC/MCStreamer.h
M llvm/include/llvm/Passes/CodeGenPassBuilder.h
M llvm/include/llvm/Transforms/Utils/SSAUpdater.h
M llvm/lib/Analysis/IVDescriptors.cpp
M llvm/lib/CodeGen/AsmPrinter/AsmPrinter.cpp
M llvm/lib/CodeGen/CodeGenPrepare.cpp
M llvm/lib/CodeGen/MachineBlockFrequencyInfo.cpp
M llvm/lib/CodeGen/MachineDebugify.cpp
M llvm/lib/CodeGen/MachineFunction.cpp
M llvm/lib/CodeGen/MachineFunctionAnalysis.cpp
M llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
M llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
M llvm/lib/DWARFLinker/Classic/DWARFLinker.cpp
M llvm/lib/DebugInfo/LogicalView/Core/LVScope.cpp
M llvm/lib/IR/DebugInfo.cpp
M llvm/lib/IR/DebugInfoMetadata.cpp
M llvm/lib/MC/MCObjectStreamer.cpp
M llvm/lib/MC/MCParser/ELFAsmParser.cpp
M llvm/lib/MC/MCParser/MCTargetAsmParser.cpp
M llvm/lib/MC/MCSectionELF.cpp
M llvm/lib/MC/MCStreamer.cpp
M llvm/lib/Object/ELF.cpp
M llvm/lib/Object/IRSymtab.cpp
M llvm/lib/Passes/PassRegistry.def
M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
M llvm/lib/Target/AMDGPU/AMDGPU.h
M llvm/lib/Target/AMDGPU/AMDGPUGISel.td
M llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp
M llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.h
M llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
M llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.h
M llvm/lib/Target/AMDGPU/AMDGPUPassRegistry.def
A llvm/lib/Target/AMDGPU/AMDGPUPrepareAGPRAlloc.cpp
A llvm/lib/Target/AMDGPU/AMDGPUPrepareAGPRAlloc.h
M llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp
M llvm/lib/Target/AMDGPU/AMDGPUResourceUsageAnalysis.cpp
M llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
M llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.h
M llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
M llvm/lib/Target/AMDGPU/BUFInstructions.td
M llvm/lib/Target/AMDGPU/CMakeLists.txt
M llvm/lib/Target/AMDGPU/FLATInstructions.td
M llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.cpp
M llvm/lib/Target/AMDGPU/SIDefines.h
M llvm/lib/Target/AMDGPU/SIFixSGPRCopies.cpp
M llvm/lib/Target/AMDGPU/SIISelLowering.cpp
M llvm/lib/Target/AMDGPU/SIInstrFormats.td
M llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
M llvm/lib/Target/AMDGPU/SIInstrInfo.h
M llvm/lib/Target/AMDGPU/SIInstrInfo.td
M llvm/lib/Target/AMDGPU/SIInstructions.td
M llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.cpp
M llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
M llvm/lib/Target/AMDGPU/SIRegisterInfo.h
M llvm/lib/Target/AMDGPU/SMInstructions.td
M llvm/lib/Target/AMDGPU/VOP1Instructions.td
M llvm/lib/Target/AMDGPU/VOPInstructions.td
M llvm/lib/Target/Hexagon/Disassembler/HexagonDisassembler.cpp
M llvm/lib/Target/Hexagon/MCTargetDesc/HexagonInstPrinter.cpp
M llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCTargetDesc.cpp
M llvm/lib/Target/LoongArch/LoongArchFrameLowering.cpp
M llvm/lib/Target/NVPTX/NVPTXISelLowering.cpp
M llvm/lib/Target/RISCV/RISCVFrameLowering.cpp
M llvm/lib/Target/RISCV/RISCVInterleavedAccess.cpp
M llvm/lib/Target/RISCV/RISCVVectorMaskDAGMutation.cpp
M llvm/lib/Target/X86/X86CallingConv.cpp
M llvm/lib/Target/X86/X86ISelLowering.cpp
M llvm/lib/TargetParser/X86TargetParser.cpp
M llvm/lib/Transforms/Coroutines/CoroFrame.cpp
M llvm/lib/Transforms/Coroutines/CoroInternal.h
M llvm/lib/Transforms/Coroutines/CoroSplit.cpp
M llvm/lib/Transforms/Coroutines/SpillUtils.cpp
M llvm/lib/Transforms/IPO/MergeFunctions.cpp
M llvm/lib/Transforms/InstCombine/InstCombineInternal.h
M llvm/lib/Transforms/InstCombine/InstructionCombining.cpp
M llvm/lib/Transforms/Scalar/ConstraintElimination.cpp
M llvm/lib/Transforms/Scalar/DeadStoreElimination.cpp
M llvm/lib/Transforms/Scalar/GVN.cpp
M llvm/lib/Transforms/Scalar/JumpThreading.cpp
M llvm/lib/Transforms/Scalar/LoopInterchange.cpp
M llvm/lib/Transforms/Scalar/LoopStrengthReduce.cpp
M llvm/lib/Transforms/Utils/CodeExtractor.cpp
M llvm/lib/Transforms/Utils/Debugify.cpp
M llvm/lib/Transforms/Utils/InlineFunction.cpp
M llvm/lib/Transforms/Utils/Local.cpp
M llvm/lib/Transforms/Utils/LoopRotationUtils.cpp
M llvm/lib/Transforms/Utils/LoopUtils.cpp
M llvm/lib/Transforms/Utils/MemoryTaggingSupport.cpp
M llvm/lib/Transforms/Utils/PromoteMemoryToRegister.cpp
M llvm/lib/Transforms/Utils/SSAUpdater.cpp
M llvm/lib/Transforms/Utils/SimplifyCFG.cpp
M llvm/lib/Transforms/Vectorize/LoopVectorizationPlanner.h
M llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
M llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
M llvm/lib/Transforms/Vectorize/VPlanAnalysis.cpp
M llvm/lib/Transforms/Vectorize/VPlanAnalysis.h
M llvm/lib/Transforms/Vectorize/VPlanConstruction.cpp
M llvm/lib/Transforms/Vectorize/VPlanRecipes.cpp
M llvm/lib/Transforms/Vectorize/VPlanTransforms.h
M llvm/test/CodeGen/AArch64/freeze.ll
M llvm/test/CodeGen/AArch64/sve-intrinsics-ldst-ext.ll
M llvm/test/CodeGen/AMDGPU/accvgpr-copy.mir
M llvm/test/CodeGen/AMDGPU/add.v2i16.ll
M llvm/test/CodeGen/AMDGPU/agpr-remat.ll
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.1024bit.ll
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.128bit.ll
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.16bit.ll
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.256bit.ll
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.320bit.ll
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.32bit.ll
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.48bit.ll
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.512bit.ll
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.64bit.ll
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.96bit.ll
M llvm/test/CodeGen/AMDGPU/amdgpu-codegenprepare-idiv.ll
A llvm/test/CodeGen/AMDGPU/amdgpu-prepare-agpr-alloc.mir
A llvm/test/CodeGen/AMDGPU/atomicrmw-bf16-gfx11plus.ll
A llvm/test/CodeGen/AMDGPU/bad-agpr-vgpr-regalloc-priority.mir
M llvm/test/CodeGen/AMDGPU/bf16.ll
M llvm/test/CodeGen/AMDGPU/branch-folding-implicit-def-subreg.ll
M llvm/test/CodeGen/AMDGPU/buffer-fat-pointer-atomicrmw-fadd.ll
M llvm/test/CodeGen/AMDGPU/buffer-fat-pointer-atomicrmw-fmax.ll
M llvm/test/CodeGen/AMDGPU/buffer-fat-pointer-atomicrmw-fmin.ll
M llvm/test/CodeGen/AMDGPU/buffer-fat-pointers-memcpy.ll
M llvm/test/CodeGen/AMDGPU/calling-conventions.ll
M llvm/test/CodeGen/AMDGPU/cvt_f32_ubyte.ll
M llvm/test/CodeGen/AMDGPU/dagcombine-fmul-sel.ll
M llvm/test/CodeGen/AMDGPU/div_i128.ll
M llvm/test/CodeGen/AMDGPU/divergence-driven-buildvector.ll
M llvm/test/CodeGen/AMDGPU/fabs.bf16.ll
M llvm/test/CodeGen/AMDGPU/flat-atomicrmw-fadd.ll
M llvm/test/CodeGen/AMDGPU/flat-atomicrmw-fmax.ll
M llvm/test/CodeGen/AMDGPU/flat-atomicrmw-fmin.ll
M llvm/test/CodeGen/AMDGPU/flat-atomicrmw-fsub.ll
A llvm/test/CodeGen/AMDGPU/flat-saddr-atomics.ll
M llvm/test/CodeGen/AMDGPU/fmax3-maximumnum.ll
M llvm/test/CodeGen/AMDGPU/fmed3.bf16.ll
M llvm/test/CodeGen/AMDGPU/fmin3-minimumnum.ll
M llvm/test/CodeGen/AMDGPU/freeze.ll
M llvm/test/CodeGen/AMDGPU/function-args.ll
M llvm/test/CodeGen/AMDGPU/gfx-callable-argument-types.ll
M llvm/test/CodeGen/AMDGPU/global-atomicrmw-fadd.ll
M llvm/test/CodeGen/AMDGPU/global-atomicrmw-fmax.ll
M llvm/test/CodeGen/AMDGPU/global-atomicrmw-fmin.ll
M llvm/test/CodeGen/AMDGPU/global-atomicrmw-fsub.ll
M llvm/test/CodeGen/AMDGPU/global-saddr-load.ll
M llvm/test/CodeGen/AMDGPU/idot4u.ll
M llvm/test/CodeGen/AMDGPU/inflate-av-remat-imm.mir
M llvm/test/CodeGen/AMDGPU/inflated-reg-class-snippet-copy-use-after-free.mir
M llvm/test/CodeGen/AMDGPU/isel-amdgpu-cs-chain-preserve-cc.ll
M llvm/test/CodeGen/AMDGPU/llc-pipeline-npm.ll
M llvm/test/CodeGen/AMDGPU/llc-pipeline.ll
A llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.sat.pk.ll
A llvm/test/CodeGen/AMDGPU/llvm.amdgcn.mfma.form.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.mfma.gfx950.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.mfma.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.permlane16.swap.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.prng.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.rcp.bf16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.rsq.bf16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.tanh.ll
M llvm/test/CodeGen/AMDGPU/llvm.exp2.bf16.ll
M llvm/test/CodeGen/AMDGPU/llvm.log.ll
M llvm/test/CodeGen/AMDGPU/llvm.log10.ll
M llvm/test/CodeGen/AMDGPU/llvm.log2.ll
M llvm/test/CodeGen/AMDGPU/llvm.rint.f64.ll
M llvm/test/CodeGen/AMDGPU/llvm.round.f64.ll
M llvm/test/CodeGen/AMDGPU/llvm.sqrt.bf16.ll
M llvm/test/CodeGen/AMDGPU/mad-mix-hi.ll
M llvm/test/CodeGen/AMDGPU/maximumnum.bf16.ll
M llvm/test/CodeGen/AMDGPU/minimumnum.bf16.ll
M llvm/test/CodeGen/AMDGPU/no-fold-accvgpr-mov.ll
M llvm/test/CodeGen/AMDGPU/no-fold-accvgpr-mov.mir
M llvm/test/CodeGen/AMDGPU/no-fold-accvgpr-read.mir
M llvm/test/CodeGen/AMDGPU/partial-regcopy-and-spill-missed-at-regalloc.ll
M llvm/test/CodeGen/AMDGPU/ptradd-sdag-optimizations.ll
M llvm/test/CodeGen/AMDGPU/regalloc-undef-copy-fold.mir
M llvm/test/CodeGen/AMDGPU/rem_i128.ll
M llvm/test/CodeGen/AMDGPU/select-undef.ll
A llvm/test/CodeGen/AMDGPU/sgpr-to-vreg1-copy.ll
A llvm/test/CodeGen/AMDGPU/sgpr-to-vreg1-copy.mir
M llvm/test/CodeGen/AMDGPU/spill-agpr.mir
M llvm/test/CodeGen/AMDGPU/spill-vector-superclass.ll
M llvm/test/CodeGen/AMDGPU/srem.ll
M llvm/test/CodeGen/AMDGPU/srem64.ll
M llvm/test/CodeGen/AMDGPU/sub.v2i16.ll
M llvm/test/CodeGen/AMDGPU/swdev502267-use-after-free-last-chance-recoloring-alloc-succeeds.mir
M llvm/test/CodeGen/AMDGPU/vector-reduce-smax.ll
M llvm/test/CodeGen/AMDGPU/vector-reduce-smin.ll
M llvm/test/CodeGen/AMDGPU/vector-reduce-umax.ll
M llvm/test/CodeGen/AMDGPU/vector-reduce-umin.ll
M llvm/test/CodeGen/LoongArch/calling-conv-common.ll
M llvm/test/CodeGen/LoongArch/calling-conv-half.ll
M llvm/test/CodeGen/LoongArch/can-not-realign-stack.ll
M llvm/test/CodeGen/LoongArch/emergency-spill-slot.ll
M llvm/test/CodeGen/LoongArch/frame.ll
M llvm/test/CodeGen/LoongArch/intrinsic-memcpy.ll
M llvm/test/CodeGen/LoongArch/lasx/fpowi.ll
M llvm/test/CodeGen/LoongArch/lasx/ir-instruction/extractelement.ll
M llvm/test/CodeGen/LoongArch/lasx/ir-instruction/insertelement.ll
M llvm/test/CodeGen/LoongArch/llvm.sincos.ll
A llvm/test/CodeGen/LoongArch/lsx/pr146455.ll
M llvm/test/CodeGen/LoongArch/stack-realignment-with-variable-sized-objects.ll
M llvm/test/CodeGen/LoongArch/stack-realignment.ll
M llvm/test/CodeGen/LoongArch/unaligned-memcpy-inline.ll
M llvm/test/CodeGen/LoongArch/vararg.ll
M llvm/test/CodeGen/MIR/X86/call-site-info-ambiguous-indirect-call-typeid.mir
M llvm/test/CodeGen/MIR/X86/call-site-info-direct-calls-typeid.mir
M llvm/test/CodeGen/MIR/X86/call-site-info-typeid.mir
M llvm/test/CodeGen/NVPTX/bf16x2-instructions.ll
M llvm/test/CodeGen/NVPTX/f16x2-instructions.ll
M llvm/test/CodeGen/NVPTX/f32x2-instructions.ll
M llvm/test/CodeGen/NVPTX/i16x2-instructions.ll
M llvm/test/CodeGen/NVPTX/i8x4-instructions.ll
A llvm/test/CodeGen/NVPTX/pr126337.ll
M llvm/test/CodeGen/NVPTX/reduction-intrinsics.ll
A llvm/test/CodeGen/NVPTX/trunc-tofp.ll
M llvm/test/CodeGen/RISCV/rvv/combine-reduce-add-to-vcpop.ll
M llvm/test/CodeGen/RISCV/rvv/extractelt-i1.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-extract-i1.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-interleaved-access.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-deinterleave.ll
A llvm/test/CodeGen/RISCV/rvv/reproducer-pr146855.ll
M llvm/test/CodeGen/RISCV/rvv/vector-deinterleave-load.ll
M llvm/test/CodeGen/RISCV/rvv/vscale-vw-web-simplification.ll
M llvm/test/CodeGen/RISCV/rvv/vselect-fp.ll
M llvm/test/CodeGen/RISCV/short-forward-branch-opt.ll
M llvm/test/CodeGen/RISCV/zdinx-spill.ll
A llvm/test/CodeGen/X86/function-align.ll
M llvm/test/CodeGen/X86/vector-bitreverse.ll
M llvm/test/Instrumentation/AddressSanitizer/lifetime.ll
A llvm/test/MC/AMDGPU/gfx1250_asm_smem.s
A llvm/test/MC/AMDGPU/gfx1250_asm_vbuffer_mubuf.s
M llvm/test/MC/AMDGPU/gfx1250_asm_vflat.s
M llvm/test/MC/AMDGPU/gfx1250_asm_vop1-fake16.s
M llvm/test/MC/AMDGPU/gfx1250_asm_vop1.s
M llvm/test/MC/AMDGPU/gfx1250_asm_vop1_dpp16-fake16.s
M llvm/test/MC/AMDGPU/gfx1250_asm_vop1_dpp16.s
M llvm/test/MC/AMDGPU/gfx1250_asm_vop1_dpp8-fake16.s
M llvm/test/MC/AMDGPU/gfx1250_asm_vop1_dpp8.s
M llvm/test/MC/AMDGPU/gfx1250_asm_vop3_from_vop1-fake16.s
M llvm/test/MC/AMDGPU/gfx1250_asm_vop3_from_vop1.s
M llvm/test/MC/AMDGPU/gfx1250_asm_vop3_from_vop1_dpp16-fake16.s
M llvm/test/MC/AMDGPU/gfx1250_asm_vop3_from_vop1_dpp16.s
M llvm/test/MC/AMDGPU/gfx1250_asm_vop3_from_vop1_dpp8-fake16.s
M llvm/test/MC/AMDGPU/gfx1250_asm_vop3_from_vop1_dpp8.s
M llvm/test/MC/AsmParser/llvm_section_types.s
A llvm/test/MC/Disassembler/AMDGPU/gfx1250_dasm_smem.txt
A llvm/test/MC/Disassembler/AMDGPU/gfx1250_dasm_vbuffer_mubuf.txt
M llvm/test/MC/Disassembler/AMDGPU/gfx1250_dasm_vflat.txt
M llvm/test/MC/Disassembler/AMDGPU/gfx1250_dasm_vop1.txt
M llvm/test/MC/Disassembler/AMDGPU/gfx1250_dasm_vop1_dpp16.txt
M llvm/test/MC/Disassembler/AMDGPU/gfx1250_dasm_vop1_dpp8.txt
M llvm/test/MC/Disassembler/AMDGPU/gfx1250_dasm_vop3_from_vop1.txt
M llvm/test/MC/Disassembler/AMDGPU/gfx1250_dasm_vop3_from_vop1_dpp16.txt
M llvm/test/MC/Disassembler/AMDGPU/gfx1250_dasm_vop3_from_vop1_dpp8.txt
M llvm/test/MC/Hexagon/two_ext.s
M llvm/test/MC/RISCV/Relocations/mc-dump.s
M llvm/test/MC/X86/verify-callgraph-section.s
M llvm/test/Transforms/DeadStoreElimination/zeroed-missing.ll
A llvm/test/Transforms/LoopInterchange/force-interchange.ll
A llvm/test/Transforms/LoopInterchange/fp-reductions.ll
M llvm/test/Transforms/LoopInterchange/reductions-non-wrapped-operations.ll
A llvm/test/Transforms/LoopStrengthReduce/X86/lifetime-use.ll
M llvm/test/Transforms/LoopUnroll/AArch64/apple-unrolling.ll
A llvm/test/Transforms/LoopUnroll/partial-unroll-reductions.ll
A llvm/test/Transforms/LoopUnroll/runtime-unroll-reductions.ll
M llvm/test/Transforms/LoopVectorize/AArch64/fmax-without-fast-math-flags.ll
M llvm/test/Transforms/LoopVectorize/AArch64/fmin-without-fast-math-flags.ll
A llvm/test/Transforms/LoopVectorize/AArch64/maxbandwidth-regpressure.ll
M llvm/test/Transforms/LoopVectorize/fmax-without-fast-math-flags-interleave.ll
M llvm/test/Transforms/LoopVectorize/fmax-without-fast-math-flags.ll
M llvm/test/Transforms/LoopVectorize/fmin-without-fast-math-flags.ll
M llvm/test/Transforms/LoopVectorize/minmax_reduction.ll
M llvm/test/Transforms/SLPVectorizer/RISCV/reordered-buildvector-scalars.ll
M llvm/test/Transforms/SLPVectorizer/X86/split-node-reorder-node-with-ops.ll
M llvm/test/Transforms/SimplifyCFG/switch-dup-bbs.ll
M llvm/test/Transforms/SimplifyCFG/switch-range-to-icmp.ll
M llvm/test/tools/llc/new-pm/start-stop.ll
A llvm/test/tools/llvm-objdump/ELF/Hexagon/hexagon-bundles.s
M llvm/test/tools/llvm-profdata/c-general.test
A llvm/test/tools/llvm-profdata/show-hot.proftext
M llvm/tools/llvm-dis/llvm-dis.cpp
M llvm/tools/llvm-mc/Disassembler.cpp
M llvm/tools/llvm-objdump/llvm-objdump.cpp
M llvm/tools/llvm-profdata/llvm-profdata.cpp
M llvm/tools/llvm-readobj/ELFDumper.cpp
M llvm/unittests/ADT/STLForwardCompatTest.cpp
M llvm/unittests/CodeGen/LexicalScopesTest.cpp
M llvm/unittests/IR/DebugInfoTest.cpp
M llvm/unittests/Transforms/Utils/DebugifyTest.cpp
M llvm/unittests/Transforms/Utils/LocalTest.cpp
M llvm/utils/TableGen/Common/CodeGenRegisters.cpp
M llvm/utils/TableGen/Common/CodeGenRegisters.h
M llvm/utils/TableGen/Common/CodeGenSchedule.cpp
M llvm/utils/gn/secondary/libcxx/include/BUILD.gn
M llvm/utils/gn/secondary/llvm/lib/Target/AMDGPU/BUILD.gn
M llvm/utils/gn/secondary/llvm/test/BUILD.gn
A llvm/utils/gn/secondary/llvm/tools/llvm-ir2vec/BUILD.gn
M mlir/docs/Tutorials/transform/Ch2.md
M mlir/include/mlir/Conversion/VectorToXeGPU/VectorToXeGPU.h
M mlir/include/mlir/Dialect/SPIRV/Transforms/Passes.td
M mlir/include/mlir/IR/OpDefinition.h
M mlir/include/mlir/IR/Operation.h
M mlir/include/mlir/IR/OperationSupport.h
M mlir/lib/AsmParser/Parser.cpp
M mlir/lib/Conversion/MemRefToEmitC/MemRefToEmitC.cpp
M mlir/lib/Dialect/Linalg/Transforms/TilingInterfaceImpl.cpp
M mlir/lib/Dialect/SPIRV/Transforms/CMakeLists.txt
A mlir/lib/Dialect/SPIRV/Transforms/ConvertToReplicatedConstantCompositePass.cpp
M mlir/lib/Dialect/Tosa/Transforms/TosaReduceTransposes.cpp
M mlir/test/Conversion/MemRefToEmitC/memref-to-emitc.mlir
A mlir/test/Dialect/SPIRV/Transforms/replicated-const-composites.mlir
M mlir/test/Interfaces/TilingInterface/tile-and-fuse-consumer.mlir
M mlir/unittests/Debug/FileLineColLocBreakpointManagerTest.cpp
M mlir/unittests/IR/OperationSupportTest.cpp
M mlir/unittests/IR/ValueTest.cpp
M mlir/unittests/Transforms/DialectConversion.cpp
M offload/plugins-nextgen/amdgpu/src/rtl.cpp
M offload/plugins-nextgen/common/include/PluginInterface.h
M offload/plugins-nextgen/cuda/src/rtl.cpp
M offload/unittests/OffloadAPI/common/Fixtures.hpp
M offload/unittests/OffloadAPI/event/olWaitEvent.cpp
M openmp/runtime/src/kmp.h
M openmp/runtime/src/kmp_tasking.cpp
M utils/bazel/llvm-project-overlay/libc/BUILD.bazel
Log Message:
-----------
Address review comments.
Created using spr 1.3.6-beta.1
Compare: https://github.com/llvm/llvm-project/compare/0c1ec48e6856...959263125e5d
To unsubscribe from these emails, change your notification settings at https://github.com/llvm/llvm-project/settings/notifications
More information about the All-commits
mailing list