[all-commits] [llvm/llvm-project] aa3978: [mlir][vector][memref] Add `alignment` attribute t...

[tyb0807 via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: aa3978573e15205b43c6a7e3b4a6f940ccded7a2
      https://github.com/llvm/llvm-project/commit/aa3978573e15205b43c6a7e3b4a6f940ccded7a2
  Author: tyb0807 <sontuan.vu119 at gmail.com>
  Date:   2025-07-17 (Thu, 17 Jul 2025)

  Changed paths:
    M mlir/docs/DefiningDialects/Operations.md
    M mlir/include/mlir/Dialect/MemRef/IR/MemRefOps.td
    M mlir/include/mlir/Dialect/Vector/IR/VectorOps.td
    M mlir/include/mlir/IR/CommonAttrConstraints.td
    M mlir/test/Dialect/MemRef/invalid.mlir
    M mlir/test/Dialect/MemRef/ops.mlir
    M mlir/test/Dialect/Vector/invalid.mlir
    M mlir/test/Dialect/Vector/ops.mlir

  Log Message:
  -----------
  [mlir][vector][memref] Add `alignment` attribute to memory access ops (#144344)

Alignment information is important to allow LLVM backends such as AMDGPU
to select wide memory accesses (e.g., dwordx4 or b128). Since this info
is not always inferable, it's better to inform LLVM backends explicitly
about it. Furthermore, alignment is not necessarily a property of the
element type, but of each individual memory access op (we can have
overaligned and underaligned accesses compared to the natural/preferred
alignment of the element type).

This patch introduces `alignment` attribute to memref/vector.load/store
ops.

Follow-up PRs will

1. Propagate the attribute to LLVM/SPIR-V.

2. Introduce `alignment` attribute to other vector memory access ops:
    vector.gather + vector.scatter
    vector.transfer_read + vector.transfer_write
    vector.compressstore + vector.expandload
    vector.maskedload + vector.maskedstore

3. Replace `--convert-vector-to-llvm='use-vector-alignment=1` with a
   simple pass to populate alignment attributes based on the vector
   types.



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