[all-commits] [llvm/llvm-project] ba5f31: [lldb][test] Disable TestChildCountTruncation on W...
Krzysztof Parzyszek via All-commits
all-commits at lists.llvm.org
Thu Jul 17 10:13:09 PDT 2025
Branch: refs/heads/users/boomanaiden154/main.ci-migrate-monolithic-linux-script-to-sccache
Home: https://github.com/llvm/llvm-project
Commit: ba5f31cfaa2452a4a94a482b53d899d6f2ee0e66
https://github.com/llvm/llvm-project/commit/ba5f31cfaa2452a4a94a482b53d899d6f2ee0e66
Author: David Spickett <david.spickett at linaro.org>
Date: 2025-07-17 (Thu, 17 Jul 2025)
Changed paths:
M lldb/test/Shell/Settings/TestChildCountTruncation.test
Log Message:
-----------
[lldb][test] Disable TestChildCountTruncation on Windows
This fails because it tells clang to use DWARF which link.exe
then discards.
The test may not need DWARF, but I'm going to confirm that in
a follow up PR review.
Test added by https://github.com/llvm/llvm-project/pull/149088.
Commit: 9fa3971fac27fbe0a6e3b9745d201c16f5f98bc2
https://github.com/llvm/llvm-project/commit/9fa3971fac27fbe0a6e3b9745d201c16f5f98bc2
Author: Piotr Fusik <p.fusik at samsung.com>
Date: 2025-07-17 (Thu, 17 Jul 2025)
Changed paths:
M llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int.ll
M llvm/test/CodeGen/RISCV/rvv/vminu-sdnode.ll
Log Message:
-----------
[DAGCombiner] Fold vector subtraction if above threshold to `umin` (#148834)
This extends #134235 and #135194 to vectors.
Commit: 8f18dde6c0b38a67ad0f06aab79cdadb78b35d33
https://github.com/llvm/llvm-project/commit/8f18dde6c0b38a67ad0f06aab79cdadb78b35d33
Author: Philip Reames <preames at rivosinc.com>
Date: 2025-07-17 (Thu, 17 Jul 2025)
Changed paths:
M llvm/lib/Target/RISCV/RISCVInterleavedAccess.cpp
Log Message:
-----------
[RISCV][IA] Rearrange code for readability and ease of merge [nfc]
Commit: 46357438baefbdcf630abc5d74565afcbf1c48dd
https://github.com/llvm/llvm-project/commit/46357438baefbdcf630abc5d74565afcbf1c48dd
Author: Florian Hahn <flo at fhahn.com>
Date: 2025-07-17 (Thu, 17 Jul 2025)
Changed paths:
M llvm/include/llvm/Transforms/Utils/ScalarEvolutionExpander.h
M llvm/lib/Transforms/Utils/ScalarEvolutionExpander.cpp
M llvm/test/Transforms/LoopVectorize/reuse-lcssa-phi-scev-expansion.ll
Log Message:
-----------
[SCEV] Try to re-use existing LCSSA phis when expanding SCEVAddRecExpr. (#147214)
If an AddRec is expanded outside a loop with a single exit block, check
if any of the (lcssa) phi nodes in the exit block match the AddRec. If
that's the case, simply use the existing lcssa phi.
This can reduce the number of instruction created for SCEV expansions,
mainly for runtime checks generated by the loop vectorizer.
Compile-time impact should be mostly neutral
https://llvm-compile-time-tracker.com/compare.php?from=48c7a3187f9831304a38df9bdb3b4d5bf6b6b1a2&to=cf9d039a7b0db5d0d912e0e2c01b19c2a653273a&stat=instructions:u
PR: https://github.com/llvm/llvm-project/pull/147214
Commit: 7817163663b3bb662a46a73cf1903ec900ba6146
https://github.com/llvm/llvm-project/commit/7817163663b3bb662a46a73cf1903ec900ba6146
Author: Jeremy Kun <jkun at google.com>
Date: 2025-07-17 (Thu, 17 Jul 2025)
Changed paths:
M mlir/include/mlir/Analysis/Presburger/IntegerRelation.h
M mlir/lib/Analysis/Presburger/IntegerRelation.cpp
M mlir/unittests/Analysis/Presburger/IntegerRelationTest.cpp
Log Message:
-----------
[mlir] [presburger] Add IntegerRelation::rangeProduct (#148092)
This is intended to match `isl::map`'s `flat_range_product`.
---------
Co-authored-by: Jeremy Kun <j2kun at users.noreply.github.com>
Commit: 4bf82aebc0da985cf6b2e70812714875e8fa78fa
https://github.com/llvm/llvm-project/commit/4bf82aebc0da985cf6b2e70812714875e8fa78fa
Author: David Spickett <david.spickett at linaro.org>
Date: 2025-07-17 (Thu, 17 Jul 2025)
Changed paths:
M lldb/test/Shell/Settings/TestChildCountTruncation.test
Log Message:
-----------
[lldb][test] Fix TestChildCountTruncation on Windows (#149322)
By not forcing the DWARF debug info format. When left as the default,
the tests pass.
Test added by https://github.com/llvm/llvm-project/pull/149088.
Commit: 149aa7679457e4c434374076fa3ad6d02efbe414
https://github.com/llvm/llvm-project/commit/149aa7679457e4c434374076fa3ad6d02efbe414
Author: Baranov Victor <bar.victor.2002 at gmail.com>
Date: 2025-07-17 (Thu, 17 Jul 2025)
Changed paths:
M clang-tools-extra/README.txt
Log Message:
-----------
[clang-tools-extra][NFC] Fix link to code review in README.txt (#148384)
Commit: 84d65e9d19ab577027238d38d053e293ba656e32
https://github.com/llvm/llvm-project/commit/84d65e9d19ab577027238d38d053e293ba656e32
Author: Amr Hesham <amr96 at programmer.net>
Date: 2025-07-17 (Thu, 17 Jul 2025)
Changed paths:
M clang/lib/CIR/CodeGen/CIRGenBuiltin.cpp
M clang/lib/CIR/CodeGen/CIRGenExprComplex.cpp
M clang/lib/CIR/CodeGen/CIRGenValue.h
M clang/test/CIR/CodeGen/complex-builtins.cpp
Log Message:
-----------
[CIR] Upstream builtin_conj for ComplexType (#149170)
This change adds support for builtin_conj for ComplexType
https://github.com/llvm/llvm-project/issues/141365
Commit: a7f595efd840f7ed2210f2703048fad4d0027fac
https://github.com/llvm/llvm-project/commit/a7f595efd840f7ed2210f2703048fad4d0027fac
Author: nvptm <pmathew at nvidia.com>
Date: 2025-07-17 (Thu, 17 Jul 2025)
Changed paths:
M flang/lib/Lower/OpenACC.cpp
M flang/test/Lower/OpenACC/acc-host-data-unwrap-defaultbounds.f90
M flang/test/Lower/OpenACC/acc-host-data.f90
A flang/test/Lower/OpenACC/acc-use-device.f90
Log Message:
-----------
[flang][acc] Create UseDeviceOp for both results of hlfir.declare (#148017)
A sample such as
```
program test
integer :: N = 100
real*8 :: b(-1:N)
!$acc data copy(b)
!$acc host_data use_device(b)
call vadd(b)
!$acc end host_data
!$acc end data
end
```
is lowered to
```
%13:2 = hlfir.declare %11(%12) {uniq_name = "_QFEb"} : (!fir.ref<!fir.array<?xf64>>, !fir.shapeshift<1>) -> (!fir.box<!fir.array<?xf64>>, !fir.ref<!fir.array<?xf64>>)
%14 = acc.copyin var(%13#0 : !fir.box<!fir.array<?xf64>>) -> !fir.box<!fir.array<?xf64>> {dataClause = #acc<data_clause acc_copy>, name = "b"}
acc.data dataOperands(%14 : !fir.box<!fir.array<?xf64>>) {
%15 = acc.use_device var(%13#0 : !fir.box<!fir.array<?xf64>>) -> !fir.box<!fir.array<?xf64>> {name = "b"}
acc.host_data dataOperands(%15 : !fir.box<!fir.array<?xf64>>) {
fir.call @_QPvadd(%13#1) fastmath<contract> : (!fir.ref<!fir.array<?xf64>>) -> ()
acc.terminator
}
acc.terminator
}
acc.copyout accVar(%14 : !fir.box<!fir.array<?xf64>>) to var(%13#0 : !fir.box<!fir.array<?xf64>>) {dataClause = #acc<data_clause acc_copy>, name = "b"}
```
Note that while the use_device clause is applied to %13#0, the argument
passed to vadd is %13#1. To avoid problems later in lowering, this
change additionally applies the use_device clause to %13#1, so that the
resulting MLIR is
```
%13:2 = hlfir.declare %11(%12) {uniq_name = "_QFEb"} : (!fir.ref<!fir.array<?xf64>>, !fir.shapeshift<1>) -> (!fir.box<!fir.array<?xf64>>, !fir.ref<!fir.array<?xf64>>)
%14 = acc.copyin var(%13#0 : !fir.box<!fir.array<?xf64>>) -> !fir.box<!fir.array<?xf64>> {dataClause = #acc<data_clause acc_copy>, name = "b"}
acc.data dataOperands(%14 : !fir.box<!fir.array<?xf64>>) {
%15 = acc.use_device var(%13#0 : !fir.box<!fir.array<?xf64>>) -> !fir.box<!fir.array<?xf64>> {name = "b"}
%16 = acc.use_device varPtr(%13#1 : !fir.ref<!fir.array<?xf64>>) -> !fir.ref<!fir.array<?xf64>> {name = "b"}
acc.host_data dataOperands(%15, %16 : !fir.box<!fir.array<?xf64>>, !fir.ref<!fir.array<?xf64>>) {
fir.call @_QPvadd(%13#1) fastmath<contract> : (!fir.ref<!fir.array<?xf64>>) -> ()
acc.terminator
}
acc.terminator
}
acc.copyout accVar(%14 : !fir.box<!fir.array<?xf64>>) to var(%13#0 : !fir.box<!fir.array<?xf64>>) {dataClause = #acc<data_clause acc_copy>, name = "b"}
```
Commit: 7caf12da0bb09d6b6992bf42afd256d453753dcb
https://github.com/llvm/llvm-project/commit/7caf12da0bb09d6b6992bf42afd256d453753dcb
Author: Jeremy Kun <jkun at google.com>
Date: 2025-07-17 (Thu, 17 Jul 2025)
Changed paths:
M mlir/include/mlir/IR/PatternMatch.h
M mlir/lib/IR/CMakeLists.txt
A mlir/lib/IR/PatternLoggingListener.cpp
M mlir/lib/Rewrite/PatternApplicator.cpp
A mlir/test/IR/test-pattern-logging-listener.mlir
M mlir/test/lit.cfg.py
Log Message:
-----------
[mlir][core] Add an MLIR "pattern catalog" generator (#146228)
This PR adds a feature that attaches a listener to all RewritePatterns that
logs information about the modified operations.
When the MLIR test suite is run, these debug outputs can
be filtered and combined into an index linking operations to the
patterns that insert, modify, or replace them. This index is intended to
be used to create a website that allows one to look up patterns from an
operation name.
The debug logs emitted can be viewed with --debug-only=generate-pattern-catalog,
and the lit config is modified to do this when the env var MLIR_GENERATE_PATTERN_CATALOG is set.
Example usage:
```
mkdir build && cd build
cmake -G Ninja ../llvm \
-DLLVM_ENABLE_PROJECTS="mlir" \
-DLLVM_TARGETS_TO_BUILD="host" \
-DCMAKE_BUILD_TYPE=DEBUG
ninja -j 24 check-mlir
MLIR_GENERATE_PATTERN_CATALOG=1 bin/llvm-lit -j 24 -v -a tools/mlir/test | grep 'pattern-logging-listener' | sed 's/^# | [pattern-logging-listener] //g' | sort | uniq > pattern_catalog.txt
```
Sample pattern catalog output (that fits in a gist):
https://gist.github.com/j2kun/02d1ab8d31c10d71027724984c89905a
---------
Co-authored-by: Jeremy Kun <j2kun at users.noreply.github.com>
Co-authored-by: Mehdi Amini <joker.eph at gmail.com>
Commit: d97c224e8cbba9158ebda6f12f9a06b09534ae29
https://github.com/llvm/llvm-project/commit/d97c224e8cbba9158ebda6f12f9a06b09534ae29
Author: Connector Switch <c8ef at outlook.com>
Date: 2025-07-18 (Fri, 18 Jul 2025)
Changed paths:
M libc/test/src/math/cospif_test.cpp
M libc/test/src/math/sincosf_test.cpp
M libc/test/src/math/sinpif_test.cpp
Log Message:
-----------
[libc][NFC]: Correct some comments about SDCOMP-26094. (#149317)
Commit: 011d38bdac95647a872a5faa339465e26535df35
https://github.com/llvm/llvm-project/commit/011d38bdac95647a872a5faa339465e26535df35
Author: erichkeane <ekeane at nvidia.com>
Date: 2025-07-17 (Thu, 17 Jul 2025)
Changed paths:
M clang/include/clang/Basic/LangOptions.h
M clang/include/clang/Driver/Options.td
M clang/lib/Driver/ToolChains/Clang.cpp
M clang/lib/Frontend/CompilerInvocation.cpp
M clang/lib/Frontend/InitPreprocessor.cpp
M clang/test/Driver/openacc.c
M clang/test/Preprocessor/openacc.c
Log Message:
-----------
[OpenACC] Update OpenACC macro, remove override macro
As we are now Sema-complete for OpenACC 3.4 (and thus have a conforming
implementation, in all modes), we can now set the _OPENACC macro
correctly.
Additionally, we remove the temporary 'override' functionality, which
was intended to allow people to experiment with this. We aren't having a
deprecation period as OpenACC support is still considered experimental.
Commit: a6fb3b3c18fd48a2eaaa8c969edbc013b9276a09
https://github.com/llvm/llvm-project/commit/a6fb3b3c18fd48a2eaaa8c969edbc013b9276a09
Author: Jacob Lalonde <jalalonde at fb.com>
Date: 2025-07-17 (Thu, 17 Jul 2025)
Changed paths:
M lldb/source/Plugins/Process/minidump/MinidumpParser.cpp
M lldb/source/Plugins/Process/minidump/MinidumpParser.h
M lldb/source/Plugins/Process/minidump/ProcessMinidump.cpp
A lldb/test/Shell/Minidump/missing-memory-region.yaml
M lldb/unittests/Process/minidump/MinidumpParserTest.cpp
Log Message:
-----------
[LLDB] Process minidump better error messages (#149206)
Prior, Process Minidump would return
```
Status::FromErrorString("could not parse memory info");
```
For any unsuccessful memory read, with no differentiation between an
error in LLDB and the data simply not being present. This lead to a lot
of user confusion and overall pretty terrible user experience. To fix
this I've refactored the APIs so we can pass an error back in an llvm
expected.
There were also no shell tests for memory read and process Minidump so I
added one.
Commit: e8a891b0f9d2a742ac3904116aaec2c7c9231b24
https://github.com/llvm/llvm-project/commit/e8a891b0f9d2a742ac3904116aaec2c7c9231b24
Author: Jonathan Cohen <joncoh at apple.com>
Date: 2025-07-17 (Thu, 17 Jul 2025)
Changed paths:
M llvm/lib/Target/AArch64/AArch64InstrInfo.cpp
M llvm/lib/Target/AArch64/AArch64InstrInfo.h
A llvm/test/CodeGen/AArch64/aarch64-combine-gather-lanes.mir
M llvm/test/CodeGen/AArch64/complex-deinterleaving-uniform-cases.ll
M llvm/test/CodeGen/AArch64/concat-vector.ll
M llvm/test/CodeGen/AArch64/fp-maximumnum-minimumnum.ll
M llvm/test/CodeGen/AArch64/fsh.ll
M llvm/test/CodeGen/AArch64/llvm.frexp.ll
M llvm/test/CodeGen/AArch64/neon-dotreduce.ll
M llvm/test/CodeGen/AArch64/nontemporal.ll
Log Message:
-----------
[AArch64][Machine-Combiner] Split gather patterns into neon regs to multiple vectors (#142941)
This changes optimizes gather-like sequences, where we load values
separately into lanes of a neon vector. Since each load has serial
dependency, when performing multiple i32 loads into a 128 bit vector for example, it
is more profitable to load into separate vector registers and zip them.
rdar://151851094
Commit: 661cbd5a5254de22ba87a49e89f54b30e2874fb3
https://github.com/llvm/llvm-project/commit/661cbd5a5254de22ba87a49e89f54b30e2874fb3
Author: Krzysztof Parzyszek <Krzysztof.Parzyszek at amd.com>
Date: 2025-07-17 (Thu, 17 Jul 2025)
Changed paths:
M llvm/test/TableGen/directive1.td
M llvm/test/TableGen/directive2.td
M llvm/unittests/Frontend/OpenMPDirectiveNameParserTest.cpp
M llvm/utils/TableGen/Basic/DirectiveEmitter.cpp
Log Message:
-----------
[utils][TableGen] Make some non-bitmask enums iterable (#148647)
Additionally, add sentinel values <Enum>::First_ and <Enum>::Last_ to
each one of those enums.
This will allow using `enum_seq_inclusive` to generate the list of
enum-typed values of any generated scoped (non-bitmask) enum.
Commit: 0dae924c1f668f74370b642ba91f818b728aca40
https://github.com/llvm/llvm-project/commit/0dae924c1f668f74370b642ba91f818b728aca40
Author: delaram-talaashrafi <dtalaashrafi at nvidia.com>
Date: 2025-07-17 (Thu, 17 Jul 2025)
Changed paths:
M flang/lib/Lower/OpenACC.cpp
M flang/test/Lower/OpenACC/acc-routine.f90
M flang/test/Lower/OpenACC/acc-routine03.f90
M mlir/include/mlir/Dialect/OpenACC/OpenACC.h
M mlir/include/mlir/Dialect/OpenACC/OpenACCOps.td
M mlir/lib/Dialect/OpenACC/IR/OpenACC.cpp
M mlir/unittests/Dialect/OpenACC/OpenACCOpsTest.cpp
Log Message:
-----------
[openacc][flang] Support two type bindName representation in acc routine (#149147)
Based on the OpenACC specification — which states that if the bind name
is given as an identifier it should be resolved according to the
compiled language, and if given as a string it should be used unmodified
— we introduce two distinct `bindName` representations for `acc routine`
to handle each case appropriately: one as an array of `SymbolRefAttr`
for identifiers and another as an array of `StringAttr` for strings.
To ensure correct correspondence between bind names and devices, this
patch also introduces two separate sets of device attributes. The
routine operation is extended accordingly, along with the necessary
updates to the OpenACC dialect and its lowering.
Commit: b3a8d0efc907aae8198ff16e5bfb8dc48f08b6ca
https://github.com/llvm/llvm-project/commit/b3a8d0efc907aae8198ff16e5bfb8dc48f08b6ca
Author: Philip Reames <preames at rivosinc.com>
Date: 2025-07-17 (Thu, 17 Jul 2025)
Changed paths:
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-interleaved-access.ll
M llvm/test/CodeGen/RISCV/rvv/vp-vector-interleaved-access.ll
Log Message:
-----------
[RISCV] Add additional coverage for one hot interleave load cases [nfc]
Add coverage for fixed vector vp.load, and the deinterleave intrinsic paths.
Commit: e4a3541ff88af03c01007a94b6b5f5cea95ecf33
https://github.com/llvm/llvm-project/commit/e4a3541ff88af03c01007a94b6b5f5cea95ecf33
Author: Akshay Khadse <akshayskhadse at gmail.com>
Date: 2025-07-17 (Thu, 17 Jul 2025)
Changed paths:
M mlir/lib/Bindings/Python/IRCore.cpp
M mlir/lib/Bindings/Python/IRModule.h
M mlir/lib/Bindings/Python/Pass.cpp
M mlir/python/mlir/_mlir_libs/_mlir/ir.pyi
M mlir/python/mlir/_mlir_libs/_mlir/passmanager.pyi
M mlir/test/python/ir/operation.py
M mlir/test/python/pass_manager.py
Log Message:
-----------
[MLIR][Python] Support eliding large resource strings in PassManager (#149187)
- Introduces a `large_resource_limit` parameter across Python bindings,
enabling the eliding of resource strings exceeding a specified character
limit during IR printing.
- To maintain backward compatibilty, when using `operation.print()` API,
if `large_resource_limit` is None and the `large_elements_limit` is set,
the later will be used to elide the resource string as well. This change
was introduced by https://github.com/llvm/llvm-project/pull/125738.
- For printing using pass manager, the `large_resource_limit` and
`large_elements_limit` are completely independent of each other.
Commit: d35931c49e5b37243ace2b79bec87463772b6c94
https://github.com/llvm/llvm-project/commit/d35931c49e5b37243ace2b79bec87463772b6c94
Author: T0b1-iOS <T0b1-iOS at users.noreply.github.com>
Date: 2025-07-17 (Thu, 17 Jul 2025)
Changed paths:
M clang/lib/CodeGen/Targets/X86.cpp
A clang/test/CodeGen/X86/i128-debuginfo.c
M clang/test/CodeGen/X86/x86_64-arguments.c
M clang/test/CodeGen/alloc-align-attr.c
M clang/test/CodeGen/builtins.c
M clang/test/CodeGen/ext-int-cc.c
M clang/test/CodeGen/extend-arg-64.c
Log Message:
-----------
[Clang][CodeGen][X86] don't coerce int128 into `{i64,i64}` for SysV-like ABIs (#135230)
Currently, clang coerces (u)int128_t to two i64 IR parameters when they
are passed in registers. This leads to broken debug info for them after
applying SROA+InstCombine. SROA generates IR like this
([godbolt](https://godbolt.org/z/YrTa4chfc)):
```llvm
define dso_local { i64, i64 } @add(i64 noundef %a.coerce0, i64 noundef %a.coerce1) {
entry:
%a.sroa.2.0.insert.ext = zext i64 %a.coerce1 to i128
%a.sroa.2.0.insert.shift = shl nuw i128 %a.sroa.2.0.insert.ext, 64
%a.sroa.0.0.insert.ext = zext i64 %a.coerce0 to i128
%a.sroa.0.0.insert.insert = or i128 %a.sroa.2.0.insert.shift, %a.sroa.0.0.insert.ext
#dbg_value(i128 %a.sroa.0.0.insert.insert, !17, !DIExpression(), !18)
// ...
!17 = !DILocalVariable(name: "a", arg: 1, scope: !10, file: !11, line: 1, type: !14)
// ...
```
and InstCombine then removes the `or`, moving it into the
`DIExpression`, and the `shl` at which point the debug info salvaging in
`Transforms/Local` replaces the arguments with `poison` as it does not
allow constants larger than 64 bit in `DIExpression`s.
I'm working under the assumption that there is interest in fixing this.
If not, please tell me.
By not coercing `int128_t`s into `{i64, i64}` but keeping them as
`i128`, the debug info stays intact and SelectionDAG then generates two
`DW_OP_LLVM_fragment` expressions for the two corresponding argument
registers.
Given that the ABI code for x64 seems to not coerce the argument when it
is passed on the stack, it should not lead to any problems keeping it as
an `i128` when it is passed in registers.
Alternatively, this could be fixed by checking if a constant value fits
in 64 bits in the debug info salvaging code and then extending the value
on the expression stack to the necessary width. This fixes InstCombine
breaking the debug info but then SelectionDAG removes the expression and
that seems significantly more complex to debug.
Another fix may be to generate `DW_OP_LLVM_fragment` expressions when
removing the `or` as it gets marked as disjoint by InstCombine. However,
I don't know if the KnownBits information is still available at the time
the `or` gets removed and it would probably require refactoring of the
debug info salvaging code as that currently only seems to replace single
expressions and is not designed to support generating new debug records.
Converting `(u)int128_t` arguments to `i128` in the IR seems like the
simpler solution, if it doesn't cause any ABI issues.
Commit: ff5784bb9094f6035851dc7abc4a5760fdc21e45
https://github.com/llvm/llvm-project/commit/ff5784bb9094f6035851dc7abc4a5760fdc21e45
Author: Krzysztof Parzyszek <Krzysztof.Parzyszek at amd.com>
Date: 2025-07-17 (Thu, 17 Jul 2025)
Changed paths:
M flang/lib/Lower/OpenMP/OpenMP.cpp
M flang/lib/Lower/OpenMP/Utils.cpp
M flang/lib/Lower/OpenMP/Utils.h
Log Message:
-----------
[flang][OpenMP] Move extractOmpDirective to Utils.cpp, NFC (#148653)
Commit: 0b56fc832b3c44d5cbfe58575bf10e73432ac971
https://github.com/llvm/llvm-project/commit/0b56fc832b3c44d5cbfe58575bf10e73432ac971
Author: Krzysztof Parzyszek <Krzysztof.Parzyszek at amd.com>
Date: 2025-07-17 (Thu, 17 Jul 2025)
Changed paths:
M clang-tools-extra/README.txt
M clang/include/clang/Basic/LangOptions.h
M clang/include/clang/Driver/Options.td
M clang/lib/CIR/CodeGen/CIRGenBuiltin.cpp
M clang/lib/CIR/CodeGen/CIRGenExprComplex.cpp
M clang/lib/CIR/CodeGen/CIRGenValue.h
M clang/lib/CodeGen/Targets/X86.cpp
M clang/lib/Driver/ToolChains/Clang.cpp
M clang/lib/Frontend/CompilerInvocation.cpp
M clang/lib/Frontend/InitPreprocessor.cpp
M clang/test/CIR/CodeGen/complex-builtins.cpp
A clang/test/CodeGen/X86/i128-debuginfo.c
M clang/test/CodeGen/X86/x86_64-arguments.c
M clang/test/CodeGen/alloc-align-attr.c
M clang/test/CodeGen/builtins.c
M clang/test/CodeGen/ext-int-cc.c
M clang/test/CodeGen/extend-arg-64.c
M clang/test/Driver/openacc.c
M clang/test/Preprocessor/openacc.c
M flang/lib/Lower/OpenACC.cpp
M flang/lib/Lower/OpenMP/OpenMP.cpp
M flang/lib/Lower/OpenMP/Utils.cpp
M flang/lib/Lower/OpenMP/Utils.h
M flang/test/Lower/OpenACC/acc-host-data-unwrap-defaultbounds.f90
M flang/test/Lower/OpenACC/acc-host-data.f90
M flang/test/Lower/OpenACC/acc-routine.f90
M flang/test/Lower/OpenACC/acc-routine03.f90
A flang/test/Lower/OpenACC/acc-use-device.f90
M libc/test/src/math/cospif_test.cpp
M libc/test/src/math/sincosf_test.cpp
M libc/test/src/math/sinpif_test.cpp
M lldb/source/Plugins/Process/minidump/MinidumpParser.cpp
M lldb/source/Plugins/Process/minidump/MinidumpParser.h
M lldb/source/Plugins/Process/minidump/ProcessMinidump.cpp
A lldb/test/Shell/Minidump/missing-memory-region.yaml
M lldb/test/Shell/Settings/TestChildCountTruncation.test
M lldb/unittests/Process/minidump/MinidumpParserTest.cpp
M llvm/include/llvm/Transforms/Utils/ScalarEvolutionExpander.h
M llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
M llvm/lib/Target/AArch64/AArch64InstrInfo.cpp
M llvm/lib/Target/AArch64/AArch64InstrInfo.h
M llvm/lib/Target/RISCV/RISCVInterleavedAccess.cpp
M llvm/lib/Transforms/Utils/ScalarEvolutionExpander.cpp
A llvm/test/CodeGen/AArch64/aarch64-combine-gather-lanes.mir
M llvm/test/CodeGen/AArch64/complex-deinterleaving-uniform-cases.ll
M llvm/test/CodeGen/AArch64/concat-vector.ll
M llvm/test/CodeGen/AArch64/fp-maximumnum-minimumnum.ll
M llvm/test/CodeGen/AArch64/fsh.ll
M llvm/test/CodeGen/AArch64/llvm.frexp.ll
M llvm/test/CodeGen/AArch64/neon-dotreduce.ll
M llvm/test/CodeGen/AArch64/nontemporal.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-interleaved-access.ll
M llvm/test/CodeGen/RISCV/rvv/vminu-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vp-vector-interleaved-access.ll
M llvm/test/TableGen/directive1.td
M llvm/test/TableGen/directive2.td
M llvm/test/Transforms/LoopVectorize/reuse-lcssa-phi-scev-expansion.ll
M llvm/unittests/Frontend/OpenMPDirectiveNameParserTest.cpp
M llvm/utils/TableGen/Basic/DirectiveEmitter.cpp
M mlir/include/mlir/Analysis/Presburger/IntegerRelation.h
M mlir/include/mlir/Dialect/OpenACC/OpenACC.h
M mlir/include/mlir/Dialect/OpenACC/OpenACCOps.td
M mlir/include/mlir/IR/PatternMatch.h
M mlir/lib/Analysis/Presburger/IntegerRelation.cpp
M mlir/lib/Bindings/Python/IRCore.cpp
M mlir/lib/Bindings/Python/IRModule.h
M mlir/lib/Bindings/Python/Pass.cpp
M mlir/lib/Dialect/OpenACC/IR/OpenACC.cpp
M mlir/lib/IR/CMakeLists.txt
A mlir/lib/IR/PatternLoggingListener.cpp
M mlir/lib/Rewrite/PatternApplicator.cpp
M mlir/python/mlir/_mlir_libs/_mlir/ir.pyi
M mlir/python/mlir/_mlir_libs/_mlir/passmanager.pyi
A mlir/test/IR/test-pattern-logging-listener.mlir
M mlir/test/lit.cfg.py
M mlir/test/python/ir/operation.py
M mlir/test/python/pass_manager.py
M mlir/unittests/Analysis/Presburger/IntegerRelationTest.cpp
M mlir/unittests/Dialect/OpenACC/OpenACCOpsTest.cpp
Log Message:
-----------
[𝘀𝗽𝗿] changes introduced through rebase
Created using spr 1.3.4
[skip ci]
Compare: https://github.com/llvm/llvm-project/compare/a1179b695282...0b56fc832b3c
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