[all-commits] [llvm/llvm-project] 82404e: [CGData][GMF] Skip merging unnamed functions (#148...
Aiden Grossman via All-commits
all-commits at lists.llvm.org
Thu Jul 17 07:30:08 PDT 2025
Branch: refs/heads/users/boomanaiden154/main.ci-migrate-monolithic-linux-script-to-sccache
Home: https://github.com/llvm/llvm-project
Commit: 82404e3c69168b9fdb779174d3499f5f87f818d2
https://github.com/llvm/llvm-project/commit/82404e3c69168b9fdb779174d3499f5f87f818d2
Author: Kyungwoo Lee <kyulee at meta.com>
Date: 2025-07-16 (Wed, 16 Jul 2025)
Changed paths:
M llvm/lib/CodeGen/GlobalMergeFunctions.cpp
A llvm/test/CodeGen/AArch64/cgdata-no-merge-unnamed.ll
Log Message:
-----------
[CGData][GMF] Skip merging unnamed functions (#148995)
Skip merging unnamed functions to fix an assertion issue, since unnamed
functions would otherwise receive the same merged name --
https://github.com/llvm/llvm-project/blob/main/llvm/lib/CodeGen/GlobalMergeFunctions.cpp#L191
Commit: 64c273a6191bd0036deed7847d39440d36bbc604
https://github.com/llvm/llvm-project/commit/64c273a6191bd0036deed7847d39440d36bbc604
Author: Erick Velez <erickvelez7 at gmail.com>
Date: 2025-07-16 (Wed, 16 Jul 2025)
Changed paths:
M clang-tools-extra/clang-doc/JSONGenerator.cpp
Log Message:
-----------
[clang-doc] fix ASan complaints from passing RepositoryURL as reference (#148923)
Passing RepositoryURL around as an optional reference triggered
stack-use-after-return complaints.
Commit: 78b9128250c9fe5c7f9e460a27cc28c6450fd8fd
https://github.com/llvm/llvm-project/commit/78b9128250c9fe5c7f9e460a27cc28c6450fd8fd
Author: Trevor Gross <tmgross at umich.edu>
Date: 2025-07-16 (Wed, 16 Jul 2025)
Changed paths:
M llvm/docs/LangRef.rst
Log Message:
-----------
[LangRef] Document the difference between `<abi>` and `<pref>` (#147929)
Document how LLVM expects to use `<abi>` and `<pref>`, as well as the
`pref >= abi` requirement.
Commit: 6e0b0ec66ac8de046cc95080166e2012819f7d93
https://github.com/llvm/llvm-project/commit/6e0b0ec66ac8de046cc95080166e2012819f7d93
Author: Peter Klausler <pklausler at nvidia.com>
Date: 2025-07-16 (Wed, 16 Jul 2025)
Changed paths:
M flang/lib/Semantics/tools.cpp
A flang/test/Semantics/bug148559.f90
Log Message:
-----------
[flang] Fix crash in Semantics (#148706)
Allow for renaming in USE association of Cray pointers.
Fixes https://github.com/llvm/llvm-project/issues/148559.
Commit: fc7f9d795d37cd119831e77e475e4690e4120bdb
https://github.com/llvm/llvm-project/commit/fc7f9d795d37cd119831e77e475e4690e4120bdb
Author: Peter Klausler <pklausler at nvidia.com>
Date: 2025-07-16 (Wed, 16 Jul 2025)
Changed paths:
M flang/lib/Semantics/expression.cpp
A flang/test/Semantics/bug148675.f90
Log Message:
-----------
[flang] Better error message for ambiguous ASSIGNMENT(=) (#148720)
When a type-bound generic ASSIGNMENT(=) procedure is ambiguous for a
particular reference, say so, rather than claiming that no specific
procedure matched the types and ranks of the LHS and RHS.
Fixes https://github.com/llvm/llvm-project/issues/148675.
Commit: 52a46dc57f29e87a5a298ce325562fa2e3d057c9
https://github.com/llvm/llvm-project/commit/52a46dc57f29e87a5a298ce325562fa2e3d057c9
Author: Peter Klausler <pklausler at nvidia.com>
Date: 2025-07-16 (Wed, 16 Jul 2025)
Changed paths:
M flang-rt/include/flang-rt/runtime/non-tbp-dio.h
M flang-rt/include/flang-rt/runtime/type-info.h
M flang-rt/lib/runtime/derived.cpp
M flang-rt/lib/runtime/descriptor-io.cpp
M flang-rt/lib/runtime/non-tbp-dio.cpp
M flang-rt/lib/runtime/type-info.cpp
M flang/include/flang/Semantics/runtime-type-info.h
M flang/lib/Lower/IO.cpp
M flang/lib/Semantics/runtime-type-info.cpp
M flang/module/__fortran_type_info.f90
M flang/test/Lower/io-derived-type.f90
M flang/test/Lower/namelist.f90
M flang/test/Lower/volatile-openmp.f90
M flang/test/Semantics/typeinfo01.f90
M flang/test/Semantics/typeinfo02.f90
M flang/test/Semantics/typeinfo09.f90
M flang/test/Semantics/typeinfo13.f90
Log Message:
-----------
[flang] Allow -fdefault-integer-8 with defined I/O (#148927)
Defined I/O subroutines have UNIT= and IOSTAT= dummy arguments that are
required to have type INTEGER with its default kind. When that default
kind is modified via -fdefault-integer-8, calls to defined I/O
subroutines from the runtime don't work.
Add a flag to the two data structures shared between the compiler and
the runtime support library to indicate that a defined I/O subroutine
was compiled under -fdefault-integer-8. This has been done in a
compatible manner, so that existing binaries are compatible with the new
library and new binaries are compatible with the old library, unless of
course -fdefault-integer-8 is used.
Fixes https://github.com/llvm/llvm-project/issues/148638.
Commit: bbcdad1f8eab303a9d56c76a0bced7b17c6d2656
https://github.com/llvm/llvm-project/commit/bbcdad1f8eab303a9d56c76a0bced7b17c6d2656
Author: Peter Klausler <pklausler at nvidia.com>
Date: 2025-07-16 (Wed, 16 Jul 2025)
Changed paths:
M flang-rt/lib/runtime/extensions.cpp
M flang/docs/Intrinsics.md
M flang/include/flang/Runtime/extensions.h
Log Message:
-----------
[flang][runtime] MCLOCK library routine (#148960)
Add MCLOCK as an interface to std::clock().
Commit: 3de11b70620d911613a48d493048cb48bb76ec19
https://github.com/llvm/llvm-project/commit/3de11b70620d911613a48d493048cb48bb76ec19
Author: Peter Klausler <pklausler at nvidia.com>
Date: 2025-07-16 (Wed, 16 Jul 2025)
Changed paths:
M flang/lib/Semantics/check-declarations.cpp
A flang/test/Semantics/bind-c18.f90
Log Message:
-----------
[flang] Catch bad members of BIND(C) COMMON block (#148971)
Variables that can't be BIND(C), like pointers, can't be in a BIND(C)
common block, either.
Fixes https://github.com/llvm/llvm-project/issues/148922.
Commit: 4f8597f071bab5113a945bd653bec84bd820d4a3
https://github.com/llvm/llvm-project/commit/4f8597f071bab5113a945bd653bec84bd820d4a3
Author: Madhur Amilkanthwar <madhura at nvidia.com>
Date: 2025-07-16 (Wed, 16 Jul 2025)
Changed paths:
M llvm/test/Transforms/LoopInterchange/reductions-non-wrapped-operations.ll
Log Message:
-----------
[LoopInterchange] Add test for floating point math flags (#149090)
Adding a test where both `ninf` and `reassoc` flags are present on the
instruction. We don't know yet if it is legal to interchange. Prima
facie, it does not look like it should be legal but more analysis is
needed.
Commit: e8dc96d9de14c4b2317b11b8bc6e9310113697b3
https://github.com/llvm/llvm-project/commit/e8dc96d9de14c4b2317b11b8bc6e9310113697b3
Author: Jonas Devlieghere <jonas at devlieghere.com>
Date: 2025-07-16 (Wed, 16 Jul 2025)
Changed paths:
M lldb/docs/use/mcp.md
Log Message:
-----------
[lldb] Document MCP tools & resources (#148708)
Add documentation for the tools and resources exposed by LLDB's MCP
server.
Commit: b470ac419d7e8eec6c8a27539096e38a1751ee12
https://github.com/llvm/llvm-project/commit/b470ac419d7e8eec6c8a27539096e38a1751ee12
Author: Jeremy Morse <jeremy.morse at sony.com>
Date: 2025-07-16 (Wed, 16 Jul 2025)
Changed paths:
M llvm/lib/IR/Verifier.cpp
Log Message:
-----------
[DebugInfo] Delete debug-intrinsic verifier checks (#149066)
We no longer produce debug-intrinsics, and whenever they're spotted in
bitcode or textual IR they get autoupgraded. We could quite reasonably
reject them out of hand as a construct that shouldn't be present.
However, the DXIL folks are likely to be converting records back to
intrinsics for years to come, and there's no need to make that an error.
There's no value in verifying them IMO.
Commit: 6f660e269242d51a8d36a9a1f98a2244e8311a1a
https://github.com/llvm/llvm-project/commit/6f660e269242d51a8d36a9a1f98a2244e8311a1a
Author: Daniel Paoliello <danpao at microsoft.com>
Date: 2025-07-16 (Wed, 16 Jul 2025)
Changed paths:
M third-party/benchmark/src/sysinfo.cc
Log Message:
-----------
Fix MSVC warning in benchmark (#147357)
Building LLVM with MSVC is raising the following warning:
```
llvm\third-party\benchmark\src\sysinfo.cc(375): warning C4062: enumerator 'CacheUnknown' in switch of enum '_PROCESSOR_CACHE_TYPE' is not handled
```
This change resolves the warning by moving the `Unknown` type into a
case block for `CacheUnknown`.
Not sure how this code flows back into the original source.
Commit: 8519143a9fd368e7cfcf61582683c4e48e7d67d0
https://github.com/llvm/llvm-project/commit/8519143a9fd368e7cfcf61582683c4e48e7d67d0
Author: Sirui Mu <msrlancern at gmail.com>
Date: 2025-07-17 (Thu, 17 Jul 2025)
Changed paths:
M clang/include/clang/CIR/Dialect/IR/CIROps.td
M clang/include/clang/CIR/MissingFeatures.h
M clang/lib/CIR/CodeGen/CIRGenBuiltin.cpp
M clang/lib/CIR/CodeGen/CIRGenFunction.h
M clang/lib/CIR/Lowering/DirectToLLVM/LowerToLLVM.cpp
M clang/lib/CIR/Lowering/DirectToLLVM/LowerToLLVM.h
M clang/test/CIR/CodeGen/builtin_bit.cpp
Log Message:
-----------
[CIR] Add rotate operation (#148426)
This patch adds `cir.rotate` operation for the `__builtin_rotateleft`
and `__builtin_rotateright` families of builtin calls.
Commit: 97922a7d401a4bbbc74013d92f98119e5bdfaebd
https://github.com/llvm/llvm-project/commit/97922a7d401a4bbbc74013d92f98119e5bdfaebd
Author: David Spickett <david.spickett at linaro.org>
Date: 2025-07-16 (Wed, 16 Jul 2025)
Changed paths:
M lldb/docs/resources/build.rst
Log Message:
-----------
[lldb][docs] Add CAMKE_BUILD_TYPE to standlone build instructions
The first stage requires it, the second appears to default to
debug mode, which works but it's better we advise release mode
to match.
Commit: 9f364fe9c446d498f46efff327871dc62db8212f
https://github.com/llvm/llvm-project/commit/9f364fe9c446d498f46efff327871dc62db8212f
Author: David Spickett <david.spickett at linaro.org>
Date: 2025-07-16 (Wed, 16 Jul 2025)
Changed paths:
M lldb/docs/resources/qemu-testing.rst
Log Message:
-----------
[lldb][docs] Add section on testing with QEMU user (#149057)
This is not recommended to basically anyone but on occasion it's useful
and could be used for testing with other simulator programs for example
bare metal simulators.
It is not something we do officially support or make any quality
guarantees for.
Adding this is also an excuse to document the limitations and make the
time spent setting up system mode look more worthwhile and might be good
to cite in future discussions about testing in simulation.
Commit: bd6c16c6cfe28105d992fa997dce6e18ea86a5a4
https://github.com/llvm/llvm-project/commit/bd6c16c6cfe28105d992fa997dce6e18ea86a5a4
Author: Ellis Hoag <ellis.sparky.hoag at gmail.com>
Date: 2025-07-16 (Wed, 16 Jul 2025)
Changed paths:
M llvm/lib/Target/AArch64/AArch64InstrInfo.cpp
M llvm/test/CodeGen/AArch64/machine-outliner-safe-range-in-middle.mir
Log Message:
-----------
[MachineOutliner] Avoid ranges that cross bundle boundary (#148977)
We found some code that was hitting this assert because
`getOutlinableRanges()` was trying to create a range that crossed a
bundle boundary.
https://github.com/llvm/llvm-project/blob/ae3bba4d15a10646ea91c6c0795633b82939857b/llvm/include/llvm/CodeGen/MachineInstrBundleIterator.h#L133-L135
Avoid creating those ranges and add a test that hit the assert.
Commit: 8349bbd0b98c84836d55593c7eb035c2b0f4e87a
https://github.com/llvm/llvm-project/commit/8349bbd0b98c84836d55593c7eb035c2b0f4e87a
Author: Valentin Clement (バレンタイン クレメン) <clementval at gmail.com>
Date: 2025-07-16 (Wed, 16 Jul 2025)
Changed paths:
M flang/lib/Lower/ConvertVariable.cpp
Log Message:
-----------
[flang][cuda] Exit early when there is no device components (#149005)
- Exit early when there is no device components
- Make the retrieval of the record type more robust
Commit: 0f0305021c6e880f8787b9be6606c27e1a0641ed
https://github.com/llvm/llvm-project/commit/0f0305021c6e880f8787b9be6606c27e1a0641ed
Author: Udit Kumar Agarwal <udit.agarwal at intel.com>
Date: 2025-07-16 (Wed, 16 Jul 2025)
Changed paths:
M .github/workflows/email-check.yaml
Log Message:
-----------
[CI] Make email check workflow fail when author's email is private in Github UI (#148694)
**Problem**
Currently, the email check workflow uses `git` to see email used for the
last commit but the email address used when merging is actually governed
by GitHub settings not what's stored in `git`. Due to this, the email
check workflow passes even when the author's email is private in Github.
We saw several such cases in our fork of llvm. See
https://github.com/intel/llvm/issues/17675
**Solution**
Try to find user's email using GH's GraphQL APIs. User's email will be
null if it's hidden in the profile.
---------
Signed-off-by: Agarwal, Udit <udit.agarwal at intel.com>
Commit: 8d21025c3aeb1c98caef08f8446ec138c62288d1
https://github.com/llvm/llvm-project/commit/8d21025c3aeb1c98caef08f8446ec138c62288d1
Author: Brad Richardson <everythingfunctional at protonmail.com>
Date: 2025-07-16 (Wed, 16 Jul 2025)
Changed paths:
A flang/docs/ParallelMultiImageFortranRuntime.md
M flang/docs/index.md
Log Message:
-----------
[flang] Parallel runtime library design doc (PRIF) (#76088)
The Parallel Runtime Interface for Fortran (PRIF) specifies the interface design for
supporting Fortran's multi-image parallel features in flang.
---------
Co-authored-by: Katherine Rasmussen <krasmussen at lbl.gov>
Co-authored-by: Damian Rouson <rouson at lbl.gov>
Co-authored-by: Dan Bonachea <dobonachea at lbl.gov>
Commit: fdec9fd4f81fd336d6d5d50bbd48cd0e095f46b9
https://github.com/llvm/llvm-project/commit/fdec9fd4f81fd336d6d5d50bbd48cd0e095f46b9
Author: duhbbx <duhbbx at gmail.com>
Date: 2025-07-16 (Wed, 16 Jul 2025)
Changed paths:
M clang/include/clang/Basic/DiagnosticSemaKinds.td
M clang/test/CXX/drs/cwg8xx.cpp
M clang/test/CXX/module/dcl.dcl/dcl.module/dcl.module.interface/p1.cppm
M clang/test/CXX/module/module.interface/p1.cpp
M clang/test/Modules/cxx20-10-2-ex1.cpp
M clang/test/Modules/cxx20-export-import.cpp
M clang/test/Modules/cxx20-import-diagnostics-a.cpp
M clang/test/Modules/export-in-non-modules.cpp
Log Message:
-----------
[Clang] Fix export declaration diagnostic message (#149059)
Change the error message from "export declaration can only be used
within a module purview" to "export declaration can only be used within
a module interface" to be technically accurate.
The previous message was misleading because export declarations are
actually within a module purview when used in module implementation
units, but they are only allowed in module interface units.
This addresses the issue pointed out in GitHub issue #149008 where
Bigcheese noted that the diagnostic wording was incorrect.
Fixes #149008
Commit: bd0f9dd86b16660debca39ce76abdd9da1c157a3
https://github.com/llvm/llvm-project/commit/bd0f9dd86b16660debca39ce76abdd9da1c157a3
Author: Amr Hesham <amr96 at programmer.net>
Date: 2025-07-16 (Wed, 16 Jul 2025)
Changed paths:
M clang/include/clang/CIR/Dialect/Builder/CIRBaseBuilder.h
M clang/lib/CIR/CodeGen/CIRGenBuilder.h
M clang/lib/CIR/CodeGen/CIRGenExprComplex.cpp
M clang/lib/CIR/Dialect/Transforms/LoweringPrepare.cpp
A clang/test/CIR/CodeGen/complex-unary.cpp
Log Message:
-----------
[CIR] Upstream unary not for ComplexType (#148857)
Upstream unary not for ComplexType
https://github.com/llvm/llvm-project/issues/141365
Commit: 55b417a75fb4cbd13066510cba13d1c214095eab
https://github.com/llvm/llvm-project/commit/55b417a75fb4cbd13066510cba13d1c214095eab
Author: Ross Brunton <ross at codeplay.com>
Date: 2025-07-16 (Wed, 16 Jul 2025)
Changed paths:
M offload/liboffload/src/OffloadImpl.cpp
M offload/unittests/OffloadAPI/symbol/olGetSymbol.cpp
Log Message:
-----------
[Offload] Cache symbols in program (#148209)
When creating a new symbol, check that it already exists. If it does,
return that pointer rather than building a new symbol structure.
Commit: 037d34815efc6b2c0b3f9f4d19945e49aac831d1
https://github.com/llvm/llvm-project/commit/037d34815efc6b2c0b3f9f4d19945e49aac831d1
Author: sribee8 <sriya.pratipati at gmail.com>
Date: 2025-07-16 (Wed, 16 Jul 2025)
Changed paths:
M libc/fuzzing/math/acos_fuzz.cpp
M libc/fuzzing/math/asin_fuzz.cpp
M libc/fuzzing/math/cos_fuzz.cpp
M libc/fuzzing/math/log10_fuzz.cpp
M libc/fuzzing/math/log1p_fuzz.cpp
M libc/fuzzing/math/log2_fuzz.cpp
M libc/fuzzing/math/log_fuzz.cpp
M libc/fuzzing/math/sin_fuzz.cpp
M libc/fuzzing/math/sincos_fuzz.cpp
M libc/fuzzing/math/sqrt_fuzz.cpp
M libc/fuzzing/math/tan_fuzz.cpp
Log Message:
-----------
[libc] Updated fuzz tests for trig functions (#148891)
Fuzz tests were set up incorrectly so updated trig functions to match
the correct format.
---------
Co-authored-by: Sriya Pratipati <sriyap at google.com>
Commit: ba271cc07334c74df55741701e5b22032c0cddbb
https://github.com/llvm/llvm-project/commit/ba271cc07334c74df55741701e5b22032c0cddbb
Author: Jun Wang <jwang86 at yahoo.com>
Date: 2025-07-16 (Wed, 16 Jul 2025)
Changed paths:
M llvm/lib/Target/AMDGPU/SIInstructions.td
M llvm/lib/Target/AMDGPU/VOP3Instructions.td
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-bswap.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fshr.mir
M llvm/test/CodeGen/AMDGPU/branch-folding-implicit-def-subreg.ll
M llvm/test/MC/AMDGPU/gfx10_asm_vop3.s
M llvm/test/MC/AMDGPU/gfx7_err_pos.s
M llvm/test/MC/AMDGPU/gfx8_err_pos.s
M llvm/test/MC/AMDGPU/gfx9_asm_vop3_e64.s
M llvm/test/MC/Disassembler/AMDGPU/gfx10_vop3.txt
M llvm/test/MC/Disassembler/AMDGPU/gfx9_vop3.txt
Log Message:
-----------
Revert "[AMDGPU][MC] Allow op_sel in v_alignbit_b32 etc in GFX9 and GFX10 (#142188) (#149138)
This reverts commit ce7851f6b7d59e50f92cb4e8dbfd801576c8b641.
The intrinsic llvm.amdgcn.alignbyte was not properly handled for gfx10.
Commit: 560e7df6893495fabe91bc921f9cc0e28a25eb73
https://github.com/llvm/llvm-project/commit/560e7df6893495fabe91bc921f9cc0e28a25eb73
Author: Changpeng Fang <changpeng.fang at amd.com>
Date: 2025-07-16 (Wed, 16 Jul 2025)
Changed paths:
M llvm/lib/Target/AMDGPU/GCNHazardRecognizer.cpp
M llvm/lib/Target/AMDGPU/GCNHazardRecognizer.h
M llvm/test/CodeGen/AMDGPU/llvm.sqrt.bf16.ll
A llvm/test/CodeGen/AMDGPU/trans-coexecution-hazard.mir
Log Message:
-----------
AMDGPU: Handle the co-execution hazards for TRANS for gfx1250 (#149024)
For the co-execution of the TRANS ops, the requirement is: 1 independent
op or V_NOP (since TRANS takes 2 cycles) after the trans op before its
sources can be overwritten or the output of the trans op can be used.
Commit: 22994edb5fd71198c48670255c979fcc962930a1
https://github.com/llvm/llvm-project/commit/22994edb5fd71198c48670255c979fcc962930a1
Author: Erich Keane <ekeane at nvidia.com>
Date: 2025-07-16 (Wed, 16 Jul 2025)
Changed paths:
M clang/include/clang/Basic/DiagnosticSemaKinds.td
M clang/lib/Sema/SemaOpenACC.cpp
A clang/test/SemaOpenACC/private_firstprivate_reduction_required_ops.cpp
Log Message:
-----------
[OpenACC][Sema] Implement warning for non-effective 'private' (#149004)
A 'private' variable reference needs to have a default constructor and a
destructor, else we cannot properly emit them in codegen. This patch
adds a warning-as-default-error to diagnose this.
We'll have to do something similar for firstprivate/reduction, however
it isn't clear whether we could skip the check for default-constructor
for those two (they still need a destructor!). Depending on how we
intend to create them (and we probably have to figure this out?), we
could either require JUST a copy-constructor (then make the init section
just the alloca, and the copy-ctor be the 'copy' section), OR they
require a default-constructor + copy-assignment.
Commit: 056f0a10b320fc2fd75f46aa67d68708303d89ad
https://github.com/llvm/llvm-project/commit/056f0a10b320fc2fd75f46aa67d68708303d89ad
Author: raoanag <127366241+raoanag at users.noreply.github.com>
Date: 2025-07-16 (Wed, 16 Jul 2025)
Changed paths:
M clang/include/clang/Basic/BuiltinsSPIRVVK.td
M clang/lib/CodeGen/TargetBuiltins/SPIR.cpp
M clang/lib/Headers/hlsl/hlsl_intrinsic_helpers.h
M clang/lib/Headers/hlsl/hlsl_intrinsics.h
M clang/lib/Sema/SemaSPIRV.cpp
A clang/test/CodeGenHLSL/builtins/refract.hlsl
A clang/test/CodeGenSPIRV/Builtins/refract.c
A clang/test/SemaHLSL/BuiltIns/refract-errors.hlsl
A clang/test/SemaSPIRV/BuiltIns/refract-errors.c
M llvm/include/llvm/IR/IntrinsicsSPIRV.td
M llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp
A llvm/test/CodeGen/SPIRV/hlsl-intrinsics/refract.ll
A llvm/test/CodeGen/SPIRV/opencl/refract-error.ll
Log Message:
-----------
[HLSL][DXIL] Implement `refract` intrinsic (#147342)
- [x] Implement refract using HLSL source in hlsl_intrinsics.h
- [x] Implement the refract SPIR-V target built-in in
clang/include/clang/Basic/BuiltinsSPIRV.td
- [x] Add sema checks for refract to CheckSPIRVBuiltinFunctionCall in
clang/lib/Sema/SemaSPIRV.cpp
- [x] Add codegen for spv refract to EmitSPIRVBuiltinExpr in
CGBuiltin.cpp
- [x] Add codegen tests to clang/test/CodeGenHLSL/builtins/refract.hlsl
- [x] Add spv codegen test to clang/test/CodeGenSPIRV/Builtins/refract.c
- [x] Add sema tests to clang/test/SemaHLSL/BuiltIns/refract-errors.hlsl
- [x] Add spv sema tests to
clang/test/SemaSPIRV/BuiltIns/refract-errors.c
- [x] Create the int_spv_refract intrinsic in IntrinsicsSPIRV.td
- [x] In SPIRVInstructionSelector.cpp create the refract lowering and
map it to int_spv_refract in SPIRVInstructionSelector::selectIntrinsic.
- [x] Create SPIR-V backend test case in
llvm/test/CodeGen/SPIRV/hlsl-intrinsics/refract.ll
- [x] Check for what OpenCL support is needed.
Resolves https://github.com/llvm/llvm-project/issues/99153
Commit: 82451d0b1341a9b6c01eaa5d27088ff9f3287853
https://github.com/llvm/llvm-project/commit/82451d0b1341a9b6c01eaa5d27088ff9f3287853
Author: sribee8 <sriya.pratipati at gmail.com>
Date: 2025-07-16 (Wed, 16 Jul 2025)
Changed paths:
M libc/fuzzing/math/exp10_fuzz.cpp
M libc/fuzzing/math/exp2_fuzz.cpp
M libc/fuzzing/math/exp_fuzz.cpp
M libc/fuzzing/math/expm1_fuzz.cpp
Log Message:
-----------
[libc] Updated exp fuzz tests (#148912)
Fuzz tests were previously in the wrong format, updated them to correct
format.
---------
Co-authored-by: Sriya Pratipati <sriyap at google.com>
Commit: c4d4e761ef27d6dd27323cf3efa506db5e9e3457
https://github.com/llvm/llvm-project/commit/c4d4e761ef27d6dd27323cf3efa506db5e9e3457
Author: Mikhail R. Gadelha <mikhail at igalia.com>
Date: 2025-07-16 (Wed, 16 Jul 2025)
Changed paths:
M llvm/lib/Target/RISCV/RISCVSchedSpacemitX60.td
M llvm/test/CodeGen/RISCV/rvv/vxrm-insert-out-of-loop.ll
M llvm/test/tools/llvm-mca/RISCV/SpacemitX60/atomic.s
M llvm/test/tools/llvm-mca/RISCV/SpacemitX60/floating-point.s
M llvm/test/tools/llvm-mca/RISCV/SpacemitX60/integer.s
A llvm/test/tools/llvm-mca/RISCV/SpacemitX60/rvv-arithmetic.s
A llvm/test/tools/llvm-mca/RISCV/SpacemitX60/rvv-bitwise.s
A llvm/test/tools/llvm-mca/RISCV/SpacemitX60/rvv-comparison.s
A llvm/test/tools/llvm-mca/RISCV/SpacemitX60/rvv-conversion.s
A llvm/test/tools/llvm-mca/RISCV/SpacemitX60/rvv-fma.s
A llvm/test/tools/llvm-mca/RISCV/SpacemitX60/rvv-fp.s
A llvm/test/tools/llvm-mca/RISCV/SpacemitX60/rvv-mask.s
A llvm/test/tools/llvm-mca/RISCV/SpacemitX60/rvv-minmax.s
A llvm/test/tools/llvm-mca/RISCV/SpacemitX60/rvv-mul-div.s
A llvm/test/tools/llvm-mca/RISCV/SpacemitX60/rvv-permutation.s
A llvm/test/tools/llvm-mca/RISCV/SpacemitX60/rvv-reduction.s
Log Message:
-----------
[RISCV] Pre-commit RVV instructions to the x60 scheduling model and tests
Commit: bcee18a2e268dd106e4b3c2a1d083a4da21f4f23
https://github.com/llvm/llvm-project/commit/bcee18a2e268dd106e4b3c2a1d083a4da21f4f23
Author: Slava Zakharin <szakharin at nvidia.com>
Date: 2025-07-16 (Wed, 16 Jul 2025)
Changed paths:
M flang/lib/Optimizer/CodeGen/LowerRepackArrays.cpp
M flang/test/Transforms/lower-repack-arrays.fir
Log Message:
-----------
[flang] Handle SEQUENCE derived types for array repacking. (#148777)
It is possible that a non-polymorphic dummy argument
has a dynamic type that does not match its static type
in a valid Fortran program, e.g. when the actual and
the dummy arguments have different compatible derived
SEQUENCE types:
module mod
type t
sequence
integer x
end type
contains
subroutine test(x)
type t
sequence
integer x
end type
type(t) :: x(:)
end subroutine
end module
'test' may be called with an actual argument of type 'mod::t',
which is the dynamic type of 'x' on entry to 'test'.
If we create the repacking temporary based on the static type of 'x'
('test::t'), then the runtime will report the types mismatch
as an error. Thus, we have to create the temporary using
the dynamic type of 'x'. The fact that the dummy's type
has SEQUENCE or BIND attribute is not easily computable
at this stage, so we use the dynamic type for all derived
type cases. As long as this is done only when the repacking
actually happens, the overhead should not be noticeable.
Commit: fb3972dd06cbc1b0a5305f81b0c2d74e44dbea41
https://github.com/llvm/llvm-project/commit/fb3972dd06cbc1b0a5305f81b0c2d74e44dbea41
Author: Daniel Bertalan <dani at danielbertalan.dev>
Date: 2025-07-16 (Wed, 16 Jul 2025)
Changed paths:
M lld/MachO/Arch/ARM64.cpp
M lld/MachO/CMakeLists.txt
A lld/MachO/LinkerOptimizationHints.cpp
A lld/MachO/LinkerOptimizationHints.h
M lld/MachO/Target.h
M lld/MachO/Writer.cpp
M llvm/utils/gn/secondary/lld/MachO/BUILD.gn
Log Message:
-----------
[lld-macho] Move Linker Optimization Hints pass to a separate file
Moving it away from the arm64 `TargetInfo` class will let us enable it
more easily for arm64_32 and the soon-to-be-added arm64e target as well.
This is the NFC part of #148964
Commit: c372a2cd0a1e4502f35bf8ebfc0a5d682223249e
https://github.com/llvm/llvm-project/commit/c372a2cd0a1e4502f35bf8ebfc0a5d682223249e
Author: Daniel Paoliello <danpao at microsoft.com>
Date: 2025-07-16 (Wed, 16 Jul 2025)
Changed paths:
M third-party/benchmark/src/sysinfo.cc
Log Message:
-----------
Use default instead of a specific case to fix the MSVC warning in sysinfo.cc (#149159)
#147357 attempted to fix an MSVC in sysinfo.cc by adding a `case` block
for a missing enum value.
However, this resulted in [CI
failures](https://github.com/llvm/llvm-project/pull/147357#issuecomment-3079709852):
```
4.170 [148/4/9] Building CXX object third-party/benchmark/src/CMakeFiles/benchmark.dir/sysinfo.cc.obj
FAILED: third-party/benchmark/src/CMakeFiles/benchmark.dir/sysinfo.cc.obj
C:\Users\tcwg\scoop\shims\ccache.exe C:\Users\tcwg\scoop\apps\llvm-arm64\current\bin\clang-cl.exe /nologo -TP -DBENCHMARK_STATIC_DEFINE -DEXPERIMENTAL_KEY_INSTRUCTIONS -DHAVE_STD_REGEX -DHAVE_STEADY_CLOCK -DUNICODE -D_CRT_NONSTDC_NO_DEPRECATE -D_CRT_NONSTDC_NO_WARNINGS -D_CRT_SECURE_NO_DEPRECATE -D_CRT_SECURE_NO_WARNINGS -D_GLIBCXX_ASSERTIONS -D_HAS_EXCEPTIONS=0 -D_SCL_SECURE_NO_DEPRECATE -D_SCL_SECURE_NO_WARNINGS -D_UNICODE -D__STDC_CONSTANT_MACROS -D__STDC_FORMAT_MACROS -D__STDC_LIMIT_MACROS -IC:/Users/tcwg/llvm-worker/flang-arm64-windows-msvc/build/third-party/benchmark/src -IC:/Users/tcwg/llvm-worker/flang-arm64-windows-msvc/llvm-project/third-party/benchmark/src -IC:/Users/tcwg/llvm-worker/flang-arm64-windows-msvc/build/include -IC:/Users/tcwg/llvm-worker/flang-arm64-windows-msvc/llvm-project/llvm/include -IC:/Users/tcwg/llvm-worker/flang-arm64-windows-msvc/llvm-project/third-party/benchmark/include /DWIN32 /D_WINDOWS /Zc:inline /Zc:__cplusplus /Oi /Brepro /bigobj /permissive- -Werror=unguarded-availability-new -Wextra -Wno-unused-parameter -Wwrite-strings -Wcast-qual -Wmissing-field-initializers -Wimplicit-fallthrough -Wcovered-switch-default -Wno-noexcept-type -Wnon-virtual-dtor -Wdelete-non-virtual-dtor -Wsuggest-override -Wstring-conversion -Wmisleading-indentation -Wctad-maybe-unsupported /Gw /W4 -EHs- -EHa- /O2 /Ob2 -std:c++14 -MD -UNDEBUG /showIncludes /Fothird-party/benchmark/src/CMakeFiles/benchmark.dir/sysinfo.cc.obj /Fdthird-party\benchmark\src\CMakeFiles\benchmark.dir\benchmark.pdb -c -- C:/Users/tcwg/llvm-worker/flang-arm64-windows-msvc/llvm-project/third-party/benchmark/src/sysinfo.cc
C:/Users/tcwg/llvm-worker/flang-arm64-windows-msvc/llvm-project/third-party/benchmark/src/sysinfo.cc(374,12): error: use of undeclared identifier 'CacheUnknown'
374 | case CacheUnknown:
| ^
1 error generated.
```
The root cause is that the enum being switched on is defined in the
Windows SDK, so depending on which version of the SDK you are using
`CacheUnknown` may or may not be defined.
The correct fix here is to use a `default` block in the switch statement
instead.
Commit: b3c72a97c5ac352b89c12f3cf7c3f223219f91ed
https://github.com/llvm/llvm-project/commit/b3c72a97c5ac352b89c12f3cf7c3f223219f91ed
Author: Andre Kuhlenschmidt <andre.kuhlenschmidt at gmail.com>
Date: 2025-07-16 (Wed, 16 Jul 2025)
Changed paths:
M flang/include/flang/Parser/message.h
M flang/lib/Frontend/FrontendAction.cpp
M flang/lib/Parser/message.cpp
M flang/lib/Semantics/semantics.cpp
A flang/test/Driver/fatal-errors-warnings.f90
Log Message:
-----------
[flang][driver] -Werror promotes warnings to error and interopts with -Wfatal-errors (#148748)
This PR changes how `-Werror` promotes warnings to errors so that it
interoperates with `-Wfatal-error`. It maintains the property that
warnings and other messages promoted to errors are displayed as there
original message.
Commit: 362594a10fa5fd8e5f8d31eb5391370c928b639e
https://github.com/llvm/llvm-project/commit/362594a10fa5fd8e5f8d31eb5391370c928b639e
Author: Jay Foad <jay.foad at amd.com>
Date: 2025-07-16 (Wed, 16 Jul 2025)
Changed paths:
M llvm/utils/TableGen/Common/CodeGenRegisters.cpp
Log Message:
-----------
[TableGen] Remove unnecessary sortAndUniqueRegisters (#149125)
Each of the SRSets is already sorted and unique because it is a filtered
version of RC->getMembers() which is already sorted and unique.
Commit: 43f10639a18b2b8fb0976f3bde84a9d240647915
https://github.com/llvm/llvm-project/commit/43f10639a18b2b8fb0976f3bde84a9d240647915
Author: Daniel Bertalan <dani at danielbertalan.dev>
Date: 2025-07-16 (Wed, 16 Jul 2025)
Changed paths:
M lld/MachO/LinkerOptimizationHints.cpp
M lld/MachO/Writer.cpp
A lld/test/MachO/loh-arm64-32.s
Log Message:
-----------
[lld-macho] Enable Linker Optimization Hints pass for arm64_32 (#148964)
The backend emits `.loh` directives for arm64_32 as well. Our pass
already handles 32-bit pointer loads correctly (there was an extraneous
sanity check for 8-byte pointer sizes, I removed that here), so we can
enable them for all arm64 subtargets, including our upcoming arm64e
support.
Commit: 4355356d96de1e171f7511a6c41d056871dacc68
https://github.com/llvm/llvm-project/commit/4355356d96de1e171f7511a6c41d056871dacc68
Author: Jay Foad <jay.foad at amd.com>
Date: 2025-07-16 (Wed, 16 Jul 2025)
Changed paths:
M llvm/utils/TableGen/Common/CodeGenRegisters.cpp
M llvm/utils/TableGen/Common/CodeGenRegisters.h
M llvm/utils/TableGen/RegisterInfoEmitter.cpp
Log Message:
-----------
[TableGen] Add a bitvector of members of CodeGenRegisterClass (#149122)
This makes CodeGenRegisterClass::contains fast. Use this to simplify
inferMatchingSuperRegClass.
Commit: 3a6ef8b359fc3f2459ef60013b8938ebe847831b
https://github.com/llvm/llvm-project/commit/3a6ef8b359fc3f2459ef60013b8938ebe847831b
Author: Muhammad Bassiouni <60100307+bassiounix at users.noreply.github.com>
Date: 2025-07-16 (Wed, 16 Jul 2025)
Changed paths:
M libc/shared/math.h
A libc/shared/math/exp10.h
M libc/src/__support/FPUtil/PolyEval.h
M libc/src/__support/FPUtil/double_double.h
M libc/src/__support/math/CMakeLists.txt
A libc/src/__support/math/exp10.h
M libc/src/math/generic/CMakeLists.txt
M libc/src/math/generic/exp10.cpp
M utils/bazel/llvm-project-overlay/libc/BUILD.bazel
Log Message:
-----------
[libc][math] Refactor exp10 implementation to header-only in src/__support/math folder. (#148400)
Part of #147386
in preparation for:
https://discourse.llvm.org/t/rfc-make-clang-builtin-math-functions-constexpr-with-llvm-libc-to-support-c-23-constexpr-math-functions/86450
Commit: 94382c8e56e878d1b6a8cf317e3632df5352e23e
https://github.com/llvm/llvm-project/commit/94382c8e56e878d1b6a8cf317e3632df5352e23e
Author: Leonard Chan <leonardchan at google.com>
Date: 2025-07-16 (Wed, 16 Jul 2025)
Changed paths:
M llvm/lib/CodeGen/StackProtector.cpp
A llvm/test/Transforms/StackProtector/cross-dso-cfi-stack-chk-fail.ll
A llvm/test/Transforms/StackProtector/stack-chk-fail-alias.ll
Log Message:
-----------
[llvm][StackProtector] Add noreturn to __stack_chk_fail call (#143976)
This is a reland for 99e53cb4139eda491f97cb33ee42ea424d352200 with the
appropriate test fixes.
It's possible for __stack_chk_fail to be an alias when using CrossDSOCFI
since it will make a jump table entry for this function and replace it
with an alias. StackProtector can crash since it always expects this to
be a regular function. Instead add the noreturn attribute to the call.
Commit: ececa877083fcbe19aa0394b280630b9d807cd6d
https://github.com/llvm/llvm-project/commit/ececa877083fcbe19aa0394b280630b9d807cd6d
Author: Mikhail R. Gadelha <mikhail at igalia.com>
Date: 2025-07-16 (Wed, 16 Jul 2025)
Changed paths:
M llvm/lib/Target/RISCV/RISCVVLOptimizer.cpp
M llvm/test/CodeGen/RISCV/rvv/vl-opt-instrs.ll
M llvm/test/CodeGen/RISCV/rvv/vl-opt-op-info.mir
Log Message:
-----------
[RISCV][VLOPT] Add support for vrgather (#148249)
This PR adds support for the vrgather.vi, vrgather.vx, vrgather.vv,
vrgatherei16.vv instructions in the RISC-V VLOptimizer.
To support vrgatherei16.vv I also needed to add support for it in
getOperandLog2EEW.
Commit: 6824bcfdb4c8315a990f4b5ce2cb9f528281a823
https://github.com/llvm/llvm-project/commit/6824bcfdb4c8315a990f4b5ce2cb9f528281a823
Author: Min-Yih Hsu <min.hsu at sifive.com>
Date: 2025-07-16 (Wed, 16 Jul 2025)
Changed paths:
M llvm/include/llvm/Analysis/VectorUtils.h
M llvm/include/llvm/CodeGen/TargetLowering.h
M llvm/lib/Analysis/VectorUtils.cpp
M llvm/lib/CodeGen/InterleavedAccessPass.cpp
M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
M llvm/lib/Target/AArch64/AArch64ISelLowering.h
M llvm/lib/Target/RISCV/RISCVISelLowering.h
M llvm/lib/Target/RISCV/RISCVInterleavedAccess.cpp
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-deinterleave-load.ll
M llvm/test/CodeGen/RISCV/rvv/vp-vector-interleaved-access.ll
M llvm/test/Transforms/InterleavedAccess/AArch64/fixed-deinterleave-intrinsics.ll
M llvm/test/Transforms/InterleavedAccess/AArch64/scalable-deinterleave-intrinsics.ll
M llvm/test/Transforms/InterleavedAccess/AArch64/sve-deinterleave4.ll
M llvm/test/Transforms/InterleavedAccess/AArch64/sve-interleaved-accesses.ll
Log Message:
-----------
[IA] Relax the requirement of having ExtractValue users on deinterleave intrinsic (#148716)
There are cases where InstCombine / InstSimplify might sink extractvalue
instructions that use a deinterleave intrinsic into successor blocks,
which prevents InterleavedAccess from kicking in because the current
pattern requires deinterleave intrinsic to be used by extractvalue.
However, this requirement is bit too strict while we could have just
replaced the users of deinterleave intrinsic with whatever generated by
the target TLI hooks.
Commit: 8c28f4920dfda2e3d91c58e8eb5b568dd396fa2d
https://github.com/llvm/llvm-project/commit/8c28f4920dfda2e3d91c58e8eb5b568dd396fa2d
Author: Michael Buch <michaelbuch12 at gmail.com>
Date: 2025-07-16 (Wed, 16 Jul 2025)
Changed paths:
M lldb/source/Commands/CommandObjectDWIMPrint.cpp
M lldb/source/Commands/CommandObjectExpression.cpp
A lldb/test/Shell/Settings/TestChildCountTruncation.test
Log Message:
-----------
[lldb] Print children-count warning for dwim-print and expr (#149088)
When dumping variables, LLDB will print a one-time warning about
truncating children (when the children count exceeds the default
`target.max-children-count`). But we only do this for `frame variable`.
So if we use `dwim-print` or `expression`, the output gets truncated but
we don't print a warning. But because we store the fact that we
truncated some output on the `CommandInterpreter`, we fire the warning
next time we use `frame variable`. E.g.,:
```
(lldb) p arr
(int[1000]) {
[0] = -5
[1] = 0
[2] = 0
<-- snipped -->
[253] = 0
[254] = 0
[255] = 0
...
}
(lldb) v someLocal
(int) someLocal = 10
*** Some of the displayed variables have more members than the debugger
will show by default. To show all of them, you can either use the
--show-all-children option to frame variable or raise the limit by
changing the target.max-children-count setting.
```
This patch prints the warning for `dwim-print` and `expression`.
I only added a test for the `target.max-children-count` for now because
it seems the `target.max-children-depth` warning is broken (I can't get
it to fire).
Commit: b9f5b39e04d22e9a6ad451bdc0779bed31015372
https://github.com/llvm/llvm-project/commit/b9f5b39e04d22e9a6ad451bdc0779bed31015372
Author: Jay Foad <jay.foad at amd.com>
Date: 2025-07-16 (Wed, 16 Jul 2025)
Changed paths:
M llvm/lib/TableGen/TGLexer.cpp
Log Message:
-----------
[TableGen] Remove explicit recursion in LexToken (#143697)
When profiling a Release+Asserts build of llvm-tblgen I noticed that it
was recursing hundreds of times to lex a sequence of hundreds of space
characters.
Commit: 7caa0c9a55b33d8d627975e94c3367aa68dc37c7
https://github.com/llvm/llvm-project/commit/7caa0c9a55b33d8d627975e94c3367aa68dc37c7
Author: Udit Kumar Agarwal <udit.agarwal at intel.com>
Date: 2025-07-16 (Wed, 16 Jul 2025)
Changed paths:
M .github/workflows/email-check.yaml
Log Message:
-----------
Revert "[CI] Make email check workflow fail when author's email is private in Github UI" (#149186)
Reverts llvm/llvm-project#148694
The workflow is failing if user's email is not listed publicly on your
GH profile. This is different from not having your email public on
Github (in Github email settings page vs. email field in Github
profile/email settings).
Commit: 1e4e2b332dc08e01498c677a6a375fcbc9d5e9f0
https://github.com/llvm/llvm-project/commit/1e4e2b332dc08e01498c677a6a375fcbc9d5e9f0
Author: Valentin Clement (バレンタイン クレメン) <clementval at gmail.com>
Date: 2025-07-16 (Wed, 16 Jul 2025)
Changed paths:
M flang/lib/Optimizer/Transforms/CUFDeviceGlobal.cpp
M flang/test/Fir/CUDA/cuda-device-global.f90
Log Message:
-----------
[flang][cuda] Import type descriptor in the gpu module when needed (#149157)
Commit: b7f6abdd052412bebfedc9cac26fc58b9edb618d
https://github.com/llvm/llvm-project/commit/b7f6abdd052412bebfedc9cac26fc58b9edb618d
Author: Daniil Fukalov <dfukalov at gmail.com>
Date: 2025-07-16 (Wed, 16 Jul 2025)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp
A llvm/test/CodeGen/AMDGPU/select-cmp-shared-constant-fp.ll
A llvm/test/CodeGen/AMDGPU/select-cmp-shared-constant-int.ll
Log Message:
-----------
[AMDGPU] Try to reuse register with the constant from compare in v_cndmask (#148740)
For some targets, the optimization X == Const ? X : Y -> X == Const ?
Const : Y can cause extra register usage or redundant immediate encoding
for the constant in cndmask generated from the ternary operation.
This patch detects such cases and reuses the register from the compare
instruction that already holds the constant, instead of materializing it
again for cndmask.
The optimization avoids immediates that can be encoded into cndmask
instruction (including +-0.0), as well as !isNormal() constants.
The change is reworked on the base of #131146
---------
Co-authored-by: Copilot <175728472+Copilot at users.noreply.github.com>
Commit: cb6d1bbfcd01866ef7a3027968e6480ef1c2c992
https://github.com/llvm/llvm-project/commit/cb6d1bbfcd01866ef7a3027968e6480ef1c2c992
Author: Guy David <49722543+guy-david at users.noreply.github.com>
Date: 2025-07-17 (Thu, 17 Jul 2025)
Changed paths:
M clang/test/CodeGen/PowerPC/builtins-ppc-fpconstrained.c
A llvm/test/CodeGen/PowerPC/spe-vsx-incompatibility.ll
Log Message:
-----------
[PowerPC] Test SPE incompatibility with VSX (#147184)
PPCSubtarget is not always initialized, depending on which passes are
running, and in our downstream fork, -enable-matrix is the default
configuration (regardless of whether matrix intrinsics are present in
the IR), which triggers a fatal error in builtins-ppc-fpconstrained.c.
Commit: 9912ccb0b4d17a4dd4ef8df718b63e3a907ad7c5
https://github.com/llvm/llvm-project/commit/9912ccb0b4d17a4dd4ef8df718b63e3a907ad7c5
Author: Stanislav Mekhanoshin <Stanislav.Mekhanoshin at amd.com>
Date: 2025-07-16 (Wed, 16 Jul 2025)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPU.td
M llvm/lib/Target/AMDGPU/FLATInstructions.td
M llvm/lib/Target/AMDGPU/GCNSubtarget.h
M llvm/test/MC/AMDGPU/gfx1250_asm_vflat.s
M llvm/test/MC/Disassembler/AMDGPU/gfx1250_dasm_vflat.txt
Log Message:
-----------
[AMDGPU] gfx1250 MC support for FLAT GVS addressing (#149173)
Commit: 703501e66198c6d4be48773b617c784370e23d4a
https://github.com/llvm/llvm-project/commit/703501e66198c6d4be48773b617c784370e23d4a
Author: Stanislav Mekhanoshin <Stanislav.Mekhanoshin at amd.com>
Date: 2025-07-16 (Wed, 16 Jul 2025)
Changed paths:
M llvm/lib/Target/AMDGPU/FLATInstructions.td
M llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
A llvm/test/CodeGen/AMDGPU/flat-saddr-load.ll
Log Message:
-----------
[AMDGPU] Select flat GVS loads on gfx1250 (#149183)
Commit: 038e80cfd37e948d78c70d5a258ffe424a438d51
https://github.com/llvm/llvm-project/commit/038e80cfd37e948d78c70d5a258ffe424a438d51
Author: Ryan Prichard <rprichard at google.com>
Date: 2025-07-16 (Wed, 16 Jul 2025)
Changed paths:
M libcxx/test/std/utilities/meta/meta.unary/meta.unary.comp/is_bounded_array.pass.cpp
M libcxx/test/std/utilities/meta/meta.unary/meta.unary.prop/has_unique_object_representations.compile.pass.cpp
M libcxx/utils/ci/Dockerfile
M libcxx/utils/ci/docker-compose.yml
Log Message:
-----------
[libc++][Android] Update compiler and sysroot (#148998)
* Upgrade from r536225 to r563880.
* Upgrade from ab/12644632 to f8b85cc5262c6e5cbc9a92c1bab2b18b32a4c63f,
the current HEAD commit of
https://android.googlesource.com/platform/prebuilts/ndk/+/refs/heads/mirror-goog-main-ndk
The previous source of sysroots (ci.android.com), deleted its artifacts
after a short period of time, and is currently out-of-date because of
the aosp-main turndown.
Updating the Docker image also fixes two tests.
Commit: 7d2a58e87d7ab5d076adf51705b1b2253cea34bb
https://github.com/llvm/llvm-project/commit/7d2a58e87d7ab5d076adf51705b1b2253cea34bb
Author: Shilei Tian <i at tianshilei.me>
Date: 2025-07-16 (Wed, 16 Jul 2025)
Changed paths:
M clang/include/clang/Basic/BuiltinsAMDGPU.def
M clang/lib/CodeGen/TargetBuiltins/AMDGPU.cpp
M clang/test/CodeGenOpenCL/builtins-amdgcn-gfx1250.cl
M llvm/lib/Target/AMDGPU/VOP1Instructions.td
A llvm/test/CodeGen/AMDGPU/llvm.amdgcn.rsq.bf16.ll
M llvm/test/MC/AMDGPU/gfx1250_asm_vop1-fake16.s
M llvm/test/MC/AMDGPU/gfx1250_asm_vop1.s
M llvm/test/MC/AMDGPU/gfx1250_asm_vop1_dpp16-fake16.s
M llvm/test/MC/AMDGPU/gfx1250_asm_vop1_dpp16.s
M llvm/test/MC/AMDGPU/gfx1250_asm_vop1_dpp8-fake16.s
M llvm/test/MC/AMDGPU/gfx1250_asm_vop1_dpp8.s
M llvm/test/MC/AMDGPU/gfx1250_asm_vop3_from_vop1-fake16.s
M llvm/test/MC/AMDGPU/gfx1250_asm_vop3_from_vop1.s
M llvm/test/MC/AMDGPU/gfx1250_asm_vop3_from_vop1_dpp16-fake16.s
M llvm/test/MC/AMDGPU/gfx1250_asm_vop3_from_vop1_dpp16.s
M llvm/test/MC/AMDGPU/gfx1250_asm_vop3_from_vop1_dpp8-fake16.s
M llvm/test/MC/AMDGPU/gfx1250_asm_vop3_from_vop1_dpp8.s
M llvm/test/MC/Disassembler/AMDGPU/gfx1250_dasm_vop1.txt
M llvm/test/MC/Disassembler/AMDGPU/gfx1250_dasm_vop1_dpp16.txt
M llvm/test/MC/Disassembler/AMDGPU/gfx1250_dasm_vop1_dpp8.txt
M llvm/test/MC/Disassembler/AMDGPU/gfx1250_dasm_vop3_from_vop1.txt
M llvm/test/MC/Disassembler/AMDGPU/gfx1250_dasm_vop3_from_vop1_dpp16.txt
M llvm/test/MC/Disassembler/AMDGPU/gfx1250_dasm_vop3_from_vop1_dpp8.txt
Log Message:
-----------
[AMDGPU] Add support for `v_rsq_bf16` on gfx1250 (#149194)
Co-authored-by: Mekhanoshin, Stanislav <Stanislav.Mekhanoshin at amd.com>
Commit: ad6d5d28215adb3def221517b1490b8df3fd1190
https://github.com/llvm/llvm-project/commit/ad6d5d28215adb3def221517b1490b8df3fd1190
Author: Shilei Tian <i at tianshilei.me>
Date: 2025-07-16 (Wed, 16 Jul 2025)
Changed paths:
M clang/include/clang/Basic/BuiltinsAMDGPU.def
M clang/lib/CodeGen/TargetBuiltins/AMDGPU.cpp
M clang/test/CodeGenOpenCL/builtins-amdgcn-gfx1250.cl
M llvm/lib/Target/AMDGPU/VOP1Instructions.td
A llvm/test/CodeGen/AMDGPU/bf16-math.ll
A llvm/test/CodeGen/AMDGPU/llvm.amdgcn.log.bf16.ll
A llvm/test/CodeGen/AMDGPU/llvm.log2.bf16.ll
M llvm/test/MC/AMDGPU/gfx1250_asm_vop1-fake16.s
M llvm/test/MC/AMDGPU/gfx1250_asm_vop1.s
M llvm/test/MC/AMDGPU/gfx1250_asm_vop1_dpp16-fake16.s
M llvm/test/MC/AMDGPU/gfx1250_asm_vop1_dpp16.s
M llvm/test/MC/AMDGPU/gfx1250_asm_vop1_dpp8-fake16.s
M llvm/test/MC/AMDGPU/gfx1250_asm_vop1_dpp8.s
M llvm/test/MC/AMDGPU/gfx1250_asm_vop3_from_vop1-fake16.s
M llvm/test/MC/AMDGPU/gfx1250_asm_vop3_from_vop1.s
M llvm/test/MC/AMDGPU/gfx1250_asm_vop3_from_vop1_dpp16-fake16.s
M llvm/test/MC/AMDGPU/gfx1250_asm_vop3_from_vop1_dpp16.s
M llvm/test/MC/AMDGPU/gfx1250_asm_vop3_from_vop1_dpp8-fake16.s
M llvm/test/MC/AMDGPU/gfx1250_asm_vop3_from_vop1_dpp8.s
M llvm/test/MC/Disassembler/AMDGPU/gfx1250_dasm_vop1.txt
M llvm/test/MC/Disassembler/AMDGPU/gfx1250_dasm_vop1_dpp16.txt
M llvm/test/MC/Disassembler/AMDGPU/gfx1250_dasm_vop1_dpp8.txt
M llvm/test/MC/Disassembler/AMDGPU/gfx1250_dasm_vop3_from_vop1.txt
M llvm/test/MC/Disassembler/AMDGPU/gfx1250_dasm_vop3_from_vop1_dpp16.txt
M llvm/test/MC/Disassembler/AMDGPU/gfx1250_dasm_vop3_from_vop1_dpp8.txt
Log Message:
-----------
[AMDGPU] Add support for `v_log_bf16` on gfx1250 (#149201)
Co-authored-by: Mekhanoshin, Stanislav <Stanislav.Mekhanoshin at amd.com>
Commit: 0110168f6aa5c8a8d02ffd9e62c7929ce6d24d26
https://github.com/llvm/llvm-project/commit/0110168f6aa5c8a8d02ffd9e62c7929ce6d24d26
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2025-07-17 (Thu, 17 Jul 2025)
Changed paths:
M llvm/include/llvm/IR/RuntimeLibcalls.td
A llvm/test/CodeGen/X86/win32-int-runtime-libcalls.ll
Log Message:
-----------
RuntimeLibcalls: Fix calling conv of win32 div libcalls (#149098)
There's probably an existing test this should be added to,
but our test coverage is really bad that this wasn't caught
by one.
Commit: 7e0fde0c2f6b0b9d727ce9196956b36e91961ac4
https://github.com/llvm/llvm-project/commit/7e0fde0c2f6b0b9d727ce9196956b36e91961ac4
Author: Sirraide <aeternalmail at gmail.com>
Date: 2025-07-16 (Wed, 16 Jul 2025)
Changed paths:
M clang/tools/libclang/libclang.map
Log Message:
-----------
[Clang] Reintroduce obsolete symbols in libclang.map (#149190)
This is a follow-up to #149079. Seems like we forgot about the fact that
the symbols also need to be in `libclang.map`.
Commit: 86c63e6bd66f9db9c7320155da7a2042407b5a1a
https://github.com/llvm/llvm-project/commit/86c63e6bd66f9db9c7320155da7a2042407b5a1a
Author: royitaqi <royitaqi at users.noreply.github.com>
Date: 2025-07-16 (Wed, 16 Jul 2025)
Changed paths:
M lldb/source/Interpreter/CommandInterpreter.cpp
Log Message:
-----------
[lldb] [cosmetic] Update help message of `(lldb) b` (#149114)
`(lldb) b` can be used in two different ways:
1. Running `b` without arguments, it lists all existing breakpoints.
2. Running `b` with arguments, it adds breakpoints.
However, the help message doesn't mention the first use case. This patch
adds help message to mention it.
**Without patch**:
```
(lldb) help b
Set a breakpoint using one of several shorthand formats. Expects 'raw' input (see 'help raw-input'.)
Syntax:
_regexp-break <filename>:<linenum>:<colnum>
main.c:12:21 // Break at line 12 and column 21 of main.c
...
```
**With patch**:
```
(lldb) help b
Set a breakpoint using one of several shorthand formats, or list the
existing breakpoints if no arguments are provided. Expects 'raw' input
(see 'help raw-input'.)
Syntax:
_regexp-break <filename>:<linenum>:<colnum>
main.c:12:21 // Break at line 12 and column 21 of main.c
...
_regexp-break
// List the existing breakpoints
```
Commit: 26b0b279deca7cd660efcae5c17bd27a15ead36d
https://github.com/llvm/llvm-project/commit/26b0b279deca7cd660efcae5c17bd27a15ead36d
Author: Stanislav Mekhanoshin <Stanislav.Mekhanoshin at amd.com>
Date: 2025-07-16 (Wed, 16 Jul 2025)
Changed paths:
M llvm/lib/Target/AMDGPU/FLATInstructions.td
A llvm/test/CodeGen/AMDGPU/flat-saddr-store.ll
Log Message:
-----------
[AMDGPU] Select flat GVS stores on gfx1250 (#149203)
Commit: 81eb7defa23dcf48a8e51391543eb210df232440
https://github.com/llvm/llvm-project/commit/81eb7defa23dcf48a8e51391543eb210df232440
Author: Cristian Assaiante <assaiante at diag.uniroma1.it>
Date: 2025-07-16 (Wed, 16 Jul 2025)
Changed paths:
M clang/test/CodeGen/new-pass-manager-opt-bisect.c
M llvm/include/llvm/IR/OptBisect.h
M llvm/include/llvm/Pass.h
M llvm/lib/IR/OptBisect.cpp
M llvm/lib/IR/Pass.cpp
M llvm/lib/Passes/StandardInstrumentations.cpp
M llvm/test/Other/opt-bisect-new-pass-manager.ll
A llvm/test/Other/opt-disable.ll
Log Message:
-----------
[OptBisect][IR] Adding a new OptPassGate for disabling passes via name (#145059)
This commit adds a new pass gate that allows selective disabling
of one or more passes via the clang command line using the
`-opt-disable` option. Passes to be disabled should be specified as a
comma-separated list of their names.
The implementation resides in the same file as the bisection tool. The
`getGlobalPassGate()` function returns the currently enabled gate.
Example: `-opt-disable="PassA,PassB"`
Pass names are matched using case-insensitive comparisons. However, note
that special characters, including spaces, must be included exactly as
they appear in the pass names.
Additionally, a `-opt-disable-enable-verbosity` flag has been introduced to
enable verbose output when this functionality is in use. When enabled,
it prints the status of all passes (either running or NOT running),
similar to the default behavior of `-opt-bisect-limit`. This flag is
disabled by default, which is the opposite of the `-opt-bisect-verbose`
flag (which defaults to enabled).
To validate this functionality, a test file has also been provided. It reuses
the same infrastructure as the opt-bisect test, but disables three
specific passes and checks the output to ensure the expected behavior.
---------
Co-authored-by: Nikita Popov <github at npopov.com>
Commit: 210cf010c3362e5648d037ea5e4b27c2673837ed
https://github.com/llvm/llvm-project/commit/210cf010c3362e5648d037ea5e4b27c2673837ed
Author: Valentin Clement (バレンタイン クレメン) <clementval at gmail.com>
Date: 2025-07-16 (Wed, 16 Jul 2025)
Changed paths:
M flang/include/flang/Optimizer/Builder/IntrinsicCall.h
M flang/lib/Optimizer/Builder/IntrinsicCall.cpp
M flang/module/cudadevice.f90
M flang/test/Lower/CUDA/cuda-device-proc.cuf
Log Message:
-----------
[flang][cuda] Lower globaltimer to NVVM op (#149217)
Commit: 9d78eb5cc51820bd7076861a9ad175e5666b90d3
https://github.com/llvm/llvm-project/commit/9d78eb5cc51820bd7076861a9ad175e5666b90d3
Author: Wenju He <wenju.he at intel.com>
Date: 2025-07-17 (Thu, 17 Jul 2025)
Changed paths:
M libclc/CMakeLists.txt
Log Message:
-----------
[libclc] Enable -fdiscard-value-names build flag to reduce bitcode size (#149016)
The flag reduces nvptx64--nvidiacl.bc size from 10.6MB to 5.2MB.
Commit: b52cf756ced2aefd05b7e2f01026c941f9a04c47
https://github.com/llvm/llvm-project/commit/b52cf756ced2aefd05b7e2f01026c941f9a04c47
Author: Changpeng Fang <changpeng.fang at amd.com>
Date: 2025-07-16 (Wed, 16 Jul 2025)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPUInsertDelayAlu.cpp
M llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
M llvm/lib/Target/AMDGPU/SIInstrInfo.h
M llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp
M llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.h
A llvm/test/CodeGen/AMDGPU/insert-delay-alu-wmma-xdl.mir
Log Message:
-----------
AMDGPU: Treat WMMA XDL ops as TRANS in S_DELAY_ALU insertion for gfx1250 (#149208)
WMMA XDL instructions are tracked as TRANs ops and the compiler should
consider them the same as TRANS in S_DELAY_ALU insertion. We use a searchable
table for the InsertDelayAlu pass to recognize these WMMA XDL instructions.
Co-authored-by: Stefan Stipanovic <Stefan.Stipanovic at amd.com>
Commit: 4cf7670b01fb5b01995cf89fe4304bfb0c69a4c0
https://github.com/llvm/llvm-project/commit/4cf7670b01fb5b01995cf89fe4304bfb0c69a4c0
Author: Valentin Clement (バレンタイン クレメン) <clementval at gmail.com>
Date: 2025-07-16 (Wed, 16 Jul 2025)
Changed paths:
M flang/include/flang/Optimizer/Builder/IntrinsicCall.h
M flang/lib/Optimizer/Builder/IntrinsicCall.cpp
M flang/module/cudadevice.f90
M flang/test/Lower/CUDA/cuda-device-proc.cuf
Log Message:
-----------
[flang][cuda] Lower clock() to NNVM op (#149228)
Also use a same gen function for all NVVM time ops.
Commit: f56211ebfa7f9ca71b9eeb119012b0f6e1a2b2c9
https://github.com/llvm/llvm-project/commit/f56211ebfa7f9ca71b9eeb119012b0f6e1a2b2c9
Author: Craig Topper <craig.topper at sifive.com>
Date: 2025-07-16 (Wed, 16 Jul 2025)
Changed paths:
M llvm/test/CodeGen/RISCV/xqcisls.ll
Log Message:
-----------
[RISCV] Add/remove/simplify tests in xqcisls.ll. NFC
-Don't use i64 for GEP indices.
-Remove tests that zero extended GEP indices from i32 to i64.
-Add i64 load/store tests taken from xtheadmemidx that get split into two i32 load/store.
-Don't extend load results to i64.
I'm working on improvements to SelectAddrRegRegScale.
Commit: 0692572e040979b2de0dceb8f0537aa16caf351f
https://github.com/llvm/llvm-project/commit/0692572e040979b2de0dceb8f0537aa16caf351f
Author: Ryotaro Kasuga <kasuga.ryotaro at fujitsu.com>
Date: 2025-07-17 (Thu, 17 Jul 2025)
Changed paths:
M clang/lib/CodeGen/CGLoopInfo.cpp
M clang/test/CodeGenCXX/pragma-loop.cpp
Log Message:
-----------
[clang][CodeGen] Fix metadata when vectorization is disabled by pragma (#135163)
Currently, when specifying `vectorize(disable) unroll_count(8)`, the
generated metadata appears as follows:
```
!loop0 = !{!"loop0", !vectorize_width, !followup}
!vectorize_width = !{!"llvm.loop.vectorize.width", i32 1}
!followup = !{!"llvm.loop.vectorize.followup_all", !unroll}
!unroll = !{!"llvm.loop.unroll_count", i32 8}
```
Since the metadata `!vectorize_width` implies that the vectorization is
disabled, the vectorization process is skipped, and the `!followup`
metadata is not processed correctly.
This patch addresses the issue by directly appending properties to the
metadata node when vectorization is disabled, instead of creating a new
follow-up MDNode. In the above case, the generated metadata will now
look like this:
```
!loop0 = !{!"loop0", !vectorize_width, !vectorize_width, !unroll}
!vectorize_width = !{!"llvm.loop.vectorize.width", i32 1}
!unroll = !{!"llvm.loop.unroll_count", i32 8}
```
Commit: b41398294c85eacdb37b9637eed6f0e91edf35cf
https://github.com/llvm/llvm-project/commit/b41398294c85eacdb37b9637eed6f0e91edf35cf
Author: Wenju He <wenju.he at intel.com>
Date: 2025-07-17 (Thu, 17 Jul 2025)
Changed paths:
M clang/lib/Basic/Targets/SPIR.h
A clang/test/CodeGenOpenCL/scoped-atomic.cl
Log Message:
-----------
[SPIR] Set MaxAtomicInlineWidth minimum size to 32 for spir32 and 64 for spir64 (#148997)
Set MaxAtomicInlineWidth the same way as SPIR-V targets in 3cfd0c0d3697.
This PR fixes build warning in scoped atomic built-in in #146814:
`warning: large atomic operation may incur significant performance
penalty; ; the access size (2 bytes) exceeds the max lock-free size (0
bytes) [-Watomic-alignment]`
Commit: b9adc4a59cb50c98ec0e01645ea5eb64e6628afd
https://github.com/llvm/llvm-project/commit/b9adc4a59cb50c98ec0e01645ea5eb64e6628afd
Author: Philip Reames <preames at rivosinc.com>
Date: 2025-07-16 (Wed, 16 Jul 2025)
Changed paths:
M llvm/include/llvm/CodeGen/TargetLowering.h
M llvm/lib/CodeGen/InterleavedAccessPass.cpp
M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
M llvm/lib/Target/AArch64/AArch64ISelLowering.h
M llvm/lib/Target/RISCV/RISCVISelLowering.h
M llvm/lib/Target/RISCV/RISCVInterleavedAccess.cpp
Log Message:
-----------
[IA] Use a single callback for lowerInterleaveIntrinsic [nfc] (#148978) (#149168)
This continues in the direction started by commit 4b81dc7. We
essentially merges the handling for VPStore - currently in
lowerInterleavedVPStore which is shared between shuffle and intrinsic
based interleaves - into the existing dedicated routine.
Commit: 34951f7de80c4b4ac2b884d08dd919efed23c024
https://github.com/llvm/llvm-project/commit/34951f7de80c4b4ac2b884d08dd919efed23c024
Author: Valentin Clement (バレンタイン クレメン) <clementval at gmail.com>
Date: 2025-07-16 (Wed, 16 Jul 2025)
Changed paths:
M flang/include/flang/Optimizer/Builder/IntrinsicCall.h
M flang/lib/Optimizer/Builder/IntrinsicCall.cpp
M flang/test/Lower/CUDA/cuda-device-proc.cuf
Log Message:
-----------
[flang][cuda] Use NVVM op for clock64 (#149223)
Commit: b36188514a76ba979439a1dcab58e68478e3f0ad
https://github.com/llvm/llvm-project/commit/b36188514a76ba979439a1dcab58e68478e3f0ad
Author: Philip Reames <preames at rivosinc.com>
Date: 2025-07-16 (Wed, 16 Jul 2025)
Changed paths:
M llvm/lib/Target/RISCV/RISCVInterleavedAccess.cpp
M llvm/test/CodeGen/RISCV/rvv/vp-vector-interleaved-access.ll
Log Message:
-----------
[RISCV][IA] Check nuw on multiply when analyzing EVL (#149205)
If we're checking to see if a number is a multiple of a small constant,
we need to be sure the multiply doesn't overflow for the mul logic to
hold. The VL is a unsigned number, so we care about unsigned overflow.
Once we've proven a number of a multiple, we can also use an
exact udiv as we know we're not discarding any bits.
This fixes what is technically a miscompile with EVL vectorization, but
I doubt we'd ever have seen it in practice since most EVLs are going to
much less than UINT_MAX.
Commit: 34b3ea367c4299ebd7c37edc7c748c9627ee66cb
https://github.com/llvm/llvm-project/commit/34b3ea367c4299ebd7c37edc7c748c9627ee66cb
Author: Christopher Ferris <cferris1000 at users.noreply.github.com>
Date: 2025-07-16 (Wed, 16 Jul 2025)
Changed paths:
M compiler-rt/lib/scudo/standalone/tests/common_test.cpp
Log Message:
-----------
[scudo] Make release to OS test more specific. (#147852)
The original version of ResidentMemorySize could be a little flaky.
Replace the test with a version that verifies exactly how much of the
map is resident.
Commit: 1f1fd07c325f174be27d6f10a512882770a976a8
https://github.com/llvm/llvm-project/commit/1f1fd07c325f174be27d6f10a512882770a976a8
Author: Ryan Buchner <buchner.ryan at gmail.com>
Date: 2025-07-16 (Wed, 16 Jul 2025)
Changed paths:
M llvm/lib/Transforms/InstCombine/InstCombineSelect.cpp
M llvm/test/Transforms/InstCombine/icmp-select.ll
A llvm/test/Transforms/InstCombine/select-fixed-zero.ll
M llvm/test/Transforms/InstCombine/select.ll
Log Message:
-----------
[InstCombine] Optimize (select %x, op(%x), 0) to op(%x) for operations where op(0) == 0 (#147605)
Currently this optimization only occurs for `mul`, but this generalizes
that for any operation that has a fixed point of `0`.
There is similar logic within `EarlyCSE` pass, but that is stricter in
terms of `poison` propagation so will not optimize for many operations.
Alive2 Proofs:
`and`:
https://alive2.llvm.org/ce/z/RraasX ; base-case
https://alive2.llvm.org/ce/z/gzfFTX ; commuted-case
https://alive2.llvm.org/ce/z/63XaoX ; compare against undef
https://alive2.llvm.org/ce/z/MVRVNd ; select undef
https://alive2.llvm.org/ce/z/2bsoYG ; vector
https://alive2.llvm.org/ce/z/xByeX- ; vector compare against undef
https://alive2.llvm.org/ce/z/zNdzmZ ; vector select undef
`fshl`:
https://alive2.llvm.org/ce/z/U3_PG3 ; base-case
https://alive2.llvm.org/ce/z/BWCnxT ; compare against undef
https://alive2.llvm.org/ce/z/8HGAE_ ; select undef
; vector times out
`fshr`:
https://alive2.llvm.org/ce/z/o6F47G ; base-case
https://alive2.llvm.org/ce/z/fVnBXy ; compare against undef
https://alive2.llvm.org/ce/z/suymYJ ; select undef
; vector times out
`umin`:
https://alive2.llvm.org/ce/z/GGMqf6 ; base-case
https://alive2.llvm.org/ce/z/6cx5-k ; commuted-case
https://alive2.llvm.org/ce/z/W5d9tz ; compare against undef
https://alive2.llvm.org/ce/z/nKbaUn ; select undef
https://alive2.llvm.org/ce/z/gxEGqc ; vector
https://alive2.llvm.org/ce/z/_SDpi_ ; vector compare against undef
`sdiv`:
https://alive2.llvm.org/ce/z/5XGs3q
`srem`:
https://alive2.llvm.org/ce/z/vXAnQM
`udiv`:
https://alive2.llvm.org/ce/z/e6_8Ug
`urem`:
https://alive2.llvm.org/ce/z/VmM2SL
`shl`:
https://alive2.llvm.org/ce/z/aCZr3u ; Argument with range
https://alive2.llvm.org/ce/z/YgDy8C ; Instruction with known bits
https://alive2.llvm.org/ce/z/6pIxR6 ; Constant
`lshr`:
https://alive2.llvm.org/ce/z/WCCBej
`ashr:
https://alive2.llvm.org/ce/z/egV4TR
---------
Co-authored-by: Ryan Buchner <rbuchner at ventanamicro.com>
Co-authored-by: Yingwei Zheng <dtcxzyw at qq.com>
Commit: 283a62fa5b9f2b07fb74336dbce91f346801225f
https://github.com/llvm/llvm-project/commit/283a62fa5b9f2b07fb74336dbce91f346801225f
Author: Jeffrey Byrnes <jeffrey.byrnes at amd.com>
Date: 2025-07-16 (Wed, 16 Jul 2025)
Changed paths:
M llvm/lib/Target/AMDGPU/GCNSchedStrategy.cpp
Log Message:
-----------
[AMDGPU] NFC: Decouple getRealRegPressure from current region (#149219)
We're already accepting a RegionIdx for the LiveIns, also use this for
the instruction iterators.
Enables querying RP for other regions -- useful for function wide
transformations (e.g. rematerialization, rewriting, etc).
Commit: 1c541aa9f9a2453324724bfb9d661bc672778d10
https://github.com/llvm/llvm-project/commit/1c541aa9f9a2453324724bfb9d661bc672778d10
Author: thetruestblue <bblueconway at gmail.com>
Date: 2025-07-16 (Wed, 16 Jul 2025)
Changed paths:
M compiler-rt/test/lit.common.cfg.py
Log Message:
-----------
[Apple][NFC] Update macOS aligned version for lit config (#143576)
This updates the aligned version for version 26.
Note: This change is for correctness only and has no functional impact
currently. `get_macos_aligned_version` is currently only consumed when
substituting flags based on min version.
rdar://152851947
Commit: 0f09f2cf00caf3e6c755197d7c897ce8e607db4d
https://github.com/llvm/llvm-project/commit/0f09f2cf00caf3e6c755197d7c897ce8e607db4d
Author: Florian Mayer <fmayer at google.com>
Date: 2025-07-16 (Wed, 16 Jul 2025)
Changed paths:
M clang/lib/CodeGen/CGDebugInfo.cpp
A clang/test/CodeGen/null-sanitizer-debug-info-regression.cpp
Log Message:
-----------
[Sanitize] fix crash in -fsanitize-annotate-debug-info (#149237)
Commit: e51ea1c7571c9d7698ab01317fd4ab3b250cb8f9
https://github.com/llvm/llvm-project/commit/e51ea1c7571c9d7698ab01317fd4ab3b250cb8f9
Author: Jim Lin <jim at andestech.com>
Date: 2025-07-17 (Thu, 17 Jul 2025)
Changed paths:
M llvm/test/CodeGen/RISCV/xandesbfhcvt.ll
Log Message:
-----------
[RISCV] Remove unneeded declarations in llvm/test/CodeGen/RISCV/xandesbfhcvt.ll. NFC.
Commit: 9753ea83dd34bfb169fbed3995cc79e621ca6963
https://github.com/llvm/llvm-project/commit/9753ea83dd34bfb169fbed3995cc79e621ca6963
Author: Fangrui Song <i at maskray.me>
Date: 2025-07-16 (Wed, 16 Jul 2025)
Changed paths:
M llvm/test/MC/AArch64/directives-case_insensitive.s
M llvm/test/MC/AArch64/reloc-directive-err.s
M llvm/test/MC/AArch64/reloc-directive.s
M llvm/test/MC/AMDGPU/reloc-directive.s
M llvm/test/MC/ARM/reloc-directive-err.s
M llvm/test/MC/ARM/reloc-directive.s
M llvm/test/MC/AVR/reloc-directive-err.s
M llvm/test/MC/AVR/reloc-directive.s
M llvm/test/MC/LoongArch/Relocations/reloc-directive-err.s
M llvm/test/MC/LoongArch/Relocations/reloc-directive.s
M llvm/test/MC/Mips/reloc-directive-bad.s
M llvm/test/MC/Mips/reloc-directive.s
M llvm/test/MC/PowerPC/ppc32-reloc-directive.s
M llvm/test/MC/PowerPC/ppc64-reloc-directive.s
M llvm/test/MC/RISCV/reloc-directive-err.s
M llvm/test/MC/RISCV/reloc-directive.s
M llvm/test/MC/Sparc/Relocations/reloc-directive.s
M llvm/test/MC/SystemZ/reloc-directive.s
M llvm/test/MC/X86/reloc-directive-elf-32.s
M llvm/test/MC/X86/reloc-directive-elf-64.s
M llvm/test/MC/X86/reloc-directive.s
Log Message:
-----------
MC,test: Migrate away from the .reloc constant hack
The initial .reloc support for MIPS incorrectly interpreted .reloc 0 as .reloc .+0 .
I was misled when porting .reloc to other targets in 2019 and 2020.
Many PRINT: prefixes are unnecessary. The MCAsmStreamer implementation
is generic, and it is unnecessary to test too many variants.
Commit: 4a3cb437a32f5611b909fe7e067a9a9d28c2b845
https://github.com/llvm/llvm-project/commit/4a3cb437a32f5611b909fe7e067a9a9d28c2b845
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2025-07-17 (Thu, 17 Jul 2025)
Changed paths:
M llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
Log Message:
-----------
AMDGPU: Avoid hardcoding mov opcode
Commit: 72c61a6a255cd07c449f213bef9439ab0ee85c08
https://github.com/llvm/llvm-project/commit/72c61a6a255cd07c449f213bef9439ab0ee85c08
Author: Vikram Hegde <115221833+vikramRH at users.noreply.github.com>
Date: 2025-07-17 (Thu, 17 Jul 2025)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
M llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.h
M llvm/test/CodeGen/AMDGPU/llc-pipeline-npm.ll
Log Message:
-----------
[AMDGPU][NPM] Fill in addPreSched2 passes (#148112)
same as https://github.com/llvm/llvm-project/pull/139516
Co-authored-by : Oke, Akshat
<[Akshat.Oke at amd.com](mailto:Akshat.Oke at amd.com)>
Commit: 34c85337424fde5796154d0cb390b39175291373
https://github.com/llvm/llvm-project/commit/34c85337424fde5796154d0cb390b39175291373
Author: Nikita Popov <npopov at redhat.com>
Date: 2025-07-17 (Thu, 17 Jul 2025)
Changed paths:
M llvm/lib/Transforms/Coroutines/CoroFrame.cpp
M llvm/test/Transforms/Coroutines/coro-async-addr-lifetime-start-bug.ll
Log Message:
-----------
[Coroutines] Always drop lifetime markers after moving allocas to frame (#149141)
https://github.com/llvm/llvm-project/pull/142551 started always dropping
lifetime markers after moving allocas on the frame, as these are not
useful on non-allocas but can cause issues.
However, this was not done for other ABIs (retcon, retcononce, async)
that go through a different code path. We should treat them the same
way.
Commit: 3cb0c7f45b97802ddc13a15560fbbca2efb75326
https://github.com/llvm/llvm-project/commit/3cb0c7f45b97802ddc13a15560fbbca2efb75326
Author: Fangrui Song <i at maskray.me>
Date: 2025-07-17 (Thu, 17 Jul 2025)
Changed paths:
M lld/ELF/Relocations.cpp
M llvm/include/llvm/MC/MCAssembler.h
M llvm/include/llvm/MC/MCELFStreamer.h
M llvm/include/llvm/MC/MCObjectStreamer.h
M llvm/include/llvm/MC/MCStreamer.h
M llvm/lib/MC/MCAsmStreamer.cpp
M llvm/lib/MC/MCAssembler.cpp
M llvm/lib/MC/MCELFStreamer.cpp
M llvm/lib/MC/MCObjectStreamer.cpp
M llvm/lib/MC/MCParser/AsmParser.cpp
M llvm/lib/Target/AArch64/MCTargetDesc/AArch64ELFStreamer.cpp
M llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp
M llvm/lib/Target/Mips/MipsAsmPrinter.cpp
M llvm/test/MC/ELF/reloc-directive.s
M llvm/test/MC/Mips/reloc-directive-bad-obj.s
M llvm/test/MC/Mips/reloc-directive-label-offset.s
Log Message:
-----------
MC: Rework .reloc directive and fix the offset when it evaluates to a constant
* Fix `.reloc constant` to mean section_symbol+constant instead of
.+constant . The initial .reloc support from MIPS incorrectly
interpreted the offset.
* Delay the evaluation of the offset expression after
MCAssembler::layout, deleting a lot of code working with MCFragment.
* Delete many FIXME from https://reviews.llvm.org/D79625
* Some lld/ELF/Arch/LoongArch.cpp relaxation tests rely on .reloc .,
R_LARCH_ALIGN generating ALIGN relocations at specific location.
Sort the relocations.
Commit: 1653a093def10543d8f958fe7d4cde9ab1dd8bca
https://github.com/llvm/llvm-project/commit/1653a093def10543d8f958fe7d4cde9ab1dd8bca
Author: Daan De Meyer <daan.j.demeyer at gmail.com>
Date: 2025-07-17 (Thu, 17 Jul 2025)
Changed paths:
M clang/docs/ClangFormatStyleOptions.rst
M clang/include/clang/Format/Format.h
M clang/lib/Format/Format.cpp
M clang/unittests/Format/ConfigParseTest.cpp
M clang/unittests/Format/SortIncludesTest.cpp
Log Message:
-----------
[clang-format] Add IgnoreExtension to SortIncludes (#137840)
Sorting by stem gives nicer results when various header file names are
substrings of other header file names. For example, a CLI application
with a main header named analyze.h and an analyze-xxx.h header for each
subcommand currently will always put analyze.h last after all the
analyze-xxx.h headers, but putting analyze.h first instead is arguably
nicer to read.
TLDR; Instead of
```
#include "analyze-blame.h"
#include "analyze.h"
```
You'd get
```
#include "analyze.h"
#include "analyze-blame.h"
```
Let's allow sorting by stem instead of full path by adding
IgnoreExtension to SortIncludes.
Commit: 2194bca2b78cf1ada2aa539e2a3ad8128a80f63a
https://github.com/llvm/llvm-project/commit/2194bca2b78cf1ada2aa539e2a3ad8128a80f63a
Author: William Tran-Viet <wtranviet at proton.me>
Date: 2025-07-17 (Thu, 17 Jul 2025)
Changed paths:
M libcxx/include/CMakeLists.txt
M libcxx/include/__format/range_default_formatter.h
A libcxx/include/__format/range_format.h
M libcxx/include/module.modulemap.in
Log Message:
-----------
[libc++] Granularize `range_format` and `format_kind` declarations (#148876)
While working on #105430 I ran into an issue implementing
[[optional.syn]](https://eel.is/c++draft/optional.syn) because of a
circular include that looked like the following: `optional ->
__format/range_default_formatter.h -> __format/range_formatter.h ->
__format/format_context.h -> optional`. Only `format_kind` and
`range_format` are needed, and so they looked like candidates to be put
into an internal header.
Commit: d218011159105208de38275594c75735929f74aa
https://github.com/llvm/llvm-project/commit/d218011159105208de38275594c75735929f74aa
Author: ZhaoQi <zhaoqi01 at loongson.cn>
Date: 2025-07-17 (Thu, 17 Jul 2025)
Changed paths:
M llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp
M llvm/lib/Target/LoongArch/LoongArchLASXInstrInfo.td
M llvm/lib/Target/LoongArch/LoongArchLSXInstrInfo.td
M llvm/test/CodeGen/LoongArch/lasx/ir-instruction/fix-xvshuf.ll
M llvm/test/CodeGen/LoongArch/lasx/ir-instruction/insert-extract-element.ll
M llvm/test/CodeGen/LoongArch/lasx/ir-instruction/insert-extract-pair-elements.ll
M llvm/test/CodeGen/LoongArch/lsx/ir-instruction/insert-extract-element.ll
Log Message:
-----------
[LoongArch] Optimize inserting extracted elements (#146018)
Commit: 3071fe55f8321ea18952412a233f7330ce26b522
https://github.com/llvm/llvm-project/commit/3071fe55f8321ea18952412a233f7330ce26b522
Author: Jonathan Wakely <github at kayari.org>
Date: 2025-07-17 (Thu, 17 Jul 2025)
Changed paths:
M libcxx/test/std/utilities/template.bitset/bitset.members/to_ullong.pass.cpp
Log Message:
-----------
[libc++] Add missing include <limits> to bitset to_ullong.pass.cpp test (#149149)
This was added to to_ulong.pass.cpp years ago by
cf1dc8d39e2c9870468ca86f7956a65c7745fece but I don't think the other
part of that commit matters here.
Commit: 1d398a96dc6b58d15d289c71e2d9f229a0ba719b
https://github.com/llvm/llvm-project/commit/1d398a96dc6b58d15d289c71e2d9f229a0ba719b
Author: Madhur Amilkanthwar <madhura at nvidia.com>
Date: 2025-07-17 (Thu, 17 Jul 2025)
Changed paths:
M llvm/lib/Transforms/Scalar/GVN.cpp
Log Message:
-----------
[GVN][NFC] Use early return in phiTranslateImpl() (#149268)
Commit: ace6e20e52c0c343500f68fa053b6be546e5a0db
https://github.com/llvm/llvm-project/commit/ace6e20e52c0c343500f68fa053b6be546e5a0db
Author: LLVM GN Syncbot <llvmgnsyncbot at gmail.com>
Date: 2025-07-17 (Thu, 17 Jul 2025)
Changed paths:
M llvm/utils/gn/secondary/libcxx/include/BUILD.gn
Log Message:
-----------
[gn build] Port 2194bca2b78c
Commit: bce951c572465c6ccd59b73a58c536641abc43eb
https://github.com/llvm/llvm-project/commit/bce951c572465c6ccd59b73a58c536641abc43eb
Author: Andrzej Warzyński <andrzej.warzynski at arm.com>
Date: 2025-07-17 (Thu, 17 Jul 2025)
Changed paths:
M mlir/lib/Dialect/Linalg/Transforms/Vectorization.cpp
M mlir/test/Dialect/Linalg/vectorization/linalg-ops.mlir
Log Message:
-----------
[mlir][linalg] Update vectorization logic for linalg.unpack (#149156)
This PR makes sure that we don't generate unnecessary `tensor.empty`
when vectorizing `linalg.unpack`.
To better visualize the changes implemented here, consider this IR:
```mlir
func.func @example(
%source: tensor<8x4x16x16xf32>,
%dest: tensor<64x127xf32>) -> tensor<64x127xf32> {
%res = linalg.unpack %source
outer_dims_perm = [1, 0]
inner_dims_pos = [0, 1]
inner_tiles = [16, 16]
into %dest : tensor<8x4x16x16xf32> -> tensor<64x127xf32>
return %res : tensor<64x127xf32>
}
```
Below is the output after vectorization, BEFORE and AFTER this PR.
BEFORE (note `tensor.empty` and the fact that `%arg1` is not used):
```mlir
func.func @example(%arg0: tensor<8x4x16x16xf32>, %arg1: tensor<64x127xf32>) -> tensor<64x127xf32> {
%cst = arith.constant 0.000000e+00 : f32
%c0 = arith.constant 0 : index
%0 = vector.transfer_read %arg0[%c0, %c0, %c0, %c0], %cst {in_bounds = [true, true, true, true]} : tensor<8x4x16x16xf32>, vector<8x4x16x16xf32>
%1 = vector.transpose %0, [1, 2, 0, 3] : vector<8x4x16x16xf32> to vector<4x16x8x16xf32>
%2 = vector.shape_cast %1 : vector<4x16x8x16xf32> to vector<64x128xf32>
%3 = tensor.empty() : tensor<64x127xf32>
%c0_0 = arith.constant 0 : index
%4 = vector.transfer_write %2, %3[%c0_0, %c0_0] {in_bounds = [true, false]} : vector<64x128xf32>, tensor<64x127xf32>
return %4 : tensor<64x127xf32>
}
```
AFTER (note that `%arg1` is correctly used):
```mlir
func.func @example(%arg0: tensor<8x4x16x16xf32>, %arg1: tensor<64x127xf32>) -> tensor<64x127xf32> {
%cst = arith.constant 0.000000e+00 : f32
%c0 = arith.constant 0 : index
%0 = vector.transfer_read %arg0[%c0, %c0, %c0, %c0], %cst {in_bounds = [true, true, true, true]} : tensor<8x4x16x16xf32>, vector<8x4x16x16xf32>
%1 = vector.transpose %0, [1, 2, 0, 3] : vector<8x4x16x16xf32> to vector<4x16x8x16xf32>
%2 = vector.shape_cast %1 : vector<4x16x8x16xf32> to vector<64x128xf32>
%c0_0 = arith.constant 0 : index
%3 = vector.transfer_write %2, %arg1[%c0_0, %c0_0] {in_bounds = [true, false]} : vector<64x128xf32>, tensor<64x127xf32>
return %3 : tensor<64x127xf32>
}
```
Commit: 8b553c495155a024d22871f22f05187fb785c4fc
https://github.com/llvm/llvm-project/commit/8b553c495155a024d22871f22f05187fb785c4fc
Author: Madhur Amilkanthwar <madhura at nvidia.com>
Date: 2025-07-17 (Thu, 17 Jul 2025)
Changed paths:
M llvm/lib/Transforms/Scalar/GVN.cpp
Log Message:
-----------
Revert "[GVN][NFC] Use early return in phiTranslateImpl() (#149268)" (#149270)
This reverts commit 1d398a96dc6b58d15d289c71e2d9f229a0ba719b.
Commit: e0cce5cdcb8a7829389d910a9204447646e69407
https://github.com/llvm/llvm-project/commit/e0cce5cdcb8a7829389d910a9204447646e69407
Author: Guillaume Chatelet <gchatelet at google.com>
Date: 2025-07-17 (Thu, 17 Jul 2025)
Changed paths:
M libc/src/string/memory_utils/CMakeLists.txt
A libc/src/string/memory_utils/arm/common.h
M libc/src/string/memory_utils/arm/inline_memcpy.h
A libc/src/string/memory_utils/arm/inline_memset.h
M libc/src/string/memory_utils/inline_memset.h
M utils/bazel/llvm-project-overlay/libc/BUILD.bazel
Log Message:
-----------
[libc] Improve Cortex `memset` and `memcpy` functions (#149044)
The code for `memcpy` is the same as in #148204 but it fixes the build
bot error by using `static_assert(cpp::always_false<decltype(access)>)`
instead of `static_assert(false)` (older compilers fails on
`static_assert(false)` in `constexpr` `else` bodies).
The code for `memset` is new and vastly improves performance over the
current byte per byte implementation.
Both `memset` and `memcpy` implementations use prefetching for sizes >=
64. This lowers a bit the performance for sizes between 64 and 256 but
improves throughput for greater sizes.
Commit: 742147ba1bb26d7a69d4289b6ad9a07bd019a2ae
https://github.com/llvm/llvm-project/commit/742147ba1bb26d7a69d4289b6ad9a07bd019a2ae
Author: Djordje Todorovic <djordje.todorovic at htecgroup.com>
Date: 2025-07-17 (Thu, 17 Jul 2025)
Changed paths:
M clang/test/Driver/frame-pointer-elim.c
M llvm/include/llvm/Object/ELFObjectFile.h
M llvm/include/llvm/TargetParser/Triple.h
M llvm/lib/Object/RelocationResolver.cpp
M llvm/lib/TargetParser/Triple.cpp
M llvm/test/tools/llvm-objcopy/ELF/binary-output-target.test
M llvm/tools/llvm-objcopy/ObjcopyOptions.cpp
M llvm/unittests/Object/ELFObjectFileTest.cpp
Log Message:
-----------
[llvm-objcopy][libObject] Add RISC-V big-endian support (#146913)
Add support for big-endian RISC-V ELF files:
- Add riscv32be/riscv64be target architectures to Triple
- Support elf32-bigriscv and elf64-bigriscv output targets in
llvm-objcopy
- Update ELFObjectFile to handle BE RISC-V format strings and
architecture detection
- Add BE RISC-V support to RelocationResolver
- Add tests for new functionality
This is a subset of a bigger RISC-V big-endian support patch, containing
only the llvm-objcopy and libObject changes. Other changes will be added
later.
Commit: 3dc5d687b09af5568e9bd80160addb550a46e341
https://github.com/llvm/llvm-project/commit/3dc5d687b09af5568e9bd80160addb550a46e341
Author: Nikolas Klauser <nikolasklauser at berlin.de>
Date: 2025-07-17 (Thu, 17 Jul 2025)
Changed paths:
R libcxx/test/libcxx/minimal_cxx11_configuration.pass.cpp
Log Message:
-----------
[libc++] Remove minimal_cxx11_configuration.pass.cpp (#149119)
This test doesn't seem to be very useful. If it is the only test that
fails we would just remove the failing parts of the test, and otherwise
it doesn't provide any value either, since there will be another test
that fails.
Commit: b291d1a71f39eb14b89b6aeccfc10bcd3c92a1ef
https://github.com/llvm/llvm-project/commit/b291d1a71f39eb14b89b6aeccfc10bcd3c92a1ef
Author: Jeffrey Byrnes <jeffrey.byrnes at amd.com>
Date: 2025-07-17 (Thu, 17 Jul 2025)
Changed paths:
M llvm/lib/CodeGen/TargetInstrInfo.cpp
A llvm/test/CodeGen/AMDGPU/regalloc-undef-copy-fold.mir
Log Message:
-----------
[TII] Do not fold undef copies (#147392)
RegallocBase::cleanupFailedVReg hacks up the state of the liveness in
order to facilitate producing valid IR. During this process, we may end
up producing undef copies.
If the destination of these copies is a spill candidate, we will attempt
to fold the source register when issuing the spill. The undef of the
source is not propagated to storeRegToStackSlot , thus we end up
dropping the undef, issuing a spill, and producing an illegal liveness
state.
This checks for undef copies, and, if found, inserts a kill instead of
spill.
Commit: 4993f5b12ce4c847bb76f9bd23c188a02b27f2d9
https://github.com/llvm/llvm-project/commit/4993f5b12ce4c847bb76f9bd23c188a02b27f2d9
Author: Nikolas Klauser <nikolasklauser at berlin.de>
Date: 2025-07-17 (Thu, 17 Jul 2025)
Changed paths:
M libcxx/include/string
Log Message:
-----------
[libc++][NFC] Use variable templates in <string> (#149038)
Variable templates are a bit lighter on the compiler than class
templates.
Commit: 4695aea28e5cc6ba2841562992c83d3e16dda36a
https://github.com/llvm/llvm-project/commit/4695aea28e5cc6ba2841562992c83d3e16dda36a
Author: Nikolas Klauser <nikolasklauser at berlin.de>
Date: 2025-07-17 (Thu, 17 Jul 2025)
Changed paths:
A libcxx/test/extensions/libcxx/localization/lit.local.cfg
A libcxx/test/extensions/libcxx/localization/locale.convenience/conversions/conversions.string/ctor_move.pass.cpp
R libcxx/test/libcxx/localization/locales/locale.convenience/conversions/conversions.string/ctor_move.pass.cpp
R libcxx/test/libcxx/memory/shared_ptr_array.pass.cpp
R libcxx/test/libcxx/numerics/c.math/fdelayed-template-parsing.pass.cpp
R libcxx/test/libcxx/numerics/rand/rand.req.urng/valid_int_type.verify.cpp
R libcxx/test/libcxx/numerics/rand/rand.req.urng/valid_real_type.verify.cpp
A libcxx/test/std/numerics/c.math/fdelayed-template-parsing.pass.cpp
A libcxx/test/std/numerics/rand/rand.req/rand.req.urng/valid_int_type.verify.cpp
A libcxx/test/std/numerics/rand/rand.req/rand.req.urng/valid_real_type.verify.cpp
A libcxx/test/std/utilities/memory/util.smartptr/util.smartptr.shared/util.smartptr.shared.create/shared_ptr_array.pass.cpp
Log Message:
-----------
[libc++] Move more tests into better places (#148419)
Commit: d87170211dc780341e42f7719c7332416f9cc290
https://github.com/llvm/llvm-project/commit/d87170211dc780341e42f7719c7332416f9cc290
Author: David Spickett <david.spickett at linaro.org>
Date: 2025-07-17 (Thu, 17 Jul 2025)
Changed paths:
M lldb/test/API/commands/frame/var-dil/basics/ArraySubscript/TestFrameVarDILArraySubscript.py
M lldb/test/API/functionalities/data-formatter/data-formatter-disabling/TestDataFormatterDisabling.py
M lldb/test/API/lang/cpp/template/TestTemplateArgs.py
Log Message:
-----------
[lldb][test] Remove XFAIL from some Windows tests
These are now passing on Windows x86_64 and Arm64.
Commit: e66eabee0022af60347e83ef2c0d4b6dbfb7f0a5
https://github.com/llvm/llvm-project/commit/e66eabee0022af60347e83ef2c0d4b6dbfb7f0a5
Author: David Spickett <david.spickett at linaro.org>
Date: 2025-07-17 (Thu, 17 Jul 2025)
Changed paths:
M llvm/CMakeLists.txt
Log Message:
-----------
[llvm][cmake] Add clang if not already present when building lldb (#149055)
Fixes https://github.com/llvm/llvm-project/issues/54555
This follows flang's pattern, it adds clang if you don't have it in
LLVM_ENABLE_PROJECTS.
Commit: a78a0f8d204393a0cce367b63395bad90311c1b8
https://github.com/llvm/llvm-project/commit/a78a0f8d204393a0cce367b63395bad90311c1b8
Author: Trevor Gross <tgross at intrepidcs.com>
Date: 2025-07-17 (Thu, 17 Jul 2025)
Changed paths:
M llvm/docs/ReleaseNotes.md
M llvm/lib/Target/X86/X86CallingConv.cpp
M llvm/lib/Target/X86/X86CallingConv.td
M llvm/lib/Target/X86/X86ISelLoweringCall.cpp
M llvm/test/CodeGen/X86/abds-neg.ll
M llvm/test/CodeGen/X86/abds.ll
M llvm/test/CodeGen/X86/abdu-neg.ll
M llvm/test/CodeGen/X86/abdu.ll
M llvm/test/CodeGen/X86/abs.ll
M llvm/test/CodeGen/X86/add-sub-bool.ll
M llvm/test/CodeGen/X86/arg-copy-elide.ll
M llvm/test/CodeGen/X86/avx512fp16-cvt.ll
M llvm/test/CodeGen/X86/bitselect.ll
M llvm/test/CodeGen/X86/bsf.ll
M llvm/test/CodeGen/X86/bsr.ll
M llvm/test/CodeGen/X86/bswap-wide-int.ll
M llvm/test/CodeGen/X86/div-rem-pair-recomposition-signed.ll
M llvm/test/CodeGen/X86/div-rem-pair-recomposition-unsigned.ll
M llvm/test/CodeGen/X86/fp128-cast-strict.ll
M llvm/test/CodeGen/X86/fp128-cast.ll
M llvm/test/CodeGen/X86/fp128-libcalls-strict.ll
M llvm/test/CodeGen/X86/fp128-libcalls.ll
M llvm/test/CodeGen/X86/fshl.ll
M llvm/test/CodeGen/X86/fshr.ll
M llvm/test/CodeGen/X86/funnel-shift.ll
M llvm/test/CodeGen/X86/i128-add.ll
M llvm/test/CodeGen/X86/i128-fp128-abi.ll
M llvm/test/CodeGen/X86/i128-sdiv.ll
M llvm/test/CodeGen/X86/i128-udiv.ll
M llvm/test/CodeGen/X86/iabs.ll
M llvm/test/CodeGen/X86/icmp-shift-opt.ll
M llvm/test/CodeGen/X86/mul128.ll
M llvm/test/CodeGen/X86/neg-abs.ll
M llvm/test/CodeGen/X86/popcnt.ll
M llvm/test/CodeGen/X86/pr46004.ll
M llvm/test/CodeGen/X86/scalar-fp-to-i32.ll
M llvm/test/CodeGen/X86/scalar-fp-to-i64.ll
M llvm/test/CodeGen/X86/scmp.ll
M llvm/test/CodeGen/X86/sdiv_fix.ll
M llvm/test/CodeGen/X86/sdiv_fix_sat.ll
M llvm/test/CodeGen/X86/shift-combine.ll
M llvm/test/CodeGen/X86/shift-i128.ll
M llvm/test/CodeGen/X86/smax.ll
M llvm/test/CodeGen/X86/smin.ll
M llvm/test/CodeGen/X86/ucmp.ll
M llvm/test/CodeGen/X86/udiv_fix.ll
M llvm/test/CodeGen/X86/udiv_fix_sat.ll
M llvm/test/CodeGen/X86/umax.ll
M llvm/test/CodeGen/X86/umin.ll
M llvm/test/CodeGen/X86/umulo-128-legalisation-lowering.ll
M llvm/test/CodeGen/X86/wide-integer-cmp.ll
Log Message:
-----------
[X86] Align f128 and i128 to 16 bytes when passing on x86-32 (#138092)
The i386 psABI specifies that `__float128` has 16 byte alignment and
must be passed on the stack; however, LLVM currently stores it in a
stack slot that has an offset of 4. Add a custom lowering to correct
this alignment to 16-byte.
i386 does not specify an `__int128`, but it seems reasonable to keep the
same behavior as `__float128` so this is changed as well. There also
isn't a good way to distinguish whether a set of four registers came
from an integer or a float.
The main test demonstrating this change is `store_perturbed` in
`llvm/test/CodeGen/X86/i128-fp128-abi.ll`.
Referenced ABI:
https://gitlab.com/x86-psABIs/i386-ABI/-/wikis/uploads/14c05f1b1e156e0e46b61bfa7c1df1e2/intel386-psABI-2020-08-07.pdf
Fixes: https://github.com/llvm/llvm-project/issues/77401
Commit: 28e1e7e1b4b059a2e42f68061475cddb4ad0a6a3
https://github.com/llvm/llvm-project/commit/28e1e7e1b4b059a2e42f68061475cddb4ad0a6a3
Author: Corentin Jabot <corentinjabot at gmail.com>
Date: 2025-07-17 (Thu, 17 Jul 2025)
Changed paths:
M clang/include/clang/Sema/Overload.h
M clang/lib/Sema/SemaOverload.cpp
M clang/test/SemaCXX/overload-resolution-deferred-templates.cpp
Log Message:
-----------
Revert "[Clang] Do not treat Foo -> const Foo conversion sequences as perfect" (#149272)
Reverts llvm/llvm-project#148613
Considering object argument conversion qualifications perfect leads to
situations where we prefer a non-template const qualified function over
a non-qualified template function, which is very wrong indeed.
I explored solutions to work around that, but instead, we might want to
go the GCC road and prefer the friend overload in the #147374 example,
as this seems a lot more consistent and reliable
Commit: 2cdcc4f2c6a0d36a5b534e16d5892ff8b03f3c88
https://github.com/llvm/llvm-project/commit/2cdcc4f2c6a0d36a5b534e16d5892ff8b03f3c88
Author: Florian Hahn <flo at fhahn.com>
Date: 2025-07-17 (Thu, 17 Jul 2025)
Changed paths:
M llvm/lib/Transforms/Vectorize/VPlan.h
Log Message:
-----------
[VPlan] Allow cloning of VPWidenRecipe without underlying instr (NFC).
Update VPWidenRecipe::clone() to use the constructor w/o mandatory
Instruction, to facilitate cloning VPWidenRecipe without underlying
instructions.
Split off from https://github.com/llvm/llvm-project/pull/148239.
Commit: 4797a6c4e8244ab06829b2e462b1329e94286dbf
https://github.com/llvm/llvm-project/commit/4797a6c4e8244ab06829b2e462b1329e94286dbf
Author: Michael Buch <michaelbuch12 at gmail.com>
Date: 2025-07-17 (Thu, 17 Jul 2025)
Changed paths:
M lldb/test/Shell/Settings/TestChildCountTruncation.test
Log Message:
-----------
[lldb][test] TestChildCountTruncation.test: add missing command
Commit: efa5063ba7a7151056439b70901219311c531cec
https://github.com/llvm/llvm-project/commit/efa5063ba7a7151056439b70901219311c531cec
Author: ZhaoQi <zhaoqi01 at loongson.cn>
Date: 2025-07-17 (Thu, 17 Jul 2025)
Changed paths:
M llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp
M llvm/test/CodeGen/LoongArch/lasx/build-vector.ll
M llvm/test/CodeGen/LoongArch/lasx/ir-instruction/insertelement.ll
Log Message:
-----------
[LoongArch] Optimize inserting element to high part of 256bits vector (#146816)
Commit: f04650bb799ce867f629a7d564e03057e8d9b4b0
https://github.com/llvm/llvm-project/commit/f04650bb799ce867f629a7d564e03057e8d9b4b0
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2025-07-17 (Thu, 17 Jul 2025)
Changed paths:
A llvm/test/CodeGen/LoongArch/llvm.exp10.ll
Log Message:
-----------
LoongArch: Add test for llvm.exp10 intrinsic (#148606)
Commit: b1fca543f7c34012697afd99c3dfe1306aa2acab
https://github.com/llvm/llvm-project/commit/b1fca543f7c34012697afd99c3dfe1306aa2acab
Author: Paul Walker <paul.walker at arm.com>
Date: 2025-07-17 (Thu, 17 Jul 2025)
Changed paths:
M llvm/lib/Target/AArch64/AArch64ExpandPseudoInsts.cpp
M llvm/test/CodeGen/AArch64/sve-pseudos-expand-undef.mir
Log Message:
-----------
[LLVM][AArch64ExpandPseudo] Preserve undef flags when expanding SVE 1/2/3-op pseudo instructions. (#149104)
Fixes https://github.com/llvm/llvm-project/issues/149034
Commit: b7c14b6ded300b9190fe0b65881d04c54b2a9fbd
https://github.com/llvm/llvm-project/commit/b7c14b6ded300b9190fe0b65881d04c54b2a9fbd
Author: Stephen Tozer <stephen.tozer at sony.com>
Date: 2025-07-17 (Thu, 17 Jul 2025)
Changed paths:
M llvm/docs/HowToUpdateDebugInfo.rst
A llvm/test/tools/llvm-original-di-preservation/acceptance-test.test
M llvm/test/tools/llvm-original-di-preservation/basic.test
M llvm/utils/llvm-original-di-preservation.py
Log Message:
-----------
[Debugify] Add 'acceptance-test' mode for the debugify report script (#147574)
For the purposes of setting up CI that makes use of debugify, this patch
adds an alternative mode for the llvm-original-di-preservation.py
script, which produces terminal-friendly(-ish) YAML output instead of an
HTML report, and sets the return code to 1 if the input file contains
errors, or 0 if the input file contains no errors or does not exist,
making it simple to use it in CI.
This introduces a small change in existing usage, in that the path for
the HTML report file is now passed with `--report-file <path>` rather
than as a positional argument; I could make the argparse logic work
without this change, but I believe that is simpler to understand this
way, and to my knowledge debugify isn't currently being used in
automated environments where changing this might cause issues. As a
small change while passing by, I also changed `-compress` to
`--compress`, for consistency.
As a note for reviewers, the reason that we treat a non-existent input
file as a pass is that this is actually the expected state: we use clang
to compile numerous files, passing a filepath for debugify errors. Any
errors found by debugify will be written to this file; if none are
found, the file is untouched. This is also mentioned in a code comment,
but I think it useful to state upfront.
Finally, the justification for adding a new mode to this script instead
of adding a separate script for the separate functionality is that this
script understands debugify's output, and performs some deduplication
that is useful for clarifying the resulting output. Writing a new script
would require duplicating logic unnecessarily, and risks the scripts
falling out-of-sync if changes are made to debugify's output.
Commit: e74082703e224740e6281fb04f9a177c42c6467f
https://github.com/llvm/llvm-project/commit/e74082703e224740e6281fb04f9a177c42c6467f
Author: ZhaoQi <zhaoqi01 at loongson.cn>
Date: 2025-07-17 (Thu, 17 Jul 2025)
Changed paths:
M llvm/lib/Target/LoongArch/LoongArchFloat32InstrInfo.td
M llvm/lib/Target/LoongArch/LoongArchLASXInstrInfo.td
M llvm/lib/Target/LoongArch/LoongArchLSXInstrInfo.td
M llvm/test/CodeGen/LoongArch/lasx/ir-instruction/bitcast-extract-element.ll
M llvm/test/CodeGen/LoongArch/lasx/ir-instruction/insert-bitcast-element.ll
M llvm/test/CodeGen/LoongArch/lsx/ir-instruction/bitcast-extract-element.ll
M llvm/test/CodeGen/LoongArch/lsx/ir-instruction/insert-bitcast-element.ll
Log Message:
-----------
[LoongArch] Optimize inserting bitcasted integer element or bitcasting extracted fp element (#147043)
Commit: fe1941967267e472f7eee15b43712bdfa2b63544
https://github.com/llvm/llvm-project/commit/fe1941967267e472f7eee15b43712bdfa2b63544
Author: Jie Fu <jiefu at tencent.com>
Date: 2025-07-17 (Thu, 17 Jul 2025)
Changed paths:
M llvm/lib/Target/X86/X86CallingConv.cpp
Log Message:
-----------
[X86] Fix an unused-variable warnig (NFC)
/llvm-project/llvm/lib/Target/X86/X86CallingConv.cpp:392:12:
error: unused variable 'NumRegs' [-Werror,-Wunused-variable]
unsigned NumRegs = PendingMembers.size();
^
1 error generated.
Commit: fcabb53f0c349885167ea3d0e53915e6c42271a7
https://github.com/llvm/llvm-project/commit/fcabb53f0c349885167ea3d0e53915e6c42271a7
Author: Abinaya Saravanan <quic_asaravan at quicinc.com>
Date: 2025-07-17 (Thu, 17 Jul 2025)
Changed paths:
M llvm/lib/Target/Hexagon/HexagonISelDAGToDAG.cpp
A llvm/test/CodeGen/Hexagon/mpy-operand-hoist.ll
Log Message:
-----------
[HEXAGON] Add AssertSext in sign-extended mpy (#149061)
The pattern i32xi32->i64, should be matched to the sign-extended
multiply op, instead of explicit sign- extension of the operands
followed by non-widening multiply (this takes 4 operations instead of
one). Currently, if one of the operands of multiply inside a loop is a
constant, the sign-extension of this constant is hoisted out of the loop
by LICM pass and this pattern is not matched by the ISEL.
This change handles multiply operand with Opcode of the type AssertSext
which is seen when the sign-extension is hoisted out-of the loop.
Modifies the DetectUseSxtw() to check for this.
Commit: 60ae9c9c632dec978e71d1d3ab3c3d18eca16c77
https://github.com/llvm/llvm-project/commit/60ae9c9c632dec978e71d1d3ab3c3d18eca16c77
Author: Alexey Bataev <a.bataev at outlook.com>
Date: 2025-07-17 (Thu, 17 Jul 2025)
Changed paths:
M llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
M llvm/test/Transforms/SLPVectorizer/X86/matched-nodes-updated.ll
Log Message:
-----------
[SLP]Do not consider non-profitable loads slices
If all slices are small and end up with strided or even vectorization
states, better to not consider these candidates for the vectorization
and try to vectorize the whole bunch as gathered loads.
Reviewers: hiraditya, RKSimon, HanKuanChen
Reviewed By: RKSimon, HanKuanChen
Pull Request: https://github.com/llvm/llvm-project/pull/149209
Commit: 2b3a410f5bc8358a9e8594331d70c9c5d59633d8
https://github.com/llvm/llvm-project/commit/2b3a410f5bc8358a9e8594331d70c9c5d59633d8
Author: Ryotaro Kasuga <kasuga.ryotaro at fujitsu.com>
Date: 2025-07-17 (Thu, 17 Jul 2025)
Changed paths:
M llvm/lib/Analysis/DependenceAnalysis.cpp
M llvm/test/Analysis/DependenceAnalysis/DifferentOffsets.ll
M llvm/test/Analysis/DependenceAnalysis/MIVCheckConst.ll
Log Message:
-----------
[DA] Check element size when analyzing deps between same instruction (#148813)
DependenceAnalysis checks whether the given addresses are divisible by
the element size of corresponding load/store instructions. However, this
check was only executed when the two instructions (Src and Dst) are
different. We must also perform the same check when Src and Dst are the
same instruction.
Fix the test added in #147715.
Commit: 145b6cdffaf6711a5b7ad191444ab3e5d97b8992
https://github.com/llvm/llvm-project/commit/145b6cdffaf6711a5b7ad191444ab3e5d97b8992
Author: Kristof Beyls <kristof.beyls at arm.com>
Date: 2025-07-17 (Thu, 17 Jul 2025)
Changed paths:
M llvm/docs/Security.rst
Log Message:
-----------
Improve description of what is considered a security issue (#147035)
This patch improves the description of what the LLVM project considers a
security issue, and what not.
This patch is based on the RFC discussion in
https://discourse.llvm.org/t/improving-documentation-of-what-is-considered-a-security-issue-in-llvm/86714
Commit: a6b5ece75e8289e93ed8233eae186c74c58e4355
https://github.com/llvm/llvm-project/commit/a6b5ece75e8289e93ed8233eae186c74c58e4355
Author: Shilei Tian <i at tianshilei.me>
Date: 2025-07-17 (Thu, 17 Jul 2025)
Changed paths:
M clang/include/clang/Basic/BuiltinsAMDGPU.def
M clang/lib/CodeGen/TargetBuiltins/AMDGPU.cpp
M clang/test/CodeGenOpenCL/builtins-amdgcn-gfx1250.cl
M llvm/lib/Target/AMDGPU/VOP1Instructions.td
M llvm/test/CodeGen/AMDGPU/bf16-math.ll
A llvm/test/CodeGen/AMDGPU/llvm.amdgcn.exp.bf16.ll
A llvm/test/CodeGen/AMDGPU/llvm.exp2.bf16.ll
M llvm/test/MC/AMDGPU/gfx1250_asm_vop1-fake16.s
M llvm/test/MC/AMDGPU/gfx1250_asm_vop1.s
M llvm/test/MC/AMDGPU/gfx1250_asm_vop1_dpp16-fake16.s
M llvm/test/MC/AMDGPU/gfx1250_asm_vop1_dpp16.s
M llvm/test/MC/AMDGPU/gfx1250_asm_vop1_dpp8-fake16.s
M llvm/test/MC/AMDGPU/gfx1250_asm_vop1_dpp8.s
M llvm/test/MC/AMDGPU/gfx1250_asm_vop3_from_vop1-fake16.s
M llvm/test/MC/AMDGPU/gfx1250_asm_vop3_from_vop1.s
M llvm/test/MC/AMDGPU/gfx1250_asm_vop3_from_vop1_dpp16-fake16.s
M llvm/test/MC/AMDGPU/gfx1250_asm_vop3_from_vop1_dpp16.s
M llvm/test/MC/AMDGPU/gfx1250_asm_vop3_from_vop1_dpp8-fake16.s
M llvm/test/MC/AMDGPU/gfx1250_asm_vop3_from_vop1_dpp8.s
M llvm/test/MC/Disassembler/AMDGPU/gfx1250_dasm_vop1.txt
M llvm/test/MC/Disassembler/AMDGPU/gfx1250_dasm_vop1_dpp16.txt
M llvm/test/MC/Disassembler/AMDGPU/gfx1250_dasm_vop1_dpp8.txt
M llvm/test/MC/Disassembler/AMDGPU/gfx1250_dasm_vop3_from_vop1.txt
M llvm/test/MC/Disassembler/AMDGPU/gfx1250_dasm_vop3_from_vop1_dpp16.txt
M llvm/test/MC/Disassembler/AMDGPU/gfx1250_dasm_vop3_from_vop1_dpp8.txt
Log Message:
-----------
[AMDGPU] Add support for `v_exp_bf16` on gfx1250 (#149229)
Co-authored-by: Mekhanoshin, Stanislav <Stanislav.Mekhanoshin at amd.com>
Commit: a102342990231f8558361da68e5df92c7b1c737d
https://github.com/llvm/llvm-project/commit/a102342990231f8558361da68e5df92c7b1c737d
Author: Shilei Tian <i at tianshilei.me>
Date: 2025-07-17 (Thu, 17 Jul 2025)
Changed paths:
M clang/include/clang/Basic/BuiltinsAMDGPU.def
M clang/lib/CodeGen/TargetBuiltins/AMDGPU.cpp
M clang/test/CodeGenOpenCL/builtins-amdgcn-gfx1250.cl
M llvm/lib/Target/AMDGPU/VOP1Instructions.td
A llvm/test/CodeGen/AMDGPU/llvm.amdgcn.sin.bf16.ll
M llvm/test/MC/AMDGPU/gfx1250_asm_vop1-fake16.s
M llvm/test/MC/AMDGPU/gfx1250_asm_vop1.s
M llvm/test/MC/AMDGPU/gfx1250_asm_vop1_dpp16-fake16.s
M llvm/test/MC/AMDGPU/gfx1250_asm_vop1_dpp16.s
M llvm/test/MC/AMDGPU/gfx1250_asm_vop1_dpp8-fake16.s
M llvm/test/MC/AMDGPU/gfx1250_asm_vop1_dpp8.s
M llvm/test/MC/AMDGPU/gfx1250_asm_vop3_from_vop1-fake16.s
M llvm/test/MC/AMDGPU/gfx1250_asm_vop3_from_vop1.s
M llvm/test/MC/AMDGPU/gfx1250_asm_vop3_from_vop1_dpp16-fake16.s
M llvm/test/MC/AMDGPU/gfx1250_asm_vop3_from_vop1_dpp16.s
M llvm/test/MC/AMDGPU/gfx1250_asm_vop3_from_vop1_dpp8-fake16.s
M llvm/test/MC/AMDGPU/gfx1250_asm_vop3_from_vop1_dpp8.s
M llvm/test/MC/Disassembler/AMDGPU/gfx1250_dasm_vop1.txt
M llvm/test/MC/Disassembler/AMDGPU/gfx1250_dasm_vop1_dpp16.txt
M llvm/test/MC/Disassembler/AMDGPU/gfx1250_dasm_vop1_dpp8.txt
M llvm/test/MC/Disassembler/AMDGPU/gfx1250_dasm_vop3_from_vop1.txt
M llvm/test/MC/Disassembler/AMDGPU/gfx1250_dasm_vop3_from_vop1_dpp16.txt
M llvm/test/MC/Disassembler/AMDGPU/gfx1250_dasm_vop3_from_vop1_dpp8.txt
Log Message:
-----------
[AMDGPU] Add support for `v_sin_bf16` on gfx1250 (#149241)
Co-authored-by: Mekhanoshin, Stanislav <Stanislav.Mekhanoshin at amd.com>
Commit: 359dca0dad72d11e41e08136bc6c6cca3f22f038
https://github.com/llvm/llvm-project/commit/359dca0dad72d11e41e08136bc6c6cca3f22f038
Author: Jay Foad <jay.foad at amd.com>
Date: 2025-07-17 (Thu, 17 Jul 2025)
Changed paths:
M llvm/lib/Target/AMDGPU/SIInsertWaitcnts.cpp
Log Message:
-----------
[AMDGPU] Move class WaitcntBrackets after class SIInsertWaitcnts. NFC.
This is a prerequisite for "[AMDGPU] Move common fields out of WaitcntBrackets. NFC. (#148864)"
Commit: 935fd986474fa2b6fe9e424ffd5d8cbc875151be
https://github.com/llvm/llvm-project/commit/935fd986474fa2b6fe9e424ffd5d8cbc875151be
Author: George Burgess IV <george.burgess.iv at gmail.com>
Date: 2025-07-17 (Thu, 17 Jul 2025)
Changed paths:
M llvm/docs/GettingInvolved.rst
Log Message:
-----------
[Docs] remove beginner office hours from GettingInvolved (#149160)
These were turned down at the beginning of this year; thanks to the
folks on
https://discourse.llvm.org/t/is-the-beginner-office-hours-still-running/87398/2
for flagging this!
---
N.B., I tried testing via `ninja doxygen-llvm`, but that didn't
terminate on my machine within 30mins (either with or without this
patch). I assume it's some local config bug on my end, but it happened
on `main` and `main~1000`, so I'm not sure how to test.
Since the change is pretty trivial, still comfortable uploading for
review.
Commit: 4166df2073b6b3e5c7ab0c25d9bc73980b50ea31
https://github.com/llvm/llvm-project/commit/4166df2073b6b3e5c7ab0c25d9bc73980b50ea31
Author: Piotr Fusik <p.fusik at samsung.com>
Date: 2025-07-17 (Thu, 17 Jul 2025)
Changed paths:
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int.ll
M llvm/test/CodeGen/RISCV/rvv/vminu-sdnode.ll
Log Message:
-----------
[RISCV][test] Add tests for vector subtraction if above threshold
Commit: fc5c5a934d2560559221bcb334b14ef4aa96a2dd
https://github.com/llvm/llvm-project/commit/fc5c5a934d2560559221bcb334b14ef4aa96a2dd
Author: jyli0116 <yu.li at arm.com>
Date: 2025-07-17 (Thu, 17 Jul 2025)
Changed paths:
M llvm/include/llvm/CodeGen/GlobalISel/CombinerHelper.h
M llvm/include/llvm/Target/GlobalISel/Combine.td
M llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp
M llvm/test/CodeGen/AArch64/rem-by-const.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/srem.i32.ll
Log Message:
-----------
[GlobalISel] Allow expansion of srem by constant in prelegalizer (#148845)
This patch allows srem by a constant to be expanded more efficiently to
avoid the need for expensive sdiv instructions. This is the last part of
the patches which fixes #118090
Commit: 66da9f38f374e786b2f1c0ecdab0b651c94c4f27
https://github.com/llvm/llvm-project/commit/66da9f38f374e786b2f1c0ecdab0b651c94c4f27
Author: Marco Elver <elver at google.com>
Date: 2025-07-17 (Thu, 17 Jul 2025)
Changed paths:
M llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
M llvm/test/CodeGen/X86/pcsections-atomics.ll
Log Message:
-----------
[SelectionDAG] Fix copyExtraInfo where new node has entry as operand (#149307)
Add special case handling where a new replacement node has the entry
node as an operand i.e. does not depend on any other nodes.
This can be observed with the existing X86/pcsections-atomics.ll test
case when targeting Haswell, where certain 128-bit atomics are
transformed into arch-specific instructions, with some operands having
no other dependencies.
Commit: 0f71424280af9e3293ed481399b2b53ca708cd15
https://github.com/llvm/llvm-project/commit/0f71424280af9e3293ed481399b2b53ca708cd15
Author: Craig Topper <craig.topper at sifive.com>
Date: 2025-07-17 (Thu, 17 Jul 2025)
Changed paths:
M llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
M llvm/test/CodeGen/RISCV/xqcisls.ll
M llvm/test/CodeGen/RISCV/xtheadmemidx.ll
Log Message:
-----------
[RISCV] Teach SelectAddrRegRegScale that ADD is commutable. (#149231)
Commit: ab25de7dec2af661b66b23b9794291f2fd81b6bc
https://github.com/llvm/llvm-project/commit/ab25de7dec2af661b66b23b9794291f2fd81b6bc
Author: Jay Foad <jay.foad at amd.com>
Date: 2025-07-17 (Thu, 17 Jul 2025)
Changed paths:
M llvm/lib/Target/AMDGPU/SIInsertWaitcnts.cpp
Log Message:
-----------
[AMDGPU] Move common fields out of WaitcntBrackets. NFC. (#148864)
WaitcntBrackets holds per-basic-block information about the state of
wait counters. It also held a bunch of fields that are constant
throughout a run of the pass. This patch moves them out into the
SIInsertWaitcnts class, for better logical separation and to save a tiny
bit of memory.
Commit: 96a7e954e1501239d1fc4bd6eba60428bd6609f7
https://github.com/llvm/llvm-project/commit/96a7e954e1501239d1fc4bd6eba60428bd6609f7
Author: Kazu Hirata <kazu at google.com>
Date: 2025-07-17 (Thu, 17 Jul 2025)
Changed paths:
M clang/lib/Sema/SemaTemplateDeduction.cpp
Log Message:
-----------
[Sema] Remove unnecessary casts (NFC) (#149253)
getParam already returns NamedDecl *.
Commit: 7fa48ce547ef9e0516564eca9c375109e83f2f71
https://github.com/llvm/llvm-project/commit/7fa48ce547ef9e0516564eca9c375109e83f2f71
Author: Kazu Hirata <kazu at google.com>
Date: 2025-07-17 (Thu, 17 Jul 2025)
Changed paths:
M llvm/lib/Target/AMDGPU/SILoadStoreOptimizer.cpp
Log Message:
-----------
[AMDGPU] Remove an unnecessary cast (NFC) (#149254)
getTargetLowering() already returns const SITargetLowering *.
Commit: 96bde11e307e53a1263ab6088f172716db7cb0d8
https://github.com/llvm/llvm-project/commit/96bde11e307e53a1263ab6088f172716db7cb0d8
Author: Kazu Hirata <kazu at google.com>
Date: 2025-07-17 (Thu, 17 Jul 2025)
Changed paths:
M llvm/include/llvm/TargetParser/Host.h
M llvm/lib/TargetParser/Host.cpp
Log Message:
-----------
[TargetParser] Remove const from a return type (NFC) (#149255)
getHostCPUFeatures constructs and returns a temporary instance of
StringMap<bool>. We don't need const on the return type.
Commit: 73e8ada540acbd60f916ef4b0a5a2b454c8ece44
https://github.com/llvm/llvm-project/commit/73e8ada540acbd60f916ef4b0a5a2b454c8ece44
Author: Kazu Hirata <kazu at google.com>
Date: 2025-07-17 (Thu, 17 Jul 2025)
Changed paths:
M clang/lib/Sema/AnalysisBasedWarnings.cpp
Log Message:
-----------
[Sema] Use llvm::all_of (NFC) (#149256)
We can pass a range to llvm::all_of.
Commit: 577585198637fc2ced2a4fdf20f91c58fb74c717
https://github.com/llvm/llvm-project/commit/577585198637fc2ced2a4fdf20f91c58fb74c717
Author: Kazu Hirata <kazu at google.com>
Date: 2025-07-17 (Thu, 17 Jul 2025)
Changed paths:
M llvm/include/llvm/ADT/EquivalenceClasses.h
M llvm/lib/MC/MCContext.cpp
Log Message:
-----------
[llvm] Use *Map::try_emplace (NFC) (#149257)
- try_emplace(Key) is shorter than insert({Key, nullptr}).
- try_emplace performs value initialization without value parameters.
- We overwrite values on successful insertion anyway.
While we are at it, this patch simplifies the code with structured
binding.
Commit: 756e07734b4f2aa64bd1bd5b6a29389c4c642323
https://github.com/llvm/llvm-project/commit/756e07734b4f2aa64bd1bd5b6a29389c4c642323
Author: David Spickett <david.spickett at linaro.org>
Date: 2025-07-17 (Thu, 17 Jul 2025)
Changed paths:
M lldb/test/API/python_api/type/main.cpp
Log Message:
-----------
[lldb][test] Adjust TestTypeList.py on Windows with exceptions
Since https://github.com/llvm/llvm-project/pull/148691 enabled
exceptions when compiling the tests, this test has been failing.
Much like was noted there, one of the variables disappeared
from the debug info. Giving it a non-zero size and initialising
it fixed that.
Commit: 9de32d56e4fdf08d88aca74149f5f815eb6505ec
https://github.com/llvm/llvm-project/commit/9de32d56e4fdf08d88aca74149f5f815eb6505ec
Author: Jacques Pienaar <jpienaar at google.com>
Date: 2025-07-17 (Thu, 17 Jul 2025)
Changed paths:
M clang-tools-extra/docs/ReleaseNotes.rst
Log Message:
-----------
[clang-tools-extra] Bump ReleaseNotes to 22.0.0git (#149306)
Move over change post 21.x branch cut.
Commit: 95639b75487895f7ef45c1468d4639f1544a1851
https://github.com/llvm/llvm-project/commit/95639b75487895f7ef45c1468d4639f1544a1851
Author: Aiden Grossman <aidengrossman at google.com>
Date: 2025-07-17 (Thu, 17 Jul 2025)
Changed paths:
M .ci/monolithic-linux.sh
M .ci/monolithic-windows.sh
Log Message:
-----------
[CI] Drop CLEAR_CACHE Support in monolithic-* scripts
This patch drops support for clearing the cache with the CLEAR_CACHE
environment variable. This is an artifact of the old infrastructure as
we now do not persist the cache across builds, instead redownloading the
cache directory everytime. This makes the scripts slightly simpler as we
are no longer supporting unneeded functionality.
Reviewers: Endilll, cmtice, dschuff, Keenuts, lnihlen, gburgessiv
Reviewed By: Keenuts, cmtice
Pull Request: https://github.com/llvm/llvm-project/pull/149193
Commit: a1179b69528245aaca7afa0c60bf9a8dc1ad3e6c
https://github.com/llvm/llvm-project/commit/a1179b69528245aaca7afa0c60bf9a8dc1ad3e6c
Author: Aiden Grossman <aidengrossman at google.com>
Date: 2025-07-17 (Thu, 17 Jul 2025)
Changed paths:
M clang-tools-extra/clang-doc/JSONGenerator.cpp
M clang-tools-extra/docs/ReleaseNotes.rst
M clang/docs/ClangFormatStyleOptions.rst
M clang/include/clang/Basic/BuiltinsAMDGPU.def
M clang/include/clang/Basic/BuiltinsSPIRVVK.td
M clang/include/clang/Basic/DiagnosticSemaKinds.td
M clang/include/clang/CIR/Dialect/Builder/CIRBaseBuilder.h
M clang/include/clang/CIR/Dialect/IR/CIROps.td
M clang/include/clang/CIR/MissingFeatures.h
M clang/include/clang/Format/Format.h
M clang/include/clang/Sema/Overload.h
M clang/lib/Basic/Targets/SPIR.h
M clang/lib/CIR/CodeGen/CIRGenBuilder.h
M clang/lib/CIR/CodeGen/CIRGenBuiltin.cpp
M clang/lib/CIR/CodeGen/CIRGenExprComplex.cpp
M clang/lib/CIR/CodeGen/CIRGenFunction.h
M clang/lib/CIR/Dialect/Transforms/LoweringPrepare.cpp
M clang/lib/CIR/Lowering/DirectToLLVM/LowerToLLVM.cpp
M clang/lib/CIR/Lowering/DirectToLLVM/LowerToLLVM.h
M clang/lib/CodeGen/CGDebugInfo.cpp
M clang/lib/CodeGen/CGLoopInfo.cpp
M clang/lib/CodeGen/TargetBuiltins/AMDGPU.cpp
M clang/lib/CodeGen/TargetBuiltins/SPIR.cpp
M clang/lib/Format/Format.cpp
M clang/lib/Headers/hlsl/hlsl_intrinsic_helpers.h
M clang/lib/Headers/hlsl/hlsl_intrinsics.h
M clang/lib/Sema/AnalysisBasedWarnings.cpp
M clang/lib/Sema/SemaOpenACC.cpp
M clang/lib/Sema/SemaOverload.cpp
M clang/lib/Sema/SemaSPIRV.cpp
M clang/lib/Sema/SemaTemplateDeduction.cpp
M clang/test/CIR/CodeGen/builtin_bit.cpp
A clang/test/CIR/CodeGen/complex-unary.cpp
M clang/test/CXX/drs/cwg8xx.cpp
M clang/test/CXX/module/dcl.dcl/dcl.module/dcl.module.interface/p1.cppm
M clang/test/CXX/module/module.interface/p1.cpp
M clang/test/CodeGen/PowerPC/builtins-ppc-fpconstrained.c
M clang/test/CodeGen/new-pass-manager-opt-bisect.c
A clang/test/CodeGen/null-sanitizer-debug-info-regression.cpp
M clang/test/CodeGenCXX/pragma-loop.cpp
A clang/test/CodeGenHLSL/builtins/refract.hlsl
M clang/test/CodeGenOpenCL/builtins-amdgcn-gfx1250.cl
A clang/test/CodeGenOpenCL/scoped-atomic.cl
A clang/test/CodeGenSPIRV/Builtins/refract.c
M clang/test/Driver/frame-pointer-elim.c
M clang/test/Modules/cxx20-10-2-ex1.cpp
M clang/test/Modules/cxx20-export-import.cpp
M clang/test/Modules/cxx20-import-diagnostics-a.cpp
M clang/test/Modules/export-in-non-modules.cpp
M clang/test/SemaCXX/overload-resolution-deferred-templates.cpp
A clang/test/SemaHLSL/BuiltIns/refract-errors.hlsl
A clang/test/SemaOpenACC/private_firstprivate_reduction_required_ops.cpp
A clang/test/SemaSPIRV/BuiltIns/refract-errors.c
M clang/tools/libclang/libclang.map
M clang/unittests/Format/ConfigParseTest.cpp
M clang/unittests/Format/SortIncludesTest.cpp
M compiler-rt/lib/scudo/standalone/tests/common_test.cpp
M compiler-rt/test/lit.common.cfg.py
M flang-rt/include/flang-rt/runtime/non-tbp-dio.h
M flang-rt/include/flang-rt/runtime/type-info.h
M flang-rt/lib/runtime/derived.cpp
M flang-rt/lib/runtime/descriptor-io.cpp
M flang-rt/lib/runtime/extensions.cpp
M flang-rt/lib/runtime/non-tbp-dio.cpp
M flang-rt/lib/runtime/type-info.cpp
M flang/docs/Intrinsics.md
A flang/docs/ParallelMultiImageFortranRuntime.md
M flang/docs/index.md
M flang/include/flang/Optimizer/Builder/IntrinsicCall.h
M flang/include/flang/Parser/message.h
M flang/include/flang/Runtime/extensions.h
M flang/include/flang/Semantics/runtime-type-info.h
M flang/lib/Frontend/FrontendAction.cpp
M flang/lib/Lower/ConvertVariable.cpp
M flang/lib/Lower/IO.cpp
M flang/lib/Optimizer/Builder/IntrinsicCall.cpp
M flang/lib/Optimizer/CodeGen/LowerRepackArrays.cpp
M flang/lib/Optimizer/Transforms/CUFDeviceGlobal.cpp
M flang/lib/Parser/message.cpp
M flang/lib/Semantics/check-declarations.cpp
M flang/lib/Semantics/expression.cpp
M flang/lib/Semantics/runtime-type-info.cpp
M flang/lib/Semantics/semantics.cpp
M flang/lib/Semantics/tools.cpp
M flang/module/__fortran_type_info.f90
M flang/module/cudadevice.f90
A flang/test/Driver/fatal-errors-warnings.f90
M flang/test/Fir/CUDA/cuda-device-global.f90
M flang/test/Lower/CUDA/cuda-device-proc.cuf
M flang/test/Lower/io-derived-type.f90
M flang/test/Lower/namelist.f90
M flang/test/Lower/volatile-openmp.f90
A flang/test/Semantics/bind-c18.f90
A flang/test/Semantics/bug148559.f90
A flang/test/Semantics/bug148675.f90
M flang/test/Semantics/typeinfo01.f90
M flang/test/Semantics/typeinfo02.f90
M flang/test/Semantics/typeinfo09.f90
M flang/test/Semantics/typeinfo13.f90
M flang/test/Transforms/lower-repack-arrays.fir
M libc/fuzzing/math/acos_fuzz.cpp
M libc/fuzzing/math/asin_fuzz.cpp
M libc/fuzzing/math/cos_fuzz.cpp
M libc/fuzzing/math/exp10_fuzz.cpp
M libc/fuzzing/math/exp2_fuzz.cpp
M libc/fuzzing/math/exp_fuzz.cpp
M libc/fuzzing/math/expm1_fuzz.cpp
M libc/fuzzing/math/log10_fuzz.cpp
M libc/fuzzing/math/log1p_fuzz.cpp
M libc/fuzzing/math/log2_fuzz.cpp
M libc/fuzzing/math/log_fuzz.cpp
M libc/fuzzing/math/sin_fuzz.cpp
M libc/fuzzing/math/sincos_fuzz.cpp
M libc/fuzzing/math/sqrt_fuzz.cpp
M libc/fuzzing/math/tan_fuzz.cpp
M libc/shared/math.h
A libc/shared/math/exp10.h
M libc/src/__support/FPUtil/PolyEval.h
M libc/src/__support/FPUtil/double_double.h
M libc/src/__support/math/CMakeLists.txt
A libc/src/__support/math/exp10.h
M libc/src/math/generic/CMakeLists.txt
M libc/src/math/generic/exp10.cpp
M libc/src/string/memory_utils/CMakeLists.txt
A libc/src/string/memory_utils/arm/common.h
M libc/src/string/memory_utils/arm/inline_memcpy.h
A libc/src/string/memory_utils/arm/inline_memset.h
M libc/src/string/memory_utils/inline_memset.h
M libclc/CMakeLists.txt
M libcxx/include/CMakeLists.txt
M libcxx/include/__format/range_default_formatter.h
A libcxx/include/__format/range_format.h
M libcxx/include/module.modulemap.in
M libcxx/include/string
A libcxx/test/extensions/libcxx/localization/lit.local.cfg
A libcxx/test/extensions/libcxx/localization/locale.convenience/conversions/conversions.string/ctor_move.pass.cpp
R libcxx/test/libcxx/localization/locales/locale.convenience/conversions/conversions.string/ctor_move.pass.cpp
R libcxx/test/libcxx/memory/shared_ptr_array.pass.cpp
R libcxx/test/libcxx/minimal_cxx11_configuration.pass.cpp
R libcxx/test/libcxx/numerics/c.math/fdelayed-template-parsing.pass.cpp
R libcxx/test/libcxx/numerics/rand/rand.req.urng/valid_int_type.verify.cpp
R libcxx/test/libcxx/numerics/rand/rand.req.urng/valid_real_type.verify.cpp
A libcxx/test/std/numerics/c.math/fdelayed-template-parsing.pass.cpp
A libcxx/test/std/numerics/rand/rand.req/rand.req.urng/valid_int_type.verify.cpp
A libcxx/test/std/numerics/rand/rand.req/rand.req.urng/valid_real_type.verify.cpp
A libcxx/test/std/utilities/memory/util.smartptr/util.smartptr.shared/util.smartptr.shared.create/shared_ptr_array.pass.cpp
M libcxx/test/std/utilities/meta/meta.unary/meta.unary.comp/is_bounded_array.pass.cpp
M libcxx/test/std/utilities/meta/meta.unary/meta.unary.prop/has_unique_object_representations.compile.pass.cpp
M libcxx/test/std/utilities/template.bitset/bitset.members/to_ullong.pass.cpp
M libcxx/utils/ci/Dockerfile
M libcxx/utils/ci/docker-compose.yml
M lld/ELF/Relocations.cpp
M lld/MachO/Arch/ARM64.cpp
M lld/MachO/CMakeLists.txt
A lld/MachO/LinkerOptimizationHints.cpp
A lld/MachO/LinkerOptimizationHints.h
M lld/MachO/Target.h
M lld/MachO/Writer.cpp
A lld/test/MachO/loh-arm64-32.s
M lldb/docs/resources/build.rst
M lldb/docs/resources/qemu-testing.rst
M lldb/docs/use/mcp.md
M lldb/source/Commands/CommandObjectDWIMPrint.cpp
M lldb/source/Commands/CommandObjectExpression.cpp
M lldb/source/Interpreter/CommandInterpreter.cpp
M lldb/test/API/commands/frame/var-dil/basics/ArraySubscript/TestFrameVarDILArraySubscript.py
M lldb/test/API/functionalities/data-formatter/data-formatter-disabling/TestDataFormatterDisabling.py
M lldb/test/API/lang/cpp/template/TestTemplateArgs.py
M lldb/test/API/python_api/type/main.cpp
A lldb/test/Shell/Settings/TestChildCountTruncation.test
M llvm/CMakeLists.txt
M llvm/docs/GettingInvolved.rst
M llvm/docs/HowToUpdateDebugInfo.rst
M llvm/docs/LangRef.rst
M llvm/docs/ReleaseNotes.md
M llvm/docs/Security.rst
M llvm/include/llvm/ADT/EquivalenceClasses.h
M llvm/include/llvm/Analysis/VectorUtils.h
M llvm/include/llvm/CodeGen/GlobalISel/CombinerHelper.h
M llvm/include/llvm/CodeGen/TargetLowering.h
M llvm/include/llvm/IR/IntrinsicsSPIRV.td
M llvm/include/llvm/IR/OptBisect.h
M llvm/include/llvm/IR/RuntimeLibcalls.td
M llvm/include/llvm/MC/MCAssembler.h
M llvm/include/llvm/MC/MCELFStreamer.h
M llvm/include/llvm/MC/MCObjectStreamer.h
M llvm/include/llvm/MC/MCStreamer.h
M llvm/include/llvm/Object/ELFObjectFile.h
M llvm/include/llvm/Pass.h
M llvm/include/llvm/Target/GlobalISel/Combine.td
M llvm/include/llvm/TargetParser/Host.h
M llvm/include/llvm/TargetParser/Triple.h
M llvm/lib/Analysis/DependenceAnalysis.cpp
M llvm/lib/Analysis/VectorUtils.cpp
M llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp
M llvm/lib/CodeGen/GlobalMergeFunctions.cpp
M llvm/lib/CodeGen/InterleavedAccessPass.cpp
M llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
M llvm/lib/CodeGen/StackProtector.cpp
M llvm/lib/CodeGen/TargetInstrInfo.cpp
M llvm/lib/IR/OptBisect.cpp
M llvm/lib/IR/Pass.cpp
M llvm/lib/IR/Verifier.cpp
M llvm/lib/MC/MCAsmStreamer.cpp
M llvm/lib/MC/MCAssembler.cpp
M llvm/lib/MC/MCContext.cpp
M llvm/lib/MC/MCELFStreamer.cpp
M llvm/lib/MC/MCObjectStreamer.cpp
M llvm/lib/MC/MCParser/AsmParser.cpp
M llvm/lib/Object/RelocationResolver.cpp
M llvm/lib/Passes/StandardInstrumentations.cpp
M llvm/lib/TableGen/TGLexer.cpp
M llvm/lib/Target/AArch64/AArch64ExpandPseudoInsts.cpp
M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
M llvm/lib/Target/AArch64/AArch64ISelLowering.h
M llvm/lib/Target/AArch64/AArch64InstrInfo.cpp
M llvm/lib/Target/AArch64/MCTargetDesc/AArch64ELFStreamer.cpp
M llvm/lib/Target/AMDGPU/AMDGPU.td
M llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp
M llvm/lib/Target/AMDGPU/AMDGPUInsertDelayAlu.cpp
M llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
M llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.h
M llvm/lib/Target/AMDGPU/FLATInstructions.td
M llvm/lib/Target/AMDGPU/GCNHazardRecognizer.cpp
M llvm/lib/Target/AMDGPU/GCNHazardRecognizer.h
M llvm/lib/Target/AMDGPU/GCNSchedStrategy.cpp
M llvm/lib/Target/AMDGPU/GCNSubtarget.h
M llvm/lib/Target/AMDGPU/SIInsertWaitcnts.cpp
M llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
M llvm/lib/Target/AMDGPU/SIInstrInfo.h
M llvm/lib/Target/AMDGPU/SIInstructions.td
M llvm/lib/Target/AMDGPU/SILoadStoreOptimizer.cpp
M llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp
M llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.h
M llvm/lib/Target/AMDGPU/VOP1Instructions.td
M llvm/lib/Target/AMDGPU/VOP3Instructions.td
M llvm/lib/Target/Hexagon/HexagonISelDAGToDAG.cpp
M llvm/lib/Target/LoongArch/LoongArchFloat32InstrInfo.td
M llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp
M llvm/lib/Target/LoongArch/LoongArchLASXInstrInfo.td
M llvm/lib/Target/LoongArch/LoongArchLSXInstrInfo.td
M llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp
M llvm/lib/Target/Mips/MipsAsmPrinter.cpp
M llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
M llvm/lib/Target/RISCV/RISCVISelLowering.h
M llvm/lib/Target/RISCV/RISCVInterleavedAccess.cpp
M llvm/lib/Target/RISCV/RISCVSchedSpacemitX60.td
M llvm/lib/Target/RISCV/RISCVVLOptimizer.cpp
M llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp
M llvm/lib/Target/X86/X86CallingConv.cpp
M llvm/lib/Target/X86/X86CallingConv.td
M llvm/lib/Target/X86/X86ISelLoweringCall.cpp
M llvm/lib/TargetParser/Host.cpp
M llvm/lib/TargetParser/Triple.cpp
M llvm/lib/Transforms/Coroutines/CoroFrame.cpp
M llvm/lib/Transforms/InstCombine/InstCombineSelect.cpp
M llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
M llvm/lib/Transforms/Vectorize/VPlan.h
M llvm/test/Analysis/DependenceAnalysis/DifferentOffsets.ll
M llvm/test/Analysis/DependenceAnalysis/MIVCheckConst.ll
A llvm/test/CodeGen/AArch64/cgdata-no-merge-unnamed.ll
M llvm/test/CodeGen/AArch64/machine-outliner-safe-range-in-middle.mir
M llvm/test/CodeGen/AArch64/rem-by-const.ll
M llvm/test/CodeGen/AArch64/sve-pseudos-expand-undef.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-bswap.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fshr.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/srem.i32.ll
A llvm/test/CodeGen/AMDGPU/bf16-math.ll
M llvm/test/CodeGen/AMDGPU/branch-folding-implicit-def-subreg.ll
A llvm/test/CodeGen/AMDGPU/flat-saddr-load.ll
A llvm/test/CodeGen/AMDGPU/flat-saddr-store.ll
A llvm/test/CodeGen/AMDGPU/insert-delay-alu-wmma-xdl.mir
M llvm/test/CodeGen/AMDGPU/llc-pipeline-npm.ll
A llvm/test/CodeGen/AMDGPU/llvm.amdgcn.exp.bf16.ll
A llvm/test/CodeGen/AMDGPU/llvm.amdgcn.log.bf16.ll
A llvm/test/CodeGen/AMDGPU/llvm.amdgcn.rsq.bf16.ll
A llvm/test/CodeGen/AMDGPU/llvm.amdgcn.sin.bf16.ll
A llvm/test/CodeGen/AMDGPU/llvm.exp2.bf16.ll
A llvm/test/CodeGen/AMDGPU/llvm.log2.bf16.ll
M llvm/test/CodeGen/AMDGPU/llvm.sqrt.bf16.ll
A llvm/test/CodeGen/AMDGPU/regalloc-undef-copy-fold.mir
A llvm/test/CodeGen/AMDGPU/select-cmp-shared-constant-fp.ll
A llvm/test/CodeGen/AMDGPU/select-cmp-shared-constant-int.ll
A llvm/test/CodeGen/AMDGPU/trans-coexecution-hazard.mir
A llvm/test/CodeGen/Hexagon/mpy-operand-hoist.ll
M llvm/test/CodeGen/LoongArch/lasx/build-vector.ll
M llvm/test/CodeGen/LoongArch/lasx/ir-instruction/bitcast-extract-element.ll
M llvm/test/CodeGen/LoongArch/lasx/ir-instruction/fix-xvshuf.ll
M llvm/test/CodeGen/LoongArch/lasx/ir-instruction/insert-bitcast-element.ll
M llvm/test/CodeGen/LoongArch/lasx/ir-instruction/insert-extract-element.ll
M llvm/test/CodeGen/LoongArch/lasx/ir-instruction/insert-extract-pair-elements.ll
M llvm/test/CodeGen/LoongArch/lasx/ir-instruction/insertelement.ll
A llvm/test/CodeGen/LoongArch/llvm.exp10.ll
M llvm/test/CodeGen/LoongArch/lsx/ir-instruction/bitcast-extract-element.ll
M llvm/test/CodeGen/LoongArch/lsx/ir-instruction/insert-bitcast-element.ll
M llvm/test/CodeGen/LoongArch/lsx/ir-instruction/insert-extract-element.ll
A llvm/test/CodeGen/PowerPC/spe-vsx-incompatibility.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-deinterleave-load.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int.ll
M llvm/test/CodeGen/RISCV/rvv/vl-opt-instrs.ll
M llvm/test/CodeGen/RISCV/rvv/vl-opt-op-info.mir
M llvm/test/CodeGen/RISCV/rvv/vminu-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vp-vector-interleaved-access.ll
M llvm/test/CodeGen/RISCV/rvv/vxrm-insert-out-of-loop.ll
M llvm/test/CodeGen/RISCV/xandesbfhcvt.ll
M llvm/test/CodeGen/RISCV/xqcisls.ll
M llvm/test/CodeGen/RISCV/xtheadmemidx.ll
A llvm/test/CodeGen/SPIRV/hlsl-intrinsics/refract.ll
A llvm/test/CodeGen/SPIRV/opencl/refract-error.ll
M llvm/test/CodeGen/X86/abds-neg.ll
M llvm/test/CodeGen/X86/abds.ll
M llvm/test/CodeGen/X86/abdu-neg.ll
M llvm/test/CodeGen/X86/abdu.ll
M llvm/test/CodeGen/X86/abs.ll
M llvm/test/CodeGen/X86/add-sub-bool.ll
M llvm/test/CodeGen/X86/arg-copy-elide.ll
M llvm/test/CodeGen/X86/avx512fp16-cvt.ll
M llvm/test/CodeGen/X86/bitselect.ll
M llvm/test/CodeGen/X86/bsf.ll
M llvm/test/CodeGen/X86/bsr.ll
M llvm/test/CodeGen/X86/bswap-wide-int.ll
M llvm/test/CodeGen/X86/div-rem-pair-recomposition-signed.ll
M llvm/test/CodeGen/X86/div-rem-pair-recomposition-unsigned.ll
M llvm/test/CodeGen/X86/fp128-cast-strict.ll
M llvm/test/CodeGen/X86/fp128-cast.ll
M llvm/test/CodeGen/X86/fp128-libcalls-strict.ll
M llvm/test/CodeGen/X86/fp128-libcalls.ll
M llvm/test/CodeGen/X86/fshl.ll
M llvm/test/CodeGen/X86/fshr.ll
M llvm/test/CodeGen/X86/funnel-shift.ll
M llvm/test/CodeGen/X86/i128-add.ll
M llvm/test/CodeGen/X86/i128-fp128-abi.ll
M llvm/test/CodeGen/X86/i128-sdiv.ll
M llvm/test/CodeGen/X86/i128-udiv.ll
M llvm/test/CodeGen/X86/iabs.ll
M llvm/test/CodeGen/X86/icmp-shift-opt.ll
M llvm/test/CodeGen/X86/mul128.ll
M llvm/test/CodeGen/X86/neg-abs.ll
M llvm/test/CodeGen/X86/pcsections-atomics.ll
M llvm/test/CodeGen/X86/popcnt.ll
M llvm/test/CodeGen/X86/pr46004.ll
M llvm/test/CodeGen/X86/scalar-fp-to-i32.ll
M llvm/test/CodeGen/X86/scalar-fp-to-i64.ll
M llvm/test/CodeGen/X86/scmp.ll
M llvm/test/CodeGen/X86/sdiv_fix.ll
M llvm/test/CodeGen/X86/sdiv_fix_sat.ll
M llvm/test/CodeGen/X86/shift-combine.ll
M llvm/test/CodeGen/X86/shift-i128.ll
M llvm/test/CodeGen/X86/smax.ll
M llvm/test/CodeGen/X86/smin.ll
M llvm/test/CodeGen/X86/ucmp.ll
M llvm/test/CodeGen/X86/udiv_fix.ll
M llvm/test/CodeGen/X86/udiv_fix_sat.ll
M llvm/test/CodeGen/X86/umax.ll
M llvm/test/CodeGen/X86/umin.ll
M llvm/test/CodeGen/X86/umulo-128-legalisation-lowering.ll
M llvm/test/CodeGen/X86/wide-integer-cmp.ll
A llvm/test/CodeGen/X86/win32-int-runtime-libcalls.ll
M llvm/test/MC/AArch64/directives-case_insensitive.s
M llvm/test/MC/AArch64/reloc-directive-err.s
M llvm/test/MC/AArch64/reloc-directive.s
M llvm/test/MC/AMDGPU/gfx10_asm_vop3.s
M llvm/test/MC/AMDGPU/gfx1250_asm_vflat.s
M llvm/test/MC/AMDGPU/gfx1250_asm_vop1-fake16.s
M llvm/test/MC/AMDGPU/gfx1250_asm_vop1.s
M llvm/test/MC/AMDGPU/gfx1250_asm_vop1_dpp16-fake16.s
M llvm/test/MC/AMDGPU/gfx1250_asm_vop1_dpp16.s
M llvm/test/MC/AMDGPU/gfx1250_asm_vop1_dpp8-fake16.s
M llvm/test/MC/AMDGPU/gfx1250_asm_vop1_dpp8.s
M llvm/test/MC/AMDGPU/gfx1250_asm_vop3_from_vop1-fake16.s
M llvm/test/MC/AMDGPU/gfx1250_asm_vop3_from_vop1.s
M llvm/test/MC/AMDGPU/gfx1250_asm_vop3_from_vop1_dpp16-fake16.s
M llvm/test/MC/AMDGPU/gfx1250_asm_vop3_from_vop1_dpp16.s
M llvm/test/MC/AMDGPU/gfx1250_asm_vop3_from_vop1_dpp8-fake16.s
M llvm/test/MC/AMDGPU/gfx1250_asm_vop3_from_vop1_dpp8.s
M llvm/test/MC/AMDGPU/gfx7_err_pos.s
M llvm/test/MC/AMDGPU/gfx8_err_pos.s
M llvm/test/MC/AMDGPU/gfx9_asm_vop3_e64.s
M llvm/test/MC/AMDGPU/reloc-directive.s
M llvm/test/MC/ARM/reloc-directive-err.s
M llvm/test/MC/ARM/reloc-directive.s
M llvm/test/MC/AVR/reloc-directive-err.s
M llvm/test/MC/AVR/reloc-directive.s
M llvm/test/MC/Disassembler/AMDGPU/gfx10_vop3.txt
M llvm/test/MC/Disassembler/AMDGPU/gfx1250_dasm_vflat.txt
M llvm/test/MC/Disassembler/AMDGPU/gfx1250_dasm_vop1.txt
M llvm/test/MC/Disassembler/AMDGPU/gfx1250_dasm_vop1_dpp16.txt
M llvm/test/MC/Disassembler/AMDGPU/gfx1250_dasm_vop1_dpp8.txt
M llvm/test/MC/Disassembler/AMDGPU/gfx1250_dasm_vop3_from_vop1.txt
M llvm/test/MC/Disassembler/AMDGPU/gfx1250_dasm_vop3_from_vop1_dpp16.txt
M llvm/test/MC/Disassembler/AMDGPU/gfx1250_dasm_vop3_from_vop1_dpp8.txt
M llvm/test/MC/Disassembler/AMDGPU/gfx9_vop3.txt
M llvm/test/MC/ELF/reloc-directive.s
M llvm/test/MC/LoongArch/Relocations/reloc-directive-err.s
M llvm/test/MC/LoongArch/Relocations/reloc-directive.s
M llvm/test/MC/Mips/reloc-directive-bad-obj.s
M llvm/test/MC/Mips/reloc-directive-bad.s
M llvm/test/MC/Mips/reloc-directive-label-offset.s
M llvm/test/MC/Mips/reloc-directive.s
M llvm/test/MC/PowerPC/ppc32-reloc-directive.s
M llvm/test/MC/PowerPC/ppc64-reloc-directive.s
M llvm/test/MC/RISCV/reloc-directive-err.s
M llvm/test/MC/RISCV/reloc-directive.s
M llvm/test/MC/Sparc/Relocations/reloc-directive.s
M llvm/test/MC/SystemZ/reloc-directive.s
M llvm/test/MC/X86/reloc-directive-elf-32.s
M llvm/test/MC/X86/reloc-directive-elf-64.s
M llvm/test/MC/X86/reloc-directive.s
M llvm/test/Other/opt-bisect-new-pass-manager.ll
A llvm/test/Other/opt-disable.ll
M llvm/test/Transforms/Coroutines/coro-async-addr-lifetime-start-bug.ll
M llvm/test/Transforms/InstCombine/icmp-select.ll
A llvm/test/Transforms/InstCombine/select-fixed-zero.ll
M llvm/test/Transforms/InstCombine/select.ll
M llvm/test/Transforms/InterleavedAccess/AArch64/fixed-deinterleave-intrinsics.ll
M llvm/test/Transforms/InterleavedAccess/AArch64/scalable-deinterleave-intrinsics.ll
M llvm/test/Transforms/InterleavedAccess/AArch64/sve-deinterleave4.ll
M llvm/test/Transforms/InterleavedAccess/AArch64/sve-interleaved-accesses.ll
M llvm/test/Transforms/LoopInterchange/reductions-non-wrapped-operations.ll
M llvm/test/Transforms/SLPVectorizer/X86/matched-nodes-updated.ll
A llvm/test/Transforms/StackProtector/cross-dso-cfi-stack-chk-fail.ll
A llvm/test/Transforms/StackProtector/stack-chk-fail-alias.ll
M llvm/test/tools/llvm-mca/RISCV/SpacemitX60/atomic.s
M llvm/test/tools/llvm-mca/RISCV/SpacemitX60/floating-point.s
M llvm/test/tools/llvm-mca/RISCV/SpacemitX60/integer.s
A llvm/test/tools/llvm-mca/RISCV/SpacemitX60/rvv-arithmetic.s
A llvm/test/tools/llvm-mca/RISCV/SpacemitX60/rvv-bitwise.s
A llvm/test/tools/llvm-mca/RISCV/SpacemitX60/rvv-comparison.s
A llvm/test/tools/llvm-mca/RISCV/SpacemitX60/rvv-conversion.s
A llvm/test/tools/llvm-mca/RISCV/SpacemitX60/rvv-fma.s
A llvm/test/tools/llvm-mca/RISCV/SpacemitX60/rvv-fp.s
A llvm/test/tools/llvm-mca/RISCV/SpacemitX60/rvv-mask.s
A llvm/test/tools/llvm-mca/RISCV/SpacemitX60/rvv-minmax.s
A llvm/test/tools/llvm-mca/RISCV/SpacemitX60/rvv-mul-div.s
A llvm/test/tools/llvm-mca/RISCV/SpacemitX60/rvv-permutation.s
A llvm/test/tools/llvm-mca/RISCV/SpacemitX60/rvv-reduction.s
M llvm/test/tools/llvm-objcopy/ELF/binary-output-target.test
A llvm/test/tools/llvm-original-di-preservation/acceptance-test.test
M llvm/test/tools/llvm-original-di-preservation/basic.test
M llvm/tools/llvm-objcopy/ObjcopyOptions.cpp
M llvm/unittests/Object/ELFObjectFileTest.cpp
M llvm/utils/TableGen/Common/CodeGenRegisters.cpp
M llvm/utils/TableGen/Common/CodeGenRegisters.h
M llvm/utils/TableGen/RegisterInfoEmitter.cpp
M llvm/utils/gn/secondary/libcxx/include/BUILD.gn
M llvm/utils/gn/secondary/lld/MachO/BUILD.gn
M llvm/utils/llvm-original-di-preservation.py
M mlir/lib/Dialect/Linalg/Transforms/Vectorization.cpp
M mlir/test/Dialect/Linalg/vectorization/linalg-ops.mlir
M offload/liboffload/src/OffloadImpl.cpp
M offload/unittests/OffloadAPI/symbol/olGetSymbol.cpp
M third-party/benchmark/src/sysinfo.cc
M utils/bazel/llvm-project-overlay/libc/BUILD.bazel
Log Message:
-----------
[𝘀𝗽𝗿] changes introduced through rebase
Created using spr 1.3.4
[skip ci]
Compare: https://github.com/llvm/llvm-project/compare/08567120a4b9...a1179b695282
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