[all-commits] [llvm/llvm-project] 0f7142: [RISCV] Teach SelectAddrRegRegScale that ADD is co...

[Craig Topper via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 0f71424280af9e3293ed481399b2b53ca708cd15
      https://github.com/llvm/llvm-project/commit/0f71424280af9e3293ed481399b2b53ca708cd15
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2025-07-17 (Thu, 17 Jul 2025)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
    M llvm/test/CodeGen/RISCV/xqcisls.ll
    M llvm/test/CodeGen/RISCV/xtheadmemidx.ll

  Log Message:
  -----------
  [RISCV] Teach SelectAddrRegRegScale that ADD is commutable. (#149231)



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