[all-commits] [llvm/llvm-project] b71c9a: [RISCV] Fix issues in ORI to QC.INSBI transformati...

[Sudharsan Veeravalli via All-commits]

  Branch: refs/heads/release/21.x
  Home:   https://github.com/llvm/llvm-project
  Commit: b71c9a43664101ff46fa0a46041a238d369a7784
      https://github.com/llvm/llvm-project/commit/b71c9a43664101ff46fa0a46041a238d369a7784
  Author: Sudharsan Veeravalli <quic_svs at quicinc.com>
  Date:   2025-07-17 (Thu, 17 Jul 2025)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
    M llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td
    M llvm/test/CodeGen/RISCV/xqcibm-cto-clo-brev.ll
    M llvm/test/CodeGen/RISCV/xqcibm-insert.ll

  Log Message:
  -----------
  [RISCV] Fix issues in ORI to QC.INSBI transformation (#148809)

The transformation done in #147349 was incorrect since we were not
passing the input node of the `OR` instruction to the `QC.INSBI`
instruction leading to the generated instruction doing the wrong thing.
In order to do this we first needed to add the output register to
`QC.INSBI` as being both an input and output.

The code produced after the above fix will need a copy (mv) to preserve
the register input to the OR instruction if it has more than one use
making the transformation net neutral ( `6-byte QC.E.ORI/ORAI` vs
`2-byte C.MV + 4-byte QC.INSB`I). Avoid doing the transformation if
there is more than one use of the input register to the OR instruction.

(cherry picked from commit d67d91a9906366585162cebf292f923a3f28c8a6)



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