[all-commits] [llvm/llvm-project] dd3d26: Revert "[Support] Error if SocketPath is too long"...
Aiden Grossman via All-commits
all-commits at lists.llvm.org
Wed Jul 16 20:10:12 PDT 2025
Branch: refs/heads/users/ilovepi/clang-version-fix-libcxx
Home: https://github.com/llvm/llvm-project
Commit: dd3d26bc8973ed18a527d61a1d8e5961060f138a
https://github.com/llvm/llvm-project/commit/dd3d26bc8973ed18a527d61a1d8e5961060f138a
Author: Marina Taylor <marina_taylor at apple.com>
Date: 2025-07-16 (Wed, 16 Jul 2025)
Changed paths:
M llvm/lib/Support/raw_socket_stream.cpp
Log Message:
-----------
Revert "[Support] Error if SocketPath is too long" (#149096)
Reverts llvm/llvm-project#148903 due to bot failure
https://lab.llvm.org/buildbot/#/builders/187/builds/8162
Commit: 1754a7d5733d5305e4ec25ef0945b39d6882bb28
https://github.com/llvm/llvm-project/commit/1754a7d5733d5305e4ec25ef0945b39d6882bb28
Author: Nikita Popov <npopov at redhat.com>
Date: 2025-07-16 (Wed, 16 Jul 2025)
Changed paths:
M llvm/lib/Support/BLAKE3/blake3_neon.c
Log Message:
-----------
[Support][BLAKE3] Restore static on blake3_hash4_neon (#149046)
This was dropped in #147948 and causes symbol conflicts if libblake3 is
also linked.
Commit: 82404e3c69168b9fdb779174d3499f5f87f818d2
https://github.com/llvm/llvm-project/commit/82404e3c69168b9fdb779174d3499f5f87f818d2
Author: Kyungwoo Lee <kyulee at meta.com>
Date: 2025-07-16 (Wed, 16 Jul 2025)
Changed paths:
M llvm/lib/CodeGen/GlobalMergeFunctions.cpp
A llvm/test/CodeGen/AArch64/cgdata-no-merge-unnamed.ll
Log Message:
-----------
[CGData][GMF] Skip merging unnamed functions (#148995)
Skip merging unnamed functions to fix an assertion issue, since unnamed
functions would otherwise receive the same merged name --
https://github.com/llvm/llvm-project/blob/main/llvm/lib/CodeGen/GlobalMergeFunctions.cpp#L191
Commit: 64c273a6191bd0036deed7847d39440d36bbc604
https://github.com/llvm/llvm-project/commit/64c273a6191bd0036deed7847d39440d36bbc604
Author: Erick Velez <erickvelez7 at gmail.com>
Date: 2025-07-16 (Wed, 16 Jul 2025)
Changed paths:
M clang-tools-extra/clang-doc/JSONGenerator.cpp
Log Message:
-----------
[clang-doc] fix ASan complaints from passing RepositoryURL as reference (#148923)
Passing RepositoryURL around as an optional reference triggered
stack-use-after-return complaints.
Commit: 78b9128250c9fe5c7f9e460a27cc28c6450fd8fd
https://github.com/llvm/llvm-project/commit/78b9128250c9fe5c7f9e460a27cc28c6450fd8fd
Author: Trevor Gross <tmgross at umich.edu>
Date: 2025-07-16 (Wed, 16 Jul 2025)
Changed paths:
M llvm/docs/LangRef.rst
Log Message:
-----------
[LangRef] Document the difference between `<abi>` and `<pref>` (#147929)
Document how LLVM expects to use `<abi>` and `<pref>`, as well as the
`pref >= abi` requirement.
Commit: 6e0b0ec66ac8de046cc95080166e2012819f7d93
https://github.com/llvm/llvm-project/commit/6e0b0ec66ac8de046cc95080166e2012819f7d93
Author: Peter Klausler <pklausler at nvidia.com>
Date: 2025-07-16 (Wed, 16 Jul 2025)
Changed paths:
M flang/lib/Semantics/tools.cpp
A flang/test/Semantics/bug148559.f90
Log Message:
-----------
[flang] Fix crash in Semantics (#148706)
Allow for renaming in USE association of Cray pointers.
Fixes https://github.com/llvm/llvm-project/issues/148559.
Commit: fc7f9d795d37cd119831e77e475e4690e4120bdb
https://github.com/llvm/llvm-project/commit/fc7f9d795d37cd119831e77e475e4690e4120bdb
Author: Peter Klausler <pklausler at nvidia.com>
Date: 2025-07-16 (Wed, 16 Jul 2025)
Changed paths:
M flang/lib/Semantics/expression.cpp
A flang/test/Semantics/bug148675.f90
Log Message:
-----------
[flang] Better error message for ambiguous ASSIGNMENT(=) (#148720)
When a type-bound generic ASSIGNMENT(=) procedure is ambiguous for a
particular reference, say so, rather than claiming that no specific
procedure matched the types and ranks of the LHS and RHS.
Fixes https://github.com/llvm/llvm-project/issues/148675.
Commit: 52a46dc57f29e87a5a298ce325562fa2e3d057c9
https://github.com/llvm/llvm-project/commit/52a46dc57f29e87a5a298ce325562fa2e3d057c9
Author: Peter Klausler <pklausler at nvidia.com>
Date: 2025-07-16 (Wed, 16 Jul 2025)
Changed paths:
M flang-rt/include/flang-rt/runtime/non-tbp-dio.h
M flang-rt/include/flang-rt/runtime/type-info.h
M flang-rt/lib/runtime/derived.cpp
M flang-rt/lib/runtime/descriptor-io.cpp
M flang-rt/lib/runtime/non-tbp-dio.cpp
M flang-rt/lib/runtime/type-info.cpp
M flang/include/flang/Semantics/runtime-type-info.h
M flang/lib/Lower/IO.cpp
M flang/lib/Semantics/runtime-type-info.cpp
M flang/module/__fortran_type_info.f90
M flang/test/Lower/io-derived-type.f90
M flang/test/Lower/namelist.f90
M flang/test/Lower/volatile-openmp.f90
M flang/test/Semantics/typeinfo01.f90
M flang/test/Semantics/typeinfo02.f90
M flang/test/Semantics/typeinfo09.f90
M flang/test/Semantics/typeinfo13.f90
Log Message:
-----------
[flang] Allow -fdefault-integer-8 with defined I/O (#148927)
Defined I/O subroutines have UNIT= and IOSTAT= dummy arguments that are
required to have type INTEGER with its default kind. When that default
kind is modified via -fdefault-integer-8, calls to defined I/O
subroutines from the runtime don't work.
Add a flag to the two data structures shared between the compiler and
the runtime support library to indicate that a defined I/O subroutine
was compiled under -fdefault-integer-8. This has been done in a
compatible manner, so that existing binaries are compatible with the new
library and new binaries are compatible with the old library, unless of
course -fdefault-integer-8 is used.
Fixes https://github.com/llvm/llvm-project/issues/148638.
Commit: bbcdad1f8eab303a9d56c76a0bced7b17c6d2656
https://github.com/llvm/llvm-project/commit/bbcdad1f8eab303a9d56c76a0bced7b17c6d2656
Author: Peter Klausler <pklausler at nvidia.com>
Date: 2025-07-16 (Wed, 16 Jul 2025)
Changed paths:
M flang-rt/lib/runtime/extensions.cpp
M flang/docs/Intrinsics.md
M flang/include/flang/Runtime/extensions.h
Log Message:
-----------
[flang][runtime] MCLOCK library routine (#148960)
Add MCLOCK as an interface to std::clock().
Commit: 3de11b70620d911613a48d493048cb48bb76ec19
https://github.com/llvm/llvm-project/commit/3de11b70620d911613a48d493048cb48bb76ec19
Author: Peter Klausler <pklausler at nvidia.com>
Date: 2025-07-16 (Wed, 16 Jul 2025)
Changed paths:
M flang/lib/Semantics/check-declarations.cpp
A flang/test/Semantics/bind-c18.f90
Log Message:
-----------
[flang] Catch bad members of BIND(C) COMMON block (#148971)
Variables that can't be BIND(C), like pointers, can't be in a BIND(C)
common block, either.
Fixes https://github.com/llvm/llvm-project/issues/148922.
Commit: 4f8597f071bab5113a945bd653bec84bd820d4a3
https://github.com/llvm/llvm-project/commit/4f8597f071bab5113a945bd653bec84bd820d4a3
Author: Madhur Amilkanthwar <madhura at nvidia.com>
Date: 2025-07-16 (Wed, 16 Jul 2025)
Changed paths:
M llvm/test/Transforms/LoopInterchange/reductions-non-wrapped-operations.ll
Log Message:
-----------
[LoopInterchange] Add test for floating point math flags (#149090)
Adding a test where both `ninf` and `reassoc` flags are present on the
instruction. We don't know yet if it is legal to interchange. Prima
facie, it does not look like it should be legal but more analysis is
needed.
Commit: e8dc96d9de14c4b2317b11b8bc6e9310113697b3
https://github.com/llvm/llvm-project/commit/e8dc96d9de14c4b2317b11b8bc6e9310113697b3
Author: Jonas Devlieghere <jonas at devlieghere.com>
Date: 2025-07-16 (Wed, 16 Jul 2025)
Changed paths:
M lldb/docs/use/mcp.md
Log Message:
-----------
[lldb] Document MCP tools & resources (#148708)
Add documentation for the tools and resources exposed by LLDB's MCP
server.
Commit: b470ac419d7e8eec6c8a27539096e38a1751ee12
https://github.com/llvm/llvm-project/commit/b470ac419d7e8eec6c8a27539096e38a1751ee12
Author: Jeremy Morse <jeremy.morse at sony.com>
Date: 2025-07-16 (Wed, 16 Jul 2025)
Changed paths:
M llvm/lib/IR/Verifier.cpp
Log Message:
-----------
[DebugInfo] Delete debug-intrinsic verifier checks (#149066)
We no longer produce debug-intrinsics, and whenever they're spotted in
bitcode or textual IR they get autoupgraded. We could quite reasonably
reject them out of hand as a construct that shouldn't be present.
However, the DXIL folks are likely to be converting records back to
intrinsics for years to come, and there's no need to make that an error.
There's no value in verifying them IMO.
Commit: 6f660e269242d51a8d36a9a1f98a2244e8311a1a
https://github.com/llvm/llvm-project/commit/6f660e269242d51a8d36a9a1f98a2244e8311a1a
Author: Daniel Paoliello <danpao at microsoft.com>
Date: 2025-07-16 (Wed, 16 Jul 2025)
Changed paths:
M third-party/benchmark/src/sysinfo.cc
Log Message:
-----------
Fix MSVC warning in benchmark (#147357)
Building LLVM with MSVC is raising the following warning:
```
llvm\third-party\benchmark\src\sysinfo.cc(375): warning C4062: enumerator 'CacheUnknown' in switch of enum '_PROCESSOR_CACHE_TYPE' is not handled
```
This change resolves the warning by moving the `Unknown` type into a
case block for `CacheUnknown`.
Not sure how this code flows back into the original source.
Commit: 8519143a9fd368e7cfcf61582683c4e48e7d67d0
https://github.com/llvm/llvm-project/commit/8519143a9fd368e7cfcf61582683c4e48e7d67d0
Author: Sirui Mu <msrlancern at gmail.com>
Date: 2025-07-17 (Thu, 17 Jul 2025)
Changed paths:
M clang/include/clang/CIR/Dialect/IR/CIROps.td
M clang/include/clang/CIR/MissingFeatures.h
M clang/lib/CIR/CodeGen/CIRGenBuiltin.cpp
M clang/lib/CIR/CodeGen/CIRGenFunction.h
M clang/lib/CIR/Lowering/DirectToLLVM/LowerToLLVM.cpp
M clang/lib/CIR/Lowering/DirectToLLVM/LowerToLLVM.h
M clang/test/CIR/CodeGen/builtin_bit.cpp
Log Message:
-----------
[CIR] Add rotate operation (#148426)
This patch adds `cir.rotate` operation for the `__builtin_rotateleft`
and `__builtin_rotateright` families of builtin calls.
Commit: 97922a7d401a4bbbc74013d92f98119e5bdfaebd
https://github.com/llvm/llvm-project/commit/97922a7d401a4bbbc74013d92f98119e5bdfaebd
Author: David Spickett <david.spickett at linaro.org>
Date: 2025-07-16 (Wed, 16 Jul 2025)
Changed paths:
M lldb/docs/resources/build.rst
Log Message:
-----------
[lldb][docs] Add CAMKE_BUILD_TYPE to standlone build instructions
The first stage requires it, the second appears to default to
debug mode, which works but it's better we advise release mode
to match.
Commit: 9f364fe9c446d498f46efff327871dc62db8212f
https://github.com/llvm/llvm-project/commit/9f364fe9c446d498f46efff327871dc62db8212f
Author: David Spickett <david.spickett at linaro.org>
Date: 2025-07-16 (Wed, 16 Jul 2025)
Changed paths:
M lldb/docs/resources/qemu-testing.rst
Log Message:
-----------
[lldb][docs] Add section on testing with QEMU user (#149057)
This is not recommended to basically anyone but on occasion it's useful
and could be used for testing with other simulator programs for example
bare metal simulators.
It is not something we do officially support or make any quality
guarantees for.
Adding this is also an excuse to document the limitations and make the
time spent setting up system mode look more worthwhile and might be good
to cite in future discussions about testing in simulation.
Commit: bd6c16c6cfe28105d992fa997dce6e18ea86a5a4
https://github.com/llvm/llvm-project/commit/bd6c16c6cfe28105d992fa997dce6e18ea86a5a4
Author: Ellis Hoag <ellis.sparky.hoag at gmail.com>
Date: 2025-07-16 (Wed, 16 Jul 2025)
Changed paths:
M llvm/lib/Target/AArch64/AArch64InstrInfo.cpp
M llvm/test/CodeGen/AArch64/machine-outliner-safe-range-in-middle.mir
Log Message:
-----------
[MachineOutliner] Avoid ranges that cross bundle boundary (#148977)
We found some code that was hitting this assert because
`getOutlinableRanges()` was trying to create a range that crossed a
bundle boundary.
https://github.com/llvm/llvm-project/blob/ae3bba4d15a10646ea91c6c0795633b82939857b/llvm/include/llvm/CodeGen/MachineInstrBundleIterator.h#L133-L135
Avoid creating those ranges and add a test that hit the assert.
Commit: 8349bbd0b98c84836d55593c7eb035c2b0f4e87a
https://github.com/llvm/llvm-project/commit/8349bbd0b98c84836d55593c7eb035c2b0f4e87a
Author: Valentin Clement (バレンタイン クレメン) <clementval at gmail.com>
Date: 2025-07-16 (Wed, 16 Jul 2025)
Changed paths:
M flang/lib/Lower/ConvertVariable.cpp
Log Message:
-----------
[flang][cuda] Exit early when there is no device components (#149005)
- Exit early when there is no device components
- Make the retrieval of the record type more robust
Commit: 0f0305021c6e880f8787b9be6606c27e1a0641ed
https://github.com/llvm/llvm-project/commit/0f0305021c6e880f8787b9be6606c27e1a0641ed
Author: Udit Kumar Agarwal <udit.agarwal at intel.com>
Date: 2025-07-16 (Wed, 16 Jul 2025)
Changed paths:
M .github/workflows/email-check.yaml
Log Message:
-----------
[CI] Make email check workflow fail when author's email is private in Github UI (#148694)
**Problem**
Currently, the email check workflow uses `git` to see email used for the
last commit but the email address used when merging is actually governed
by GitHub settings not what's stored in `git`. Due to this, the email
check workflow passes even when the author's email is private in Github.
We saw several such cases in our fork of llvm. See
https://github.com/intel/llvm/issues/17675
**Solution**
Try to find user's email using GH's GraphQL APIs. User's email will be
null if it's hidden in the profile.
---------
Signed-off-by: Agarwal, Udit <udit.agarwal at intel.com>
Commit: 8d21025c3aeb1c98caef08f8446ec138c62288d1
https://github.com/llvm/llvm-project/commit/8d21025c3aeb1c98caef08f8446ec138c62288d1
Author: Brad Richardson <everythingfunctional at protonmail.com>
Date: 2025-07-16 (Wed, 16 Jul 2025)
Changed paths:
A flang/docs/ParallelMultiImageFortranRuntime.md
M flang/docs/index.md
Log Message:
-----------
[flang] Parallel runtime library design doc (PRIF) (#76088)
The Parallel Runtime Interface for Fortran (PRIF) specifies the interface design for
supporting Fortran's multi-image parallel features in flang.
---------
Co-authored-by: Katherine Rasmussen <krasmussen at lbl.gov>
Co-authored-by: Damian Rouson <rouson at lbl.gov>
Co-authored-by: Dan Bonachea <dobonachea at lbl.gov>
Commit: fdec9fd4f81fd336d6d5d50bbd48cd0e095f46b9
https://github.com/llvm/llvm-project/commit/fdec9fd4f81fd336d6d5d50bbd48cd0e095f46b9
Author: duhbbx <duhbbx at gmail.com>
Date: 2025-07-16 (Wed, 16 Jul 2025)
Changed paths:
M clang/include/clang/Basic/DiagnosticSemaKinds.td
M clang/test/CXX/drs/cwg8xx.cpp
M clang/test/CXX/module/dcl.dcl/dcl.module/dcl.module.interface/p1.cppm
M clang/test/CXX/module/module.interface/p1.cpp
M clang/test/Modules/cxx20-10-2-ex1.cpp
M clang/test/Modules/cxx20-export-import.cpp
M clang/test/Modules/cxx20-import-diagnostics-a.cpp
M clang/test/Modules/export-in-non-modules.cpp
Log Message:
-----------
[Clang] Fix export declaration diagnostic message (#149059)
Change the error message from "export declaration can only be used
within a module purview" to "export declaration can only be used within
a module interface" to be technically accurate.
The previous message was misleading because export declarations are
actually within a module purview when used in module implementation
units, but they are only allowed in module interface units.
This addresses the issue pointed out in GitHub issue #149008 where
Bigcheese noted that the diagnostic wording was incorrect.
Fixes #149008
Commit: bd0f9dd86b16660debca39ce76abdd9da1c157a3
https://github.com/llvm/llvm-project/commit/bd0f9dd86b16660debca39ce76abdd9da1c157a3
Author: Amr Hesham <amr96 at programmer.net>
Date: 2025-07-16 (Wed, 16 Jul 2025)
Changed paths:
M clang/include/clang/CIR/Dialect/Builder/CIRBaseBuilder.h
M clang/lib/CIR/CodeGen/CIRGenBuilder.h
M clang/lib/CIR/CodeGen/CIRGenExprComplex.cpp
M clang/lib/CIR/Dialect/Transforms/LoweringPrepare.cpp
A clang/test/CIR/CodeGen/complex-unary.cpp
Log Message:
-----------
[CIR] Upstream unary not for ComplexType (#148857)
Upstream unary not for ComplexType
https://github.com/llvm/llvm-project/issues/141365
Commit: 55b417a75fb4cbd13066510cba13d1c214095eab
https://github.com/llvm/llvm-project/commit/55b417a75fb4cbd13066510cba13d1c214095eab
Author: Ross Brunton <ross at codeplay.com>
Date: 2025-07-16 (Wed, 16 Jul 2025)
Changed paths:
M offload/liboffload/src/OffloadImpl.cpp
M offload/unittests/OffloadAPI/symbol/olGetSymbol.cpp
Log Message:
-----------
[Offload] Cache symbols in program (#148209)
When creating a new symbol, check that it already exists. If it does,
return that pointer rather than building a new symbol structure.
Commit: 037d34815efc6b2c0b3f9f4d19945e49aac831d1
https://github.com/llvm/llvm-project/commit/037d34815efc6b2c0b3f9f4d19945e49aac831d1
Author: sribee8 <sriya.pratipati at gmail.com>
Date: 2025-07-16 (Wed, 16 Jul 2025)
Changed paths:
M libc/fuzzing/math/acos_fuzz.cpp
M libc/fuzzing/math/asin_fuzz.cpp
M libc/fuzzing/math/cos_fuzz.cpp
M libc/fuzzing/math/log10_fuzz.cpp
M libc/fuzzing/math/log1p_fuzz.cpp
M libc/fuzzing/math/log2_fuzz.cpp
M libc/fuzzing/math/log_fuzz.cpp
M libc/fuzzing/math/sin_fuzz.cpp
M libc/fuzzing/math/sincos_fuzz.cpp
M libc/fuzzing/math/sqrt_fuzz.cpp
M libc/fuzzing/math/tan_fuzz.cpp
Log Message:
-----------
[libc] Updated fuzz tests for trig functions (#148891)
Fuzz tests were set up incorrectly so updated trig functions to match
the correct format.
---------
Co-authored-by: Sriya Pratipati <sriyap at google.com>
Commit: ba271cc07334c74df55741701e5b22032c0cddbb
https://github.com/llvm/llvm-project/commit/ba271cc07334c74df55741701e5b22032c0cddbb
Author: Jun Wang <jwang86 at yahoo.com>
Date: 2025-07-16 (Wed, 16 Jul 2025)
Changed paths:
M llvm/lib/Target/AMDGPU/SIInstructions.td
M llvm/lib/Target/AMDGPU/VOP3Instructions.td
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-bswap.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fshr.mir
M llvm/test/CodeGen/AMDGPU/branch-folding-implicit-def-subreg.ll
M llvm/test/MC/AMDGPU/gfx10_asm_vop3.s
M llvm/test/MC/AMDGPU/gfx7_err_pos.s
M llvm/test/MC/AMDGPU/gfx8_err_pos.s
M llvm/test/MC/AMDGPU/gfx9_asm_vop3_e64.s
M llvm/test/MC/Disassembler/AMDGPU/gfx10_vop3.txt
M llvm/test/MC/Disassembler/AMDGPU/gfx9_vop3.txt
Log Message:
-----------
Revert "[AMDGPU][MC] Allow op_sel in v_alignbit_b32 etc in GFX9 and GFX10 (#142188) (#149138)
This reverts commit ce7851f6b7d59e50f92cb4e8dbfd801576c8b641.
The intrinsic llvm.amdgcn.alignbyte was not properly handled for gfx10.
Commit: 560e7df6893495fabe91bc921f9cc0e28a25eb73
https://github.com/llvm/llvm-project/commit/560e7df6893495fabe91bc921f9cc0e28a25eb73
Author: Changpeng Fang <changpeng.fang at amd.com>
Date: 2025-07-16 (Wed, 16 Jul 2025)
Changed paths:
M llvm/lib/Target/AMDGPU/GCNHazardRecognizer.cpp
M llvm/lib/Target/AMDGPU/GCNHazardRecognizer.h
M llvm/test/CodeGen/AMDGPU/llvm.sqrt.bf16.ll
A llvm/test/CodeGen/AMDGPU/trans-coexecution-hazard.mir
Log Message:
-----------
AMDGPU: Handle the co-execution hazards for TRANS for gfx1250 (#149024)
For the co-execution of the TRANS ops, the requirement is: 1 independent
op or V_NOP (since TRANS takes 2 cycles) after the trans op before its
sources can be overwritten or the output of the trans op can be used.
Commit: 22994edb5fd71198c48670255c979fcc962930a1
https://github.com/llvm/llvm-project/commit/22994edb5fd71198c48670255c979fcc962930a1
Author: Erich Keane <ekeane at nvidia.com>
Date: 2025-07-16 (Wed, 16 Jul 2025)
Changed paths:
M clang/include/clang/Basic/DiagnosticSemaKinds.td
M clang/lib/Sema/SemaOpenACC.cpp
A clang/test/SemaOpenACC/private_firstprivate_reduction_required_ops.cpp
Log Message:
-----------
[OpenACC][Sema] Implement warning for non-effective 'private' (#149004)
A 'private' variable reference needs to have a default constructor and a
destructor, else we cannot properly emit them in codegen. This patch
adds a warning-as-default-error to diagnose this.
We'll have to do something similar for firstprivate/reduction, however
it isn't clear whether we could skip the check for default-constructor
for those two (they still need a destructor!). Depending on how we
intend to create them (and we probably have to figure this out?), we
could either require JUST a copy-constructor (then make the init section
just the alloca, and the copy-ctor be the 'copy' section), OR they
require a default-constructor + copy-assignment.
Commit: 056f0a10b320fc2fd75f46aa67d68708303d89ad
https://github.com/llvm/llvm-project/commit/056f0a10b320fc2fd75f46aa67d68708303d89ad
Author: raoanag <127366241+raoanag at users.noreply.github.com>
Date: 2025-07-16 (Wed, 16 Jul 2025)
Changed paths:
M clang/include/clang/Basic/BuiltinsSPIRVVK.td
M clang/lib/CodeGen/TargetBuiltins/SPIR.cpp
M clang/lib/Headers/hlsl/hlsl_intrinsic_helpers.h
M clang/lib/Headers/hlsl/hlsl_intrinsics.h
M clang/lib/Sema/SemaSPIRV.cpp
A clang/test/CodeGenHLSL/builtins/refract.hlsl
A clang/test/CodeGenSPIRV/Builtins/refract.c
A clang/test/SemaHLSL/BuiltIns/refract-errors.hlsl
A clang/test/SemaSPIRV/BuiltIns/refract-errors.c
M llvm/include/llvm/IR/IntrinsicsSPIRV.td
M llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp
A llvm/test/CodeGen/SPIRV/hlsl-intrinsics/refract.ll
A llvm/test/CodeGen/SPIRV/opencl/refract-error.ll
Log Message:
-----------
[HLSL][DXIL] Implement `refract` intrinsic (#147342)
- [x] Implement refract using HLSL source in hlsl_intrinsics.h
- [x] Implement the refract SPIR-V target built-in in
clang/include/clang/Basic/BuiltinsSPIRV.td
- [x] Add sema checks for refract to CheckSPIRVBuiltinFunctionCall in
clang/lib/Sema/SemaSPIRV.cpp
- [x] Add codegen for spv refract to EmitSPIRVBuiltinExpr in
CGBuiltin.cpp
- [x] Add codegen tests to clang/test/CodeGenHLSL/builtins/refract.hlsl
- [x] Add spv codegen test to clang/test/CodeGenSPIRV/Builtins/refract.c
- [x] Add sema tests to clang/test/SemaHLSL/BuiltIns/refract-errors.hlsl
- [x] Add spv sema tests to
clang/test/SemaSPIRV/BuiltIns/refract-errors.c
- [x] Create the int_spv_refract intrinsic in IntrinsicsSPIRV.td
- [x] In SPIRVInstructionSelector.cpp create the refract lowering and
map it to int_spv_refract in SPIRVInstructionSelector::selectIntrinsic.
- [x] Create SPIR-V backend test case in
llvm/test/CodeGen/SPIRV/hlsl-intrinsics/refract.ll
- [x] Check for what OpenCL support is needed.
Resolves https://github.com/llvm/llvm-project/issues/99153
Commit: 82451d0b1341a9b6c01eaa5d27088ff9f3287853
https://github.com/llvm/llvm-project/commit/82451d0b1341a9b6c01eaa5d27088ff9f3287853
Author: sribee8 <sriya.pratipati at gmail.com>
Date: 2025-07-16 (Wed, 16 Jul 2025)
Changed paths:
M libc/fuzzing/math/exp10_fuzz.cpp
M libc/fuzzing/math/exp2_fuzz.cpp
M libc/fuzzing/math/exp_fuzz.cpp
M libc/fuzzing/math/expm1_fuzz.cpp
Log Message:
-----------
[libc] Updated exp fuzz tests (#148912)
Fuzz tests were previously in the wrong format, updated them to correct
format.
---------
Co-authored-by: Sriya Pratipati <sriyap at google.com>
Commit: c4d4e761ef27d6dd27323cf3efa506db5e9e3457
https://github.com/llvm/llvm-project/commit/c4d4e761ef27d6dd27323cf3efa506db5e9e3457
Author: Mikhail R. Gadelha <mikhail at igalia.com>
Date: 2025-07-16 (Wed, 16 Jul 2025)
Changed paths:
M llvm/lib/Target/RISCV/RISCVSchedSpacemitX60.td
M llvm/test/CodeGen/RISCV/rvv/vxrm-insert-out-of-loop.ll
M llvm/test/tools/llvm-mca/RISCV/SpacemitX60/atomic.s
M llvm/test/tools/llvm-mca/RISCV/SpacemitX60/floating-point.s
M llvm/test/tools/llvm-mca/RISCV/SpacemitX60/integer.s
A llvm/test/tools/llvm-mca/RISCV/SpacemitX60/rvv-arithmetic.s
A llvm/test/tools/llvm-mca/RISCV/SpacemitX60/rvv-bitwise.s
A llvm/test/tools/llvm-mca/RISCV/SpacemitX60/rvv-comparison.s
A llvm/test/tools/llvm-mca/RISCV/SpacemitX60/rvv-conversion.s
A llvm/test/tools/llvm-mca/RISCV/SpacemitX60/rvv-fma.s
A llvm/test/tools/llvm-mca/RISCV/SpacemitX60/rvv-fp.s
A llvm/test/tools/llvm-mca/RISCV/SpacemitX60/rvv-mask.s
A llvm/test/tools/llvm-mca/RISCV/SpacemitX60/rvv-minmax.s
A llvm/test/tools/llvm-mca/RISCV/SpacemitX60/rvv-mul-div.s
A llvm/test/tools/llvm-mca/RISCV/SpacemitX60/rvv-permutation.s
A llvm/test/tools/llvm-mca/RISCV/SpacemitX60/rvv-reduction.s
Log Message:
-----------
[RISCV] Pre-commit RVV instructions to the x60 scheduling model and tests
Commit: bcee18a2e268dd106e4b3c2a1d083a4da21f4f23
https://github.com/llvm/llvm-project/commit/bcee18a2e268dd106e4b3c2a1d083a4da21f4f23
Author: Slava Zakharin <szakharin at nvidia.com>
Date: 2025-07-16 (Wed, 16 Jul 2025)
Changed paths:
M flang/lib/Optimizer/CodeGen/LowerRepackArrays.cpp
M flang/test/Transforms/lower-repack-arrays.fir
Log Message:
-----------
[flang] Handle SEQUENCE derived types for array repacking. (#148777)
It is possible that a non-polymorphic dummy argument
has a dynamic type that does not match its static type
in a valid Fortran program, e.g. when the actual and
the dummy arguments have different compatible derived
SEQUENCE types:
module mod
type t
sequence
integer x
end type
contains
subroutine test(x)
type t
sequence
integer x
end type
type(t) :: x(:)
end subroutine
end module
'test' may be called with an actual argument of type 'mod::t',
which is the dynamic type of 'x' on entry to 'test'.
If we create the repacking temporary based on the static type of 'x'
('test::t'), then the runtime will report the types mismatch
as an error. Thus, we have to create the temporary using
the dynamic type of 'x'. The fact that the dummy's type
has SEQUENCE or BIND attribute is not easily computable
at this stage, so we use the dynamic type for all derived
type cases. As long as this is done only when the repacking
actually happens, the overhead should not be noticeable.
Commit: fb3972dd06cbc1b0a5305f81b0c2d74e44dbea41
https://github.com/llvm/llvm-project/commit/fb3972dd06cbc1b0a5305f81b0c2d74e44dbea41
Author: Daniel Bertalan <dani at danielbertalan.dev>
Date: 2025-07-16 (Wed, 16 Jul 2025)
Changed paths:
M lld/MachO/Arch/ARM64.cpp
M lld/MachO/CMakeLists.txt
A lld/MachO/LinkerOptimizationHints.cpp
A lld/MachO/LinkerOptimizationHints.h
M lld/MachO/Target.h
M lld/MachO/Writer.cpp
M llvm/utils/gn/secondary/lld/MachO/BUILD.gn
Log Message:
-----------
[lld-macho] Move Linker Optimization Hints pass to a separate file
Moving it away from the arm64 `TargetInfo` class will let us enable it
more easily for arm64_32 and the soon-to-be-added arm64e target as well.
This is the NFC part of #148964
Commit: c372a2cd0a1e4502f35bf8ebfc0a5d682223249e
https://github.com/llvm/llvm-project/commit/c372a2cd0a1e4502f35bf8ebfc0a5d682223249e
Author: Daniel Paoliello <danpao at microsoft.com>
Date: 2025-07-16 (Wed, 16 Jul 2025)
Changed paths:
M third-party/benchmark/src/sysinfo.cc
Log Message:
-----------
Use default instead of a specific case to fix the MSVC warning in sysinfo.cc (#149159)
#147357 attempted to fix an MSVC in sysinfo.cc by adding a `case` block
for a missing enum value.
However, this resulted in [CI
failures](https://github.com/llvm/llvm-project/pull/147357#issuecomment-3079709852):
```
4.170 [148/4/9] Building CXX object third-party/benchmark/src/CMakeFiles/benchmark.dir/sysinfo.cc.obj
FAILED: third-party/benchmark/src/CMakeFiles/benchmark.dir/sysinfo.cc.obj
C:\Users\tcwg\scoop\shims\ccache.exe C:\Users\tcwg\scoop\apps\llvm-arm64\current\bin\clang-cl.exe /nologo -TP -DBENCHMARK_STATIC_DEFINE -DEXPERIMENTAL_KEY_INSTRUCTIONS -DHAVE_STD_REGEX -DHAVE_STEADY_CLOCK -DUNICODE -D_CRT_NONSTDC_NO_DEPRECATE -D_CRT_NONSTDC_NO_WARNINGS -D_CRT_SECURE_NO_DEPRECATE -D_CRT_SECURE_NO_WARNINGS -D_GLIBCXX_ASSERTIONS -D_HAS_EXCEPTIONS=0 -D_SCL_SECURE_NO_DEPRECATE -D_SCL_SECURE_NO_WARNINGS -D_UNICODE -D__STDC_CONSTANT_MACROS -D__STDC_FORMAT_MACROS -D__STDC_LIMIT_MACROS -IC:/Users/tcwg/llvm-worker/flang-arm64-windows-msvc/build/third-party/benchmark/src -IC:/Users/tcwg/llvm-worker/flang-arm64-windows-msvc/llvm-project/third-party/benchmark/src -IC:/Users/tcwg/llvm-worker/flang-arm64-windows-msvc/build/include -IC:/Users/tcwg/llvm-worker/flang-arm64-windows-msvc/llvm-project/llvm/include -IC:/Users/tcwg/llvm-worker/flang-arm64-windows-msvc/llvm-project/third-party/benchmark/include /DWIN32 /D_WINDOWS /Zc:inline /Zc:__cplusplus /Oi /Brepro /bigobj /permissive- -Werror=unguarded-availability-new -Wextra -Wno-unused-parameter -Wwrite-strings -Wcast-qual -Wmissing-field-initializers -Wimplicit-fallthrough -Wcovered-switch-default -Wno-noexcept-type -Wnon-virtual-dtor -Wdelete-non-virtual-dtor -Wsuggest-override -Wstring-conversion -Wmisleading-indentation -Wctad-maybe-unsupported /Gw /W4 -EHs- -EHa- /O2 /Ob2 -std:c++14 -MD -UNDEBUG /showIncludes /Fothird-party/benchmark/src/CMakeFiles/benchmark.dir/sysinfo.cc.obj /Fdthird-party\benchmark\src\CMakeFiles\benchmark.dir\benchmark.pdb -c -- C:/Users/tcwg/llvm-worker/flang-arm64-windows-msvc/llvm-project/third-party/benchmark/src/sysinfo.cc
C:/Users/tcwg/llvm-worker/flang-arm64-windows-msvc/llvm-project/third-party/benchmark/src/sysinfo.cc(374,12): error: use of undeclared identifier 'CacheUnknown'
374 | case CacheUnknown:
| ^
1 error generated.
```
The root cause is that the enum being switched on is defined in the
Windows SDK, so depending on which version of the SDK you are using
`CacheUnknown` may or may not be defined.
The correct fix here is to use a `default` block in the switch statement
instead.
Commit: b3c72a97c5ac352b89c12f3cf7c3f223219f91ed
https://github.com/llvm/llvm-project/commit/b3c72a97c5ac352b89c12f3cf7c3f223219f91ed
Author: Andre Kuhlenschmidt <andre.kuhlenschmidt at gmail.com>
Date: 2025-07-16 (Wed, 16 Jul 2025)
Changed paths:
M flang/include/flang/Parser/message.h
M flang/lib/Frontend/FrontendAction.cpp
M flang/lib/Parser/message.cpp
M flang/lib/Semantics/semantics.cpp
A flang/test/Driver/fatal-errors-warnings.f90
Log Message:
-----------
[flang][driver] -Werror promotes warnings to error and interopts with -Wfatal-errors (#148748)
This PR changes how `-Werror` promotes warnings to errors so that it
interoperates with `-Wfatal-error`. It maintains the property that
warnings and other messages promoted to errors are displayed as there
original message.
Commit: 362594a10fa5fd8e5f8d31eb5391370c928b639e
https://github.com/llvm/llvm-project/commit/362594a10fa5fd8e5f8d31eb5391370c928b639e
Author: Jay Foad <jay.foad at amd.com>
Date: 2025-07-16 (Wed, 16 Jul 2025)
Changed paths:
M llvm/utils/TableGen/Common/CodeGenRegisters.cpp
Log Message:
-----------
[TableGen] Remove unnecessary sortAndUniqueRegisters (#149125)
Each of the SRSets is already sorted and unique because it is a filtered
version of RC->getMembers() which is already sorted and unique.
Commit: 43f10639a18b2b8fb0976f3bde84a9d240647915
https://github.com/llvm/llvm-project/commit/43f10639a18b2b8fb0976f3bde84a9d240647915
Author: Daniel Bertalan <dani at danielbertalan.dev>
Date: 2025-07-16 (Wed, 16 Jul 2025)
Changed paths:
M lld/MachO/LinkerOptimizationHints.cpp
M lld/MachO/Writer.cpp
A lld/test/MachO/loh-arm64-32.s
Log Message:
-----------
[lld-macho] Enable Linker Optimization Hints pass for arm64_32 (#148964)
The backend emits `.loh` directives for arm64_32 as well. Our pass
already handles 32-bit pointer loads correctly (there was an extraneous
sanity check for 8-byte pointer sizes, I removed that here), so we can
enable them for all arm64 subtargets, including our upcoming arm64e
support.
Commit: 4355356d96de1e171f7511a6c41d056871dacc68
https://github.com/llvm/llvm-project/commit/4355356d96de1e171f7511a6c41d056871dacc68
Author: Jay Foad <jay.foad at amd.com>
Date: 2025-07-16 (Wed, 16 Jul 2025)
Changed paths:
M llvm/utils/TableGen/Common/CodeGenRegisters.cpp
M llvm/utils/TableGen/Common/CodeGenRegisters.h
M llvm/utils/TableGen/RegisterInfoEmitter.cpp
Log Message:
-----------
[TableGen] Add a bitvector of members of CodeGenRegisterClass (#149122)
This makes CodeGenRegisterClass::contains fast. Use this to simplify
inferMatchingSuperRegClass.
Commit: 3a6ef8b359fc3f2459ef60013b8938ebe847831b
https://github.com/llvm/llvm-project/commit/3a6ef8b359fc3f2459ef60013b8938ebe847831b
Author: Muhammad Bassiouni <60100307+bassiounix at users.noreply.github.com>
Date: 2025-07-16 (Wed, 16 Jul 2025)
Changed paths:
M libc/shared/math.h
A libc/shared/math/exp10.h
M libc/src/__support/FPUtil/PolyEval.h
M libc/src/__support/FPUtil/double_double.h
M libc/src/__support/math/CMakeLists.txt
A libc/src/__support/math/exp10.h
M libc/src/math/generic/CMakeLists.txt
M libc/src/math/generic/exp10.cpp
M utils/bazel/llvm-project-overlay/libc/BUILD.bazel
Log Message:
-----------
[libc][math] Refactor exp10 implementation to header-only in src/__support/math folder. (#148400)
Part of #147386
in preparation for:
https://discourse.llvm.org/t/rfc-make-clang-builtin-math-functions-constexpr-with-llvm-libc-to-support-c-23-constexpr-math-functions/86450
Commit: 94382c8e56e878d1b6a8cf317e3632df5352e23e
https://github.com/llvm/llvm-project/commit/94382c8e56e878d1b6a8cf317e3632df5352e23e
Author: Leonard Chan <leonardchan at google.com>
Date: 2025-07-16 (Wed, 16 Jul 2025)
Changed paths:
M llvm/lib/CodeGen/StackProtector.cpp
A llvm/test/Transforms/StackProtector/cross-dso-cfi-stack-chk-fail.ll
A llvm/test/Transforms/StackProtector/stack-chk-fail-alias.ll
Log Message:
-----------
[llvm][StackProtector] Add noreturn to __stack_chk_fail call (#143976)
This is a reland for 99e53cb4139eda491f97cb33ee42ea424d352200 with the
appropriate test fixes.
It's possible for __stack_chk_fail to be an alias when using CrossDSOCFI
since it will make a jump table entry for this function and replace it
with an alias. StackProtector can crash since it always expects this to
be a regular function. Instead add the noreturn attribute to the call.
Commit: ececa877083fcbe19aa0394b280630b9d807cd6d
https://github.com/llvm/llvm-project/commit/ececa877083fcbe19aa0394b280630b9d807cd6d
Author: Mikhail R. Gadelha <mikhail at igalia.com>
Date: 2025-07-16 (Wed, 16 Jul 2025)
Changed paths:
M llvm/lib/Target/RISCV/RISCVVLOptimizer.cpp
M llvm/test/CodeGen/RISCV/rvv/vl-opt-instrs.ll
M llvm/test/CodeGen/RISCV/rvv/vl-opt-op-info.mir
Log Message:
-----------
[RISCV][VLOPT] Add support for vrgather (#148249)
This PR adds support for the vrgather.vi, vrgather.vx, vrgather.vv,
vrgatherei16.vv instructions in the RISC-V VLOptimizer.
To support vrgatherei16.vv I also needed to add support for it in
getOperandLog2EEW.
Commit: 6824bcfdb4c8315a990f4b5ce2cb9f528281a823
https://github.com/llvm/llvm-project/commit/6824bcfdb4c8315a990f4b5ce2cb9f528281a823
Author: Min-Yih Hsu <min.hsu at sifive.com>
Date: 2025-07-16 (Wed, 16 Jul 2025)
Changed paths:
M llvm/include/llvm/Analysis/VectorUtils.h
M llvm/include/llvm/CodeGen/TargetLowering.h
M llvm/lib/Analysis/VectorUtils.cpp
M llvm/lib/CodeGen/InterleavedAccessPass.cpp
M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
M llvm/lib/Target/AArch64/AArch64ISelLowering.h
M llvm/lib/Target/RISCV/RISCVISelLowering.h
M llvm/lib/Target/RISCV/RISCVInterleavedAccess.cpp
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-deinterleave-load.ll
M llvm/test/CodeGen/RISCV/rvv/vp-vector-interleaved-access.ll
M llvm/test/Transforms/InterleavedAccess/AArch64/fixed-deinterleave-intrinsics.ll
M llvm/test/Transforms/InterleavedAccess/AArch64/scalable-deinterleave-intrinsics.ll
M llvm/test/Transforms/InterleavedAccess/AArch64/sve-deinterleave4.ll
M llvm/test/Transforms/InterleavedAccess/AArch64/sve-interleaved-accesses.ll
Log Message:
-----------
[IA] Relax the requirement of having ExtractValue users on deinterleave intrinsic (#148716)
There are cases where InstCombine / InstSimplify might sink extractvalue
instructions that use a deinterleave intrinsic into successor blocks,
which prevents InterleavedAccess from kicking in because the current
pattern requires deinterleave intrinsic to be used by extractvalue.
However, this requirement is bit too strict while we could have just
replaced the users of deinterleave intrinsic with whatever generated by
the target TLI hooks.
Commit: 8c28f4920dfda2e3d91c58e8eb5b568dd396fa2d
https://github.com/llvm/llvm-project/commit/8c28f4920dfda2e3d91c58e8eb5b568dd396fa2d
Author: Michael Buch <michaelbuch12 at gmail.com>
Date: 2025-07-16 (Wed, 16 Jul 2025)
Changed paths:
M lldb/source/Commands/CommandObjectDWIMPrint.cpp
M lldb/source/Commands/CommandObjectExpression.cpp
A lldb/test/Shell/Settings/TestChildCountTruncation.test
Log Message:
-----------
[lldb] Print children-count warning for dwim-print and expr (#149088)
When dumping variables, LLDB will print a one-time warning about
truncating children (when the children count exceeds the default
`target.max-children-count`). But we only do this for `frame variable`.
So if we use `dwim-print` or `expression`, the output gets truncated but
we don't print a warning. But because we store the fact that we
truncated some output on the `CommandInterpreter`, we fire the warning
next time we use `frame variable`. E.g.,:
```
(lldb) p arr
(int[1000]) {
[0] = -5
[1] = 0
[2] = 0
<-- snipped -->
[253] = 0
[254] = 0
[255] = 0
...
}
(lldb) v someLocal
(int) someLocal = 10
*** Some of the displayed variables have more members than the debugger
will show by default. To show all of them, you can either use the
--show-all-children option to frame variable or raise the limit by
changing the target.max-children-count setting.
```
This patch prints the warning for `dwim-print` and `expression`.
I only added a test for the `target.max-children-count` for now because
it seems the `target.max-children-depth` warning is broken (I can't get
it to fire).
Commit: b9f5b39e04d22e9a6ad451bdc0779bed31015372
https://github.com/llvm/llvm-project/commit/b9f5b39e04d22e9a6ad451bdc0779bed31015372
Author: Jay Foad <jay.foad at amd.com>
Date: 2025-07-16 (Wed, 16 Jul 2025)
Changed paths:
M llvm/lib/TableGen/TGLexer.cpp
Log Message:
-----------
[TableGen] Remove explicit recursion in LexToken (#143697)
When profiling a Release+Asserts build of llvm-tblgen I noticed that it
was recursing hundreds of times to lex a sequence of hundreds of space
characters.
Commit: 7caa0c9a55b33d8d627975e94c3367aa68dc37c7
https://github.com/llvm/llvm-project/commit/7caa0c9a55b33d8d627975e94c3367aa68dc37c7
Author: Udit Kumar Agarwal <udit.agarwal at intel.com>
Date: 2025-07-16 (Wed, 16 Jul 2025)
Changed paths:
M .github/workflows/email-check.yaml
Log Message:
-----------
Revert "[CI] Make email check workflow fail when author's email is private in Github UI" (#149186)
Reverts llvm/llvm-project#148694
The workflow is failing if user's email is not listed publicly on your
GH profile. This is different from not having your email public on
Github (in Github email settings page vs. email field in Github
profile/email settings).
Commit: 1e4e2b332dc08e01498c677a6a375fcbc9d5e9f0
https://github.com/llvm/llvm-project/commit/1e4e2b332dc08e01498c677a6a375fcbc9d5e9f0
Author: Valentin Clement (バレンタイン クレメン) <clementval at gmail.com>
Date: 2025-07-16 (Wed, 16 Jul 2025)
Changed paths:
M flang/lib/Optimizer/Transforms/CUFDeviceGlobal.cpp
M flang/test/Fir/CUDA/cuda-device-global.f90
Log Message:
-----------
[flang][cuda] Import type descriptor in the gpu module when needed (#149157)
Commit: b7f6abdd052412bebfedc9cac26fc58b9edb618d
https://github.com/llvm/llvm-project/commit/b7f6abdd052412bebfedc9cac26fc58b9edb618d
Author: Daniil Fukalov <dfukalov at gmail.com>
Date: 2025-07-16 (Wed, 16 Jul 2025)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp
A llvm/test/CodeGen/AMDGPU/select-cmp-shared-constant-fp.ll
A llvm/test/CodeGen/AMDGPU/select-cmp-shared-constant-int.ll
Log Message:
-----------
[AMDGPU] Try to reuse register with the constant from compare in v_cndmask (#148740)
For some targets, the optimization X == Const ? X : Y -> X == Const ?
Const : Y can cause extra register usage or redundant immediate encoding
for the constant in cndmask generated from the ternary operation.
This patch detects such cases and reuses the register from the compare
instruction that already holds the constant, instead of materializing it
again for cndmask.
The optimization avoids immediates that can be encoded into cndmask
instruction (including +-0.0), as well as !isNormal() constants.
The change is reworked on the base of #131146
---------
Co-authored-by: Copilot <175728472+Copilot at users.noreply.github.com>
Commit: cb6d1bbfcd01866ef7a3027968e6480ef1c2c992
https://github.com/llvm/llvm-project/commit/cb6d1bbfcd01866ef7a3027968e6480ef1c2c992
Author: Guy David <49722543+guy-david at users.noreply.github.com>
Date: 2025-07-17 (Thu, 17 Jul 2025)
Changed paths:
M clang/test/CodeGen/PowerPC/builtins-ppc-fpconstrained.c
A llvm/test/CodeGen/PowerPC/spe-vsx-incompatibility.ll
Log Message:
-----------
[PowerPC] Test SPE incompatibility with VSX (#147184)
PPCSubtarget is not always initialized, depending on which passes are
running, and in our downstream fork, -enable-matrix is the default
configuration (regardless of whether matrix intrinsics are present in
the IR), which triggers a fatal error in builtins-ppc-fpconstrained.c.
Commit: 9912ccb0b4d17a4dd4ef8df718b63e3a907ad7c5
https://github.com/llvm/llvm-project/commit/9912ccb0b4d17a4dd4ef8df718b63e3a907ad7c5
Author: Stanislav Mekhanoshin <Stanislav.Mekhanoshin at amd.com>
Date: 2025-07-16 (Wed, 16 Jul 2025)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPU.td
M llvm/lib/Target/AMDGPU/FLATInstructions.td
M llvm/lib/Target/AMDGPU/GCNSubtarget.h
M llvm/test/MC/AMDGPU/gfx1250_asm_vflat.s
M llvm/test/MC/Disassembler/AMDGPU/gfx1250_dasm_vflat.txt
Log Message:
-----------
[AMDGPU] gfx1250 MC support for FLAT GVS addressing (#149173)
Commit: 703501e66198c6d4be48773b617c784370e23d4a
https://github.com/llvm/llvm-project/commit/703501e66198c6d4be48773b617c784370e23d4a
Author: Stanislav Mekhanoshin <Stanislav.Mekhanoshin at amd.com>
Date: 2025-07-16 (Wed, 16 Jul 2025)
Changed paths:
M llvm/lib/Target/AMDGPU/FLATInstructions.td
M llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
A llvm/test/CodeGen/AMDGPU/flat-saddr-load.ll
Log Message:
-----------
[AMDGPU] Select flat GVS loads on gfx1250 (#149183)
Commit: 038e80cfd37e948d78c70d5a258ffe424a438d51
https://github.com/llvm/llvm-project/commit/038e80cfd37e948d78c70d5a258ffe424a438d51
Author: Ryan Prichard <rprichard at google.com>
Date: 2025-07-16 (Wed, 16 Jul 2025)
Changed paths:
M libcxx/test/std/utilities/meta/meta.unary/meta.unary.comp/is_bounded_array.pass.cpp
M libcxx/test/std/utilities/meta/meta.unary/meta.unary.prop/has_unique_object_representations.compile.pass.cpp
M libcxx/utils/ci/Dockerfile
M libcxx/utils/ci/docker-compose.yml
Log Message:
-----------
[libc++][Android] Update compiler and sysroot (#148998)
* Upgrade from r536225 to r563880.
* Upgrade from ab/12644632 to f8b85cc5262c6e5cbc9a92c1bab2b18b32a4c63f,
the current HEAD commit of
https://android.googlesource.com/platform/prebuilts/ndk/+/refs/heads/mirror-goog-main-ndk
The previous source of sysroots (ci.android.com), deleted its artifacts
after a short period of time, and is currently out-of-date because of
the aosp-main turndown.
Updating the Docker image also fixes two tests.
Commit: 7d2a58e87d7ab5d076adf51705b1b2253cea34bb
https://github.com/llvm/llvm-project/commit/7d2a58e87d7ab5d076adf51705b1b2253cea34bb
Author: Shilei Tian <i at tianshilei.me>
Date: 2025-07-16 (Wed, 16 Jul 2025)
Changed paths:
M clang/include/clang/Basic/BuiltinsAMDGPU.def
M clang/lib/CodeGen/TargetBuiltins/AMDGPU.cpp
M clang/test/CodeGenOpenCL/builtins-amdgcn-gfx1250.cl
M llvm/lib/Target/AMDGPU/VOP1Instructions.td
A llvm/test/CodeGen/AMDGPU/llvm.amdgcn.rsq.bf16.ll
M llvm/test/MC/AMDGPU/gfx1250_asm_vop1-fake16.s
M llvm/test/MC/AMDGPU/gfx1250_asm_vop1.s
M llvm/test/MC/AMDGPU/gfx1250_asm_vop1_dpp16-fake16.s
M llvm/test/MC/AMDGPU/gfx1250_asm_vop1_dpp16.s
M llvm/test/MC/AMDGPU/gfx1250_asm_vop1_dpp8-fake16.s
M llvm/test/MC/AMDGPU/gfx1250_asm_vop1_dpp8.s
M llvm/test/MC/AMDGPU/gfx1250_asm_vop3_from_vop1-fake16.s
M llvm/test/MC/AMDGPU/gfx1250_asm_vop3_from_vop1.s
M llvm/test/MC/AMDGPU/gfx1250_asm_vop3_from_vop1_dpp16-fake16.s
M llvm/test/MC/AMDGPU/gfx1250_asm_vop3_from_vop1_dpp16.s
M llvm/test/MC/AMDGPU/gfx1250_asm_vop3_from_vop1_dpp8-fake16.s
M llvm/test/MC/AMDGPU/gfx1250_asm_vop3_from_vop1_dpp8.s
M llvm/test/MC/Disassembler/AMDGPU/gfx1250_dasm_vop1.txt
M llvm/test/MC/Disassembler/AMDGPU/gfx1250_dasm_vop1_dpp16.txt
M llvm/test/MC/Disassembler/AMDGPU/gfx1250_dasm_vop1_dpp8.txt
M llvm/test/MC/Disassembler/AMDGPU/gfx1250_dasm_vop3_from_vop1.txt
M llvm/test/MC/Disassembler/AMDGPU/gfx1250_dasm_vop3_from_vop1_dpp16.txt
M llvm/test/MC/Disassembler/AMDGPU/gfx1250_dasm_vop3_from_vop1_dpp8.txt
Log Message:
-----------
[AMDGPU] Add support for `v_rsq_bf16` on gfx1250 (#149194)
Co-authored-by: Mekhanoshin, Stanislav <Stanislav.Mekhanoshin at amd.com>
Commit: ad6d5d28215adb3def221517b1490b8df3fd1190
https://github.com/llvm/llvm-project/commit/ad6d5d28215adb3def221517b1490b8df3fd1190
Author: Shilei Tian <i at tianshilei.me>
Date: 2025-07-16 (Wed, 16 Jul 2025)
Changed paths:
M clang/include/clang/Basic/BuiltinsAMDGPU.def
M clang/lib/CodeGen/TargetBuiltins/AMDGPU.cpp
M clang/test/CodeGenOpenCL/builtins-amdgcn-gfx1250.cl
M llvm/lib/Target/AMDGPU/VOP1Instructions.td
A llvm/test/CodeGen/AMDGPU/bf16-math.ll
A llvm/test/CodeGen/AMDGPU/llvm.amdgcn.log.bf16.ll
A llvm/test/CodeGen/AMDGPU/llvm.log2.bf16.ll
M llvm/test/MC/AMDGPU/gfx1250_asm_vop1-fake16.s
M llvm/test/MC/AMDGPU/gfx1250_asm_vop1.s
M llvm/test/MC/AMDGPU/gfx1250_asm_vop1_dpp16-fake16.s
M llvm/test/MC/AMDGPU/gfx1250_asm_vop1_dpp16.s
M llvm/test/MC/AMDGPU/gfx1250_asm_vop1_dpp8-fake16.s
M llvm/test/MC/AMDGPU/gfx1250_asm_vop1_dpp8.s
M llvm/test/MC/AMDGPU/gfx1250_asm_vop3_from_vop1-fake16.s
M llvm/test/MC/AMDGPU/gfx1250_asm_vop3_from_vop1.s
M llvm/test/MC/AMDGPU/gfx1250_asm_vop3_from_vop1_dpp16-fake16.s
M llvm/test/MC/AMDGPU/gfx1250_asm_vop3_from_vop1_dpp16.s
M llvm/test/MC/AMDGPU/gfx1250_asm_vop3_from_vop1_dpp8-fake16.s
M llvm/test/MC/AMDGPU/gfx1250_asm_vop3_from_vop1_dpp8.s
M llvm/test/MC/Disassembler/AMDGPU/gfx1250_dasm_vop1.txt
M llvm/test/MC/Disassembler/AMDGPU/gfx1250_dasm_vop1_dpp16.txt
M llvm/test/MC/Disassembler/AMDGPU/gfx1250_dasm_vop1_dpp8.txt
M llvm/test/MC/Disassembler/AMDGPU/gfx1250_dasm_vop3_from_vop1.txt
M llvm/test/MC/Disassembler/AMDGPU/gfx1250_dasm_vop3_from_vop1_dpp16.txt
M llvm/test/MC/Disassembler/AMDGPU/gfx1250_dasm_vop3_from_vop1_dpp8.txt
Log Message:
-----------
[AMDGPU] Add support for `v_log_bf16` on gfx1250 (#149201)
Co-authored-by: Mekhanoshin, Stanislav <Stanislav.Mekhanoshin at amd.com>
Commit: 0110168f6aa5c8a8d02ffd9e62c7929ce6d24d26
https://github.com/llvm/llvm-project/commit/0110168f6aa5c8a8d02ffd9e62c7929ce6d24d26
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2025-07-17 (Thu, 17 Jul 2025)
Changed paths:
M llvm/include/llvm/IR/RuntimeLibcalls.td
A llvm/test/CodeGen/X86/win32-int-runtime-libcalls.ll
Log Message:
-----------
RuntimeLibcalls: Fix calling conv of win32 div libcalls (#149098)
There's probably an existing test this should be added to,
but our test coverage is really bad that this wasn't caught
by one.
Commit: 7e0fde0c2f6b0b9d727ce9196956b36e91961ac4
https://github.com/llvm/llvm-project/commit/7e0fde0c2f6b0b9d727ce9196956b36e91961ac4
Author: Sirraide <aeternalmail at gmail.com>
Date: 2025-07-16 (Wed, 16 Jul 2025)
Changed paths:
M clang/tools/libclang/libclang.map
Log Message:
-----------
[Clang] Reintroduce obsolete symbols in libclang.map (#149190)
This is a follow-up to #149079. Seems like we forgot about the fact that
the symbols also need to be in `libclang.map`.
Commit: 86c63e6bd66f9db9c7320155da7a2042407b5a1a
https://github.com/llvm/llvm-project/commit/86c63e6bd66f9db9c7320155da7a2042407b5a1a
Author: royitaqi <royitaqi at users.noreply.github.com>
Date: 2025-07-16 (Wed, 16 Jul 2025)
Changed paths:
M lldb/source/Interpreter/CommandInterpreter.cpp
Log Message:
-----------
[lldb] [cosmetic] Update help message of `(lldb) b` (#149114)
`(lldb) b` can be used in two different ways:
1. Running `b` without arguments, it lists all existing breakpoints.
2. Running `b` with arguments, it adds breakpoints.
However, the help message doesn't mention the first use case. This patch
adds help message to mention it.
**Without patch**:
```
(lldb) help b
Set a breakpoint using one of several shorthand formats. Expects 'raw' input (see 'help raw-input'.)
Syntax:
_regexp-break <filename>:<linenum>:<colnum>
main.c:12:21 // Break at line 12 and column 21 of main.c
...
```
**With patch**:
```
(lldb) help b
Set a breakpoint using one of several shorthand formats, or list the
existing breakpoints if no arguments are provided. Expects 'raw' input
(see 'help raw-input'.)
Syntax:
_regexp-break <filename>:<linenum>:<colnum>
main.c:12:21 // Break at line 12 and column 21 of main.c
...
_regexp-break
// List the existing breakpoints
```
Commit: 26b0b279deca7cd660efcae5c17bd27a15ead36d
https://github.com/llvm/llvm-project/commit/26b0b279deca7cd660efcae5c17bd27a15ead36d
Author: Stanislav Mekhanoshin <Stanislav.Mekhanoshin at amd.com>
Date: 2025-07-16 (Wed, 16 Jul 2025)
Changed paths:
M llvm/lib/Target/AMDGPU/FLATInstructions.td
A llvm/test/CodeGen/AMDGPU/flat-saddr-store.ll
Log Message:
-----------
[AMDGPU] Select flat GVS stores on gfx1250 (#149203)
Commit: 81eb7defa23dcf48a8e51391543eb210df232440
https://github.com/llvm/llvm-project/commit/81eb7defa23dcf48a8e51391543eb210df232440
Author: Cristian Assaiante <assaiante at diag.uniroma1.it>
Date: 2025-07-16 (Wed, 16 Jul 2025)
Changed paths:
M clang/test/CodeGen/new-pass-manager-opt-bisect.c
M llvm/include/llvm/IR/OptBisect.h
M llvm/include/llvm/Pass.h
M llvm/lib/IR/OptBisect.cpp
M llvm/lib/IR/Pass.cpp
M llvm/lib/Passes/StandardInstrumentations.cpp
M llvm/test/Other/opt-bisect-new-pass-manager.ll
A llvm/test/Other/opt-disable.ll
Log Message:
-----------
[OptBisect][IR] Adding a new OptPassGate for disabling passes via name (#145059)
This commit adds a new pass gate that allows selective disabling
of one or more passes via the clang command line using the
`-opt-disable` option. Passes to be disabled should be specified as a
comma-separated list of their names.
The implementation resides in the same file as the bisection tool. The
`getGlobalPassGate()` function returns the currently enabled gate.
Example: `-opt-disable="PassA,PassB"`
Pass names are matched using case-insensitive comparisons. However, note
that special characters, including spaces, must be included exactly as
they appear in the pass names.
Additionally, a `-opt-disable-enable-verbosity` flag has been introduced to
enable verbose output when this functionality is in use. When enabled,
it prints the status of all passes (either running or NOT running),
similar to the default behavior of `-opt-bisect-limit`. This flag is
disabled by default, which is the opposite of the `-opt-bisect-verbose`
flag (which defaults to enabled).
To validate this functionality, a test file has also been provided. It reuses
the same infrastructure as the opt-bisect test, but disables three
specific passes and checks the output to ensure the expected behavior.
---------
Co-authored-by: Nikita Popov <github at npopov.com>
Commit: 210cf010c3362e5648d037ea5e4b27c2673837ed
https://github.com/llvm/llvm-project/commit/210cf010c3362e5648d037ea5e4b27c2673837ed
Author: Valentin Clement (バレンタイン クレメン) <clementval at gmail.com>
Date: 2025-07-16 (Wed, 16 Jul 2025)
Changed paths:
M flang/include/flang/Optimizer/Builder/IntrinsicCall.h
M flang/lib/Optimizer/Builder/IntrinsicCall.cpp
M flang/module/cudadevice.f90
M flang/test/Lower/CUDA/cuda-device-proc.cuf
Log Message:
-----------
[flang][cuda] Lower globaltimer to NVVM op (#149217)
Commit: 9d78eb5cc51820bd7076861a9ad175e5666b90d3
https://github.com/llvm/llvm-project/commit/9d78eb5cc51820bd7076861a9ad175e5666b90d3
Author: Wenju He <wenju.he at intel.com>
Date: 2025-07-17 (Thu, 17 Jul 2025)
Changed paths:
M libclc/CMakeLists.txt
Log Message:
-----------
[libclc] Enable -fdiscard-value-names build flag to reduce bitcode size (#149016)
The flag reduces nvptx64--nvidiacl.bc size from 10.6MB to 5.2MB.
Commit: b52cf756ced2aefd05b7e2f01026c941f9a04c47
https://github.com/llvm/llvm-project/commit/b52cf756ced2aefd05b7e2f01026c941f9a04c47
Author: Changpeng Fang <changpeng.fang at amd.com>
Date: 2025-07-16 (Wed, 16 Jul 2025)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPUInsertDelayAlu.cpp
M llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
M llvm/lib/Target/AMDGPU/SIInstrInfo.h
M llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp
M llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.h
A llvm/test/CodeGen/AMDGPU/insert-delay-alu-wmma-xdl.mir
Log Message:
-----------
AMDGPU: Treat WMMA XDL ops as TRANS in S_DELAY_ALU insertion for gfx1250 (#149208)
WMMA XDL instructions are tracked as TRANs ops and the compiler should
consider them the same as TRANS in S_DELAY_ALU insertion. We use a searchable
table for the InsertDelayAlu pass to recognize these WMMA XDL instructions.
Co-authored-by: Stefan Stipanovic <Stefan.Stipanovic at amd.com>
Commit: 4cf7670b01fb5b01995cf89fe4304bfb0c69a4c0
https://github.com/llvm/llvm-project/commit/4cf7670b01fb5b01995cf89fe4304bfb0c69a4c0
Author: Valentin Clement (バレンタイン クレメン) <clementval at gmail.com>
Date: 2025-07-16 (Wed, 16 Jul 2025)
Changed paths:
M flang/include/flang/Optimizer/Builder/IntrinsicCall.h
M flang/lib/Optimizer/Builder/IntrinsicCall.cpp
M flang/module/cudadevice.f90
M flang/test/Lower/CUDA/cuda-device-proc.cuf
Log Message:
-----------
[flang][cuda] Lower clock() to NNVM op (#149228)
Also use a same gen function for all NVVM time ops.
Commit: f56211ebfa7f9ca71b9eeb119012b0f6e1a2b2c9
https://github.com/llvm/llvm-project/commit/f56211ebfa7f9ca71b9eeb119012b0f6e1a2b2c9
Author: Craig Topper <craig.topper at sifive.com>
Date: 2025-07-16 (Wed, 16 Jul 2025)
Changed paths:
M llvm/test/CodeGen/RISCV/xqcisls.ll
Log Message:
-----------
[RISCV] Add/remove/simplify tests in xqcisls.ll. NFC
-Don't use i64 for GEP indices.
-Remove tests that zero extended GEP indices from i32 to i64.
-Add i64 load/store tests taken from xtheadmemidx that get split into two i32 load/store.
-Don't extend load results to i64.
I'm working on improvements to SelectAddrRegRegScale.
Commit: 0692572e040979b2de0dceb8f0537aa16caf351f
https://github.com/llvm/llvm-project/commit/0692572e040979b2de0dceb8f0537aa16caf351f
Author: Ryotaro Kasuga <kasuga.ryotaro at fujitsu.com>
Date: 2025-07-17 (Thu, 17 Jul 2025)
Changed paths:
M clang/lib/CodeGen/CGLoopInfo.cpp
M clang/test/CodeGenCXX/pragma-loop.cpp
Log Message:
-----------
[clang][CodeGen] Fix metadata when vectorization is disabled by pragma (#135163)
Currently, when specifying `vectorize(disable) unroll_count(8)`, the
generated metadata appears as follows:
```
!loop0 = !{!"loop0", !vectorize_width, !followup}
!vectorize_width = !{!"llvm.loop.vectorize.width", i32 1}
!followup = !{!"llvm.loop.vectorize.followup_all", !unroll}
!unroll = !{!"llvm.loop.unroll_count", i32 8}
```
Since the metadata `!vectorize_width` implies that the vectorization is
disabled, the vectorization process is skipped, and the `!followup`
metadata is not processed correctly.
This patch addresses the issue by directly appending properties to the
metadata node when vectorization is disabled, instead of creating a new
follow-up MDNode. In the above case, the generated metadata will now
look like this:
```
!loop0 = !{!"loop0", !vectorize_width, !vectorize_width, !unroll}
!vectorize_width = !{!"llvm.loop.vectorize.width", i32 1}
!unroll = !{!"llvm.loop.unroll_count", i32 8}
```
Commit: b41398294c85eacdb37b9637eed6f0e91edf35cf
https://github.com/llvm/llvm-project/commit/b41398294c85eacdb37b9637eed6f0e91edf35cf
Author: Wenju He <wenju.he at intel.com>
Date: 2025-07-17 (Thu, 17 Jul 2025)
Changed paths:
M clang/lib/Basic/Targets/SPIR.h
A clang/test/CodeGenOpenCL/scoped-atomic.cl
Log Message:
-----------
[SPIR] Set MaxAtomicInlineWidth minimum size to 32 for spir32 and 64 for spir64 (#148997)
Set MaxAtomicInlineWidth the same way as SPIR-V targets in 3cfd0c0d3697.
This PR fixes build warning in scoped atomic built-in in #146814:
`warning: large atomic operation may incur significant performance
penalty; ; the access size (2 bytes) exceeds the max lock-free size (0
bytes) [-Watomic-alignment]`
Commit: b9adc4a59cb50c98ec0e01645ea5eb64e6628afd
https://github.com/llvm/llvm-project/commit/b9adc4a59cb50c98ec0e01645ea5eb64e6628afd
Author: Philip Reames <preames at rivosinc.com>
Date: 2025-07-16 (Wed, 16 Jul 2025)
Changed paths:
M llvm/include/llvm/CodeGen/TargetLowering.h
M llvm/lib/CodeGen/InterleavedAccessPass.cpp
M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
M llvm/lib/Target/AArch64/AArch64ISelLowering.h
M llvm/lib/Target/RISCV/RISCVISelLowering.h
M llvm/lib/Target/RISCV/RISCVInterleavedAccess.cpp
Log Message:
-----------
[IA] Use a single callback for lowerInterleaveIntrinsic [nfc] (#148978) (#149168)
This continues in the direction started by commit 4b81dc7. We
essentially merges the handling for VPStore - currently in
lowerInterleavedVPStore which is shared between shuffle and intrinsic
based interleaves - into the existing dedicated routine.
Commit: 34951f7de80c4b4ac2b884d08dd919efed23c024
https://github.com/llvm/llvm-project/commit/34951f7de80c4b4ac2b884d08dd919efed23c024
Author: Valentin Clement (バレンタイン クレメン) <clementval at gmail.com>
Date: 2025-07-16 (Wed, 16 Jul 2025)
Changed paths:
M flang/include/flang/Optimizer/Builder/IntrinsicCall.h
M flang/lib/Optimizer/Builder/IntrinsicCall.cpp
M flang/test/Lower/CUDA/cuda-device-proc.cuf
Log Message:
-----------
[flang][cuda] Use NVVM op for clock64 (#149223)
Commit: b36188514a76ba979439a1dcab58e68478e3f0ad
https://github.com/llvm/llvm-project/commit/b36188514a76ba979439a1dcab58e68478e3f0ad
Author: Philip Reames <preames at rivosinc.com>
Date: 2025-07-16 (Wed, 16 Jul 2025)
Changed paths:
M llvm/lib/Target/RISCV/RISCVInterleavedAccess.cpp
M llvm/test/CodeGen/RISCV/rvv/vp-vector-interleaved-access.ll
Log Message:
-----------
[RISCV][IA] Check nuw on multiply when analyzing EVL (#149205)
If we're checking to see if a number is a multiple of a small constant,
we need to be sure the multiply doesn't overflow for the mul logic to
hold. The VL is a unsigned number, so we care about unsigned overflow.
Once we've proven a number of a multiple, we can also use an
exact udiv as we know we're not discarding any bits.
This fixes what is technically a miscompile with EVL vectorization, but
I doubt we'd ever have seen it in practice since most EVLs are going to
much less than UINT_MAX.
Commit: 34b3ea367c4299ebd7c37edc7c748c9627ee66cb
https://github.com/llvm/llvm-project/commit/34b3ea367c4299ebd7c37edc7c748c9627ee66cb
Author: Christopher Ferris <cferris1000 at users.noreply.github.com>
Date: 2025-07-16 (Wed, 16 Jul 2025)
Changed paths:
M compiler-rt/lib/scudo/standalone/tests/common_test.cpp
Log Message:
-----------
[scudo] Make release to OS test more specific. (#147852)
The original version of ResidentMemorySize could be a little flaky.
Replace the test with a version that verifies exactly how much of the
map is resident.
Commit: 1f1fd07c325f174be27d6f10a512882770a976a8
https://github.com/llvm/llvm-project/commit/1f1fd07c325f174be27d6f10a512882770a976a8
Author: Ryan Buchner <buchner.ryan at gmail.com>
Date: 2025-07-16 (Wed, 16 Jul 2025)
Changed paths:
M llvm/lib/Transforms/InstCombine/InstCombineSelect.cpp
M llvm/test/Transforms/InstCombine/icmp-select.ll
A llvm/test/Transforms/InstCombine/select-fixed-zero.ll
M llvm/test/Transforms/InstCombine/select.ll
Log Message:
-----------
[InstCombine] Optimize (select %x, op(%x), 0) to op(%x) for operations where op(0) == 0 (#147605)
Currently this optimization only occurs for `mul`, but this generalizes
that for any operation that has a fixed point of `0`.
There is similar logic within `EarlyCSE` pass, but that is stricter in
terms of `poison` propagation so will not optimize for many operations.
Alive2 Proofs:
`and`:
https://alive2.llvm.org/ce/z/RraasX ; base-case
https://alive2.llvm.org/ce/z/gzfFTX ; commuted-case
https://alive2.llvm.org/ce/z/63XaoX ; compare against undef
https://alive2.llvm.org/ce/z/MVRVNd ; select undef
https://alive2.llvm.org/ce/z/2bsoYG ; vector
https://alive2.llvm.org/ce/z/xByeX- ; vector compare against undef
https://alive2.llvm.org/ce/z/zNdzmZ ; vector select undef
`fshl`:
https://alive2.llvm.org/ce/z/U3_PG3 ; base-case
https://alive2.llvm.org/ce/z/BWCnxT ; compare against undef
https://alive2.llvm.org/ce/z/8HGAE_ ; select undef
; vector times out
`fshr`:
https://alive2.llvm.org/ce/z/o6F47G ; base-case
https://alive2.llvm.org/ce/z/fVnBXy ; compare against undef
https://alive2.llvm.org/ce/z/suymYJ ; select undef
; vector times out
`umin`:
https://alive2.llvm.org/ce/z/GGMqf6 ; base-case
https://alive2.llvm.org/ce/z/6cx5-k ; commuted-case
https://alive2.llvm.org/ce/z/W5d9tz ; compare against undef
https://alive2.llvm.org/ce/z/nKbaUn ; select undef
https://alive2.llvm.org/ce/z/gxEGqc ; vector
https://alive2.llvm.org/ce/z/_SDpi_ ; vector compare against undef
`sdiv`:
https://alive2.llvm.org/ce/z/5XGs3q
`srem`:
https://alive2.llvm.org/ce/z/vXAnQM
`udiv`:
https://alive2.llvm.org/ce/z/e6_8Ug
`urem`:
https://alive2.llvm.org/ce/z/VmM2SL
`shl`:
https://alive2.llvm.org/ce/z/aCZr3u ; Argument with range
https://alive2.llvm.org/ce/z/YgDy8C ; Instruction with known bits
https://alive2.llvm.org/ce/z/6pIxR6 ; Constant
`lshr`:
https://alive2.llvm.org/ce/z/WCCBej
`ashr:
https://alive2.llvm.org/ce/z/egV4TR
---------
Co-authored-by: Ryan Buchner <rbuchner at ventanamicro.com>
Co-authored-by: Yingwei Zheng <dtcxzyw at qq.com>
Commit: 283a62fa5b9f2b07fb74336dbce91f346801225f
https://github.com/llvm/llvm-project/commit/283a62fa5b9f2b07fb74336dbce91f346801225f
Author: Jeffrey Byrnes <jeffrey.byrnes at amd.com>
Date: 2025-07-16 (Wed, 16 Jul 2025)
Changed paths:
M llvm/lib/Target/AMDGPU/GCNSchedStrategy.cpp
Log Message:
-----------
[AMDGPU] NFC: Decouple getRealRegPressure from current region (#149219)
We're already accepting a RegionIdx for the LiveIns, also use this for
the instruction iterators.
Enables querying RP for other regions -- useful for function wide
transformations (e.g. rematerialization, rewriting, etc).
Commit: 86062e2d3837f85f18295fe321f1e0b4c13f604e
https://github.com/llvm/llvm-project/commit/86062e2d3837f85f18295fe321f1e0b4c13f604e
Author: Aiden Grossman <aidengrossman at google.com>
Date: 2025-07-16 (Wed, 16 Jul 2025)
Changed paths:
M clang-tools-extra/clang-doc/JSONGenerator.cpp
M clang/include/clang/Basic/BuiltinsAMDGPU.def
M clang/include/clang/Basic/BuiltinsSPIRVVK.td
M clang/include/clang/Basic/DiagnosticSemaKinds.td
M clang/include/clang/CIR/Dialect/Builder/CIRBaseBuilder.h
M clang/include/clang/CIR/Dialect/IR/CIROps.td
M clang/include/clang/CIR/MissingFeatures.h
M clang/lib/Basic/Targets/SPIR.h
M clang/lib/CIR/CodeGen/CIRGenBuilder.h
M clang/lib/CIR/CodeGen/CIRGenBuiltin.cpp
M clang/lib/CIR/CodeGen/CIRGenExprComplex.cpp
M clang/lib/CIR/CodeGen/CIRGenFunction.h
M clang/lib/CIR/Dialect/Transforms/LoweringPrepare.cpp
M clang/lib/CIR/Lowering/DirectToLLVM/LowerToLLVM.cpp
M clang/lib/CIR/Lowering/DirectToLLVM/LowerToLLVM.h
M clang/lib/CodeGen/CGLoopInfo.cpp
M clang/lib/CodeGen/TargetBuiltins/AMDGPU.cpp
M clang/lib/CodeGen/TargetBuiltins/SPIR.cpp
M clang/lib/Headers/hlsl/hlsl_intrinsic_helpers.h
M clang/lib/Headers/hlsl/hlsl_intrinsics.h
M clang/lib/Sema/SemaOpenACC.cpp
M clang/lib/Sema/SemaSPIRV.cpp
M clang/test/CIR/CodeGen/builtin_bit.cpp
A clang/test/CIR/CodeGen/complex-unary.cpp
M clang/test/CXX/drs/cwg8xx.cpp
M clang/test/CXX/module/dcl.dcl/dcl.module/dcl.module.interface/p1.cppm
M clang/test/CXX/module/module.interface/p1.cpp
M clang/test/CodeGen/PowerPC/builtins-ppc-fpconstrained.c
M clang/test/CodeGen/new-pass-manager-opt-bisect.c
M clang/test/CodeGenCXX/pragma-loop.cpp
A clang/test/CodeGenHLSL/builtins/refract.hlsl
M clang/test/CodeGenOpenCL/builtins-amdgcn-gfx1250.cl
A clang/test/CodeGenOpenCL/scoped-atomic.cl
A clang/test/CodeGenSPIRV/Builtins/refract.c
M clang/test/Modules/cxx20-10-2-ex1.cpp
M clang/test/Modules/cxx20-export-import.cpp
M clang/test/Modules/cxx20-import-diagnostics-a.cpp
M clang/test/Modules/export-in-non-modules.cpp
A clang/test/SemaHLSL/BuiltIns/refract-errors.hlsl
A clang/test/SemaOpenACC/private_firstprivate_reduction_required_ops.cpp
A clang/test/SemaSPIRV/BuiltIns/refract-errors.c
M clang/tools/libclang/libclang.map
M compiler-rt/lib/scudo/standalone/tests/common_test.cpp
M flang-rt/include/flang-rt/runtime/non-tbp-dio.h
M flang-rt/include/flang-rt/runtime/type-info.h
M flang-rt/lib/runtime/derived.cpp
M flang-rt/lib/runtime/descriptor-io.cpp
M flang-rt/lib/runtime/extensions.cpp
M flang-rt/lib/runtime/non-tbp-dio.cpp
M flang-rt/lib/runtime/type-info.cpp
M flang/docs/Intrinsics.md
A flang/docs/ParallelMultiImageFortranRuntime.md
M flang/docs/index.md
M flang/include/flang/Optimizer/Builder/IntrinsicCall.h
M flang/include/flang/Parser/message.h
M flang/include/flang/Runtime/extensions.h
M flang/include/flang/Semantics/runtime-type-info.h
M flang/lib/Frontend/FrontendAction.cpp
M flang/lib/Lower/ConvertVariable.cpp
M flang/lib/Lower/IO.cpp
M flang/lib/Optimizer/Builder/IntrinsicCall.cpp
M flang/lib/Optimizer/CodeGen/LowerRepackArrays.cpp
M flang/lib/Optimizer/Transforms/CUFDeviceGlobal.cpp
M flang/lib/Parser/message.cpp
M flang/lib/Semantics/check-declarations.cpp
M flang/lib/Semantics/expression.cpp
M flang/lib/Semantics/runtime-type-info.cpp
M flang/lib/Semantics/semantics.cpp
M flang/lib/Semantics/tools.cpp
M flang/module/__fortran_type_info.f90
M flang/module/cudadevice.f90
A flang/test/Driver/fatal-errors-warnings.f90
M flang/test/Fir/CUDA/cuda-device-global.f90
M flang/test/Lower/CUDA/cuda-device-proc.cuf
M flang/test/Lower/io-derived-type.f90
M flang/test/Lower/namelist.f90
M flang/test/Lower/volatile-openmp.f90
A flang/test/Semantics/bind-c18.f90
A flang/test/Semantics/bug148559.f90
A flang/test/Semantics/bug148675.f90
M flang/test/Semantics/typeinfo01.f90
M flang/test/Semantics/typeinfo02.f90
M flang/test/Semantics/typeinfo09.f90
M flang/test/Semantics/typeinfo13.f90
M flang/test/Transforms/lower-repack-arrays.fir
M libc/fuzzing/math/acos_fuzz.cpp
M libc/fuzzing/math/asin_fuzz.cpp
M libc/fuzzing/math/cos_fuzz.cpp
M libc/fuzzing/math/exp10_fuzz.cpp
M libc/fuzzing/math/exp2_fuzz.cpp
M libc/fuzzing/math/exp_fuzz.cpp
M libc/fuzzing/math/expm1_fuzz.cpp
M libc/fuzzing/math/log10_fuzz.cpp
M libc/fuzzing/math/log1p_fuzz.cpp
M libc/fuzzing/math/log2_fuzz.cpp
M libc/fuzzing/math/log_fuzz.cpp
M libc/fuzzing/math/sin_fuzz.cpp
M libc/fuzzing/math/sincos_fuzz.cpp
M libc/fuzzing/math/sqrt_fuzz.cpp
M libc/fuzzing/math/tan_fuzz.cpp
M libc/shared/math.h
A libc/shared/math/exp10.h
M libc/src/__support/FPUtil/PolyEval.h
M libc/src/__support/FPUtil/double_double.h
M libc/src/__support/math/CMakeLists.txt
A libc/src/__support/math/exp10.h
M libc/src/math/generic/CMakeLists.txt
M libc/src/math/generic/exp10.cpp
M libclc/CMakeLists.txt
M libcxx/test/std/utilities/meta/meta.unary/meta.unary.comp/is_bounded_array.pass.cpp
M libcxx/test/std/utilities/meta/meta.unary/meta.unary.prop/has_unique_object_representations.compile.pass.cpp
M libcxx/utils/ci/Dockerfile
M libcxx/utils/ci/docker-compose.yml
M lld/MachO/Arch/ARM64.cpp
M lld/MachO/CMakeLists.txt
A lld/MachO/LinkerOptimizationHints.cpp
A lld/MachO/LinkerOptimizationHints.h
M lld/MachO/Target.h
M lld/MachO/Writer.cpp
A lld/test/MachO/loh-arm64-32.s
M lldb/docs/resources/build.rst
M lldb/docs/resources/qemu-testing.rst
M lldb/docs/use/mcp.md
M lldb/source/Commands/CommandObjectDWIMPrint.cpp
M lldb/source/Commands/CommandObjectExpression.cpp
M lldb/source/Interpreter/CommandInterpreter.cpp
A lldb/test/Shell/Settings/TestChildCountTruncation.test
M llvm/docs/LangRef.rst
M llvm/include/llvm/Analysis/VectorUtils.h
M llvm/include/llvm/CodeGen/TargetLowering.h
M llvm/include/llvm/IR/IntrinsicsSPIRV.td
M llvm/include/llvm/IR/OptBisect.h
M llvm/include/llvm/IR/RuntimeLibcalls.td
M llvm/include/llvm/Pass.h
M llvm/lib/Analysis/VectorUtils.cpp
M llvm/lib/CodeGen/GlobalMergeFunctions.cpp
M llvm/lib/CodeGen/InterleavedAccessPass.cpp
M llvm/lib/CodeGen/StackProtector.cpp
M llvm/lib/IR/OptBisect.cpp
M llvm/lib/IR/Pass.cpp
M llvm/lib/IR/Verifier.cpp
M llvm/lib/Passes/StandardInstrumentations.cpp
M llvm/lib/Support/BLAKE3/blake3_neon.c
M llvm/lib/Support/raw_socket_stream.cpp
M llvm/lib/TableGen/TGLexer.cpp
M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
M llvm/lib/Target/AArch64/AArch64ISelLowering.h
M llvm/lib/Target/AArch64/AArch64InstrInfo.cpp
M llvm/lib/Target/AMDGPU/AMDGPU.td
M llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp
M llvm/lib/Target/AMDGPU/AMDGPUInsertDelayAlu.cpp
M llvm/lib/Target/AMDGPU/FLATInstructions.td
M llvm/lib/Target/AMDGPU/GCNHazardRecognizer.cpp
M llvm/lib/Target/AMDGPU/GCNHazardRecognizer.h
M llvm/lib/Target/AMDGPU/GCNSchedStrategy.cpp
M llvm/lib/Target/AMDGPU/GCNSubtarget.h
M llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
M llvm/lib/Target/AMDGPU/SIInstrInfo.h
M llvm/lib/Target/AMDGPU/SIInstructions.td
M llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp
M llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.h
M llvm/lib/Target/AMDGPU/VOP1Instructions.td
M llvm/lib/Target/AMDGPU/VOP3Instructions.td
M llvm/lib/Target/RISCV/RISCVISelLowering.h
M llvm/lib/Target/RISCV/RISCVInterleavedAccess.cpp
M llvm/lib/Target/RISCV/RISCVSchedSpacemitX60.td
M llvm/lib/Target/RISCV/RISCVVLOptimizer.cpp
M llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp
M llvm/lib/Transforms/InstCombine/InstCombineSelect.cpp
A llvm/test/CodeGen/AArch64/cgdata-no-merge-unnamed.ll
M llvm/test/CodeGen/AArch64/machine-outliner-safe-range-in-middle.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-bswap.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fshr.mir
A llvm/test/CodeGen/AMDGPU/bf16-math.ll
M llvm/test/CodeGen/AMDGPU/branch-folding-implicit-def-subreg.ll
A llvm/test/CodeGen/AMDGPU/flat-saddr-load.ll
A llvm/test/CodeGen/AMDGPU/flat-saddr-store.ll
A llvm/test/CodeGen/AMDGPU/insert-delay-alu-wmma-xdl.mir
A llvm/test/CodeGen/AMDGPU/llvm.amdgcn.log.bf16.ll
A llvm/test/CodeGen/AMDGPU/llvm.amdgcn.rsq.bf16.ll
A llvm/test/CodeGen/AMDGPU/llvm.log2.bf16.ll
M llvm/test/CodeGen/AMDGPU/llvm.sqrt.bf16.ll
A llvm/test/CodeGen/AMDGPU/select-cmp-shared-constant-fp.ll
A llvm/test/CodeGen/AMDGPU/select-cmp-shared-constant-int.ll
A llvm/test/CodeGen/AMDGPU/trans-coexecution-hazard.mir
A llvm/test/CodeGen/PowerPC/spe-vsx-incompatibility.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-deinterleave-load.ll
M llvm/test/CodeGen/RISCV/rvv/vl-opt-instrs.ll
M llvm/test/CodeGen/RISCV/rvv/vl-opt-op-info.mir
M llvm/test/CodeGen/RISCV/rvv/vp-vector-interleaved-access.ll
M llvm/test/CodeGen/RISCV/rvv/vxrm-insert-out-of-loop.ll
M llvm/test/CodeGen/RISCV/xqcisls.ll
A llvm/test/CodeGen/SPIRV/hlsl-intrinsics/refract.ll
A llvm/test/CodeGen/SPIRV/opencl/refract-error.ll
A llvm/test/CodeGen/X86/win32-int-runtime-libcalls.ll
M llvm/test/MC/AMDGPU/gfx10_asm_vop3.s
M llvm/test/MC/AMDGPU/gfx1250_asm_vflat.s
M llvm/test/MC/AMDGPU/gfx1250_asm_vop1-fake16.s
M llvm/test/MC/AMDGPU/gfx1250_asm_vop1.s
M llvm/test/MC/AMDGPU/gfx1250_asm_vop1_dpp16-fake16.s
M llvm/test/MC/AMDGPU/gfx1250_asm_vop1_dpp16.s
M llvm/test/MC/AMDGPU/gfx1250_asm_vop1_dpp8-fake16.s
M llvm/test/MC/AMDGPU/gfx1250_asm_vop1_dpp8.s
M llvm/test/MC/AMDGPU/gfx1250_asm_vop3_from_vop1-fake16.s
M llvm/test/MC/AMDGPU/gfx1250_asm_vop3_from_vop1.s
M llvm/test/MC/AMDGPU/gfx1250_asm_vop3_from_vop1_dpp16-fake16.s
M llvm/test/MC/AMDGPU/gfx1250_asm_vop3_from_vop1_dpp16.s
M llvm/test/MC/AMDGPU/gfx1250_asm_vop3_from_vop1_dpp8-fake16.s
M llvm/test/MC/AMDGPU/gfx1250_asm_vop3_from_vop1_dpp8.s
M llvm/test/MC/AMDGPU/gfx7_err_pos.s
M llvm/test/MC/AMDGPU/gfx8_err_pos.s
M llvm/test/MC/AMDGPU/gfx9_asm_vop3_e64.s
M llvm/test/MC/Disassembler/AMDGPU/gfx10_vop3.txt
M llvm/test/MC/Disassembler/AMDGPU/gfx1250_dasm_vflat.txt
M llvm/test/MC/Disassembler/AMDGPU/gfx1250_dasm_vop1.txt
M llvm/test/MC/Disassembler/AMDGPU/gfx1250_dasm_vop1_dpp16.txt
M llvm/test/MC/Disassembler/AMDGPU/gfx1250_dasm_vop1_dpp8.txt
M llvm/test/MC/Disassembler/AMDGPU/gfx1250_dasm_vop3_from_vop1.txt
M llvm/test/MC/Disassembler/AMDGPU/gfx1250_dasm_vop3_from_vop1_dpp16.txt
M llvm/test/MC/Disassembler/AMDGPU/gfx1250_dasm_vop3_from_vop1_dpp8.txt
M llvm/test/MC/Disassembler/AMDGPU/gfx9_vop3.txt
M llvm/test/Other/opt-bisect-new-pass-manager.ll
A llvm/test/Other/opt-disable.ll
M llvm/test/Transforms/InstCombine/icmp-select.ll
A llvm/test/Transforms/InstCombine/select-fixed-zero.ll
M llvm/test/Transforms/InstCombine/select.ll
M llvm/test/Transforms/InterleavedAccess/AArch64/fixed-deinterleave-intrinsics.ll
M llvm/test/Transforms/InterleavedAccess/AArch64/scalable-deinterleave-intrinsics.ll
M llvm/test/Transforms/InterleavedAccess/AArch64/sve-deinterleave4.ll
M llvm/test/Transforms/InterleavedAccess/AArch64/sve-interleaved-accesses.ll
M llvm/test/Transforms/LoopInterchange/reductions-non-wrapped-operations.ll
A llvm/test/Transforms/StackProtector/cross-dso-cfi-stack-chk-fail.ll
A llvm/test/Transforms/StackProtector/stack-chk-fail-alias.ll
M llvm/test/tools/llvm-mca/RISCV/SpacemitX60/atomic.s
M llvm/test/tools/llvm-mca/RISCV/SpacemitX60/floating-point.s
M llvm/test/tools/llvm-mca/RISCV/SpacemitX60/integer.s
A llvm/test/tools/llvm-mca/RISCV/SpacemitX60/rvv-arithmetic.s
A llvm/test/tools/llvm-mca/RISCV/SpacemitX60/rvv-bitwise.s
A llvm/test/tools/llvm-mca/RISCV/SpacemitX60/rvv-comparison.s
A llvm/test/tools/llvm-mca/RISCV/SpacemitX60/rvv-conversion.s
A llvm/test/tools/llvm-mca/RISCV/SpacemitX60/rvv-fma.s
A llvm/test/tools/llvm-mca/RISCV/SpacemitX60/rvv-fp.s
A llvm/test/tools/llvm-mca/RISCV/SpacemitX60/rvv-mask.s
A llvm/test/tools/llvm-mca/RISCV/SpacemitX60/rvv-minmax.s
A llvm/test/tools/llvm-mca/RISCV/SpacemitX60/rvv-mul-div.s
A llvm/test/tools/llvm-mca/RISCV/SpacemitX60/rvv-permutation.s
A llvm/test/tools/llvm-mca/RISCV/SpacemitX60/rvv-reduction.s
M llvm/utils/TableGen/Common/CodeGenRegisters.cpp
M llvm/utils/TableGen/Common/CodeGenRegisters.h
M llvm/utils/TableGen/RegisterInfoEmitter.cpp
M llvm/utils/gn/secondary/lld/MachO/BUILD.gn
M offload/liboffload/src/OffloadImpl.cpp
M offload/unittests/OffloadAPI/symbol/olGetSymbol.cpp
M third-party/benchmark/src/sysinfo.cc
M utils/bazel/llvm-project-overlay/libc/BUILD.bazel
Log Message:
-----------
Merge branch 'main' into users/ilovepi/clang-version-fix-libcxx
Compare: https://github.com/llvm/llvm-project/compare/bd6dd16ec5ef...86062e2d3837
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