[all-commits] [llvm/llvm-project] 1f1fd0: [InstCombine] Optimize (select %x, op(%x), 0) to o...

[Ryan Buchner via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 1f1fd07c325f174be27d6f10a512882770a976a8
      https://github.com/llvm/llvm-project/commit/1f1fd07c325f174be27d6f10a512882770a976a8
  Author: Ryan Buchner <buchner.ryan at gmail.com>
  Date:   2025-07-16 (Wed, 16 Jul 2025)

  Changed paths:
    M llvm/lib/Transforms/InstCombine/InstCombineSelect.cpp
    M llvm/test/Transforms/InstCombine/icmp-select.ll
    A llvm/test/Transforms/InstCombine/select-fixed-zero.ll
    M llvm/test/Transforms/InstCombine/select.ll

  Log Message:
  -----------
  [InstCombine] Optimize (select %x, op(%x), 0) to op(%x) for operations where op(0) == 0  (#147605)

Currently this optimization only occurs for `mul`, but this generalizes
that for any operation that has a fixed point of `0`.

There is similar logic within `EarlyCSE` pass, but that is stricter in
terms of `poison` propagation so will not optimize for many operations.

Alive2 Proofs:
`and`:
https://alive2.llvm.org/ce/z/RraasX ; base-case
https://alive2.llvm.org/ce/z/gzfFTX ; commuted-case
https://alive2.llvm.org/ce/z/63XaoX ; compare against undef
https://alive2.llvm.org/ce/z/MVRVNd ; select undef
https://alive2.llvm.org/ce/z/2bsoYG ; vector
https://alive2.llvm.org/ce/z/xByeX- ; vector compare against undef
https://alive2.llvm.org/ce/z/zNdzmZ ; vector select undef

`fshl`:
https://alive2.llvm.org/ce/z/U3_PG3 ; base-case
https://alive2.llvm.org/ce/z/BWCnxT ; compare against undef
https://alive2.llvm.org/ce/z/8HGAE_ ; select undef
; vector times out

`fshr`:
https://alive2.llvm.org/ce/z/o6F47G ; base-case
https://alive2.llvm.org/ce/z/fVnBXy ; compare against undef
https://alive2.llvm.org/ce/z/suymYJ ; select undef
; vector times out

`umin`:
https://alive2.llvm.org/ce/z/GGMqf6 ; base-case
https://alive2.llvm.org/ce/z/6cx5-k ; commuted-case
https://alive2.llvm.org/ce/z/W5d9tz ; compare against undef
https://alive2.llvm.org/ce/z/nKbaUn ; select undef
https://alive2.llvm.org/ce/z/gxEGqc ; vector
https://alive2.llvm.org/ce/z/_SDpi_ ; vector compare against undef

`sdiv`:
https://alive2.llvm.org/ce/z/5XGs3q

`srem`:
https://alive2.llvm.org/ce/z/vXAnQM

`udiv`:
https://alive2.llvm.org/ce/z/e6_8Ug

`urem`:
https://alive2.llvm.org/ce/z/VmM2SL

`shl`:
https://alive2.llvm.org/ce/z/aCZr3u ; Argument with range
https://alive2.llvm.org/ce/z/YgDy8C ; Instruction with known bits
https://alive2.llvm.org/ce/z/6pIxR6 ; Constant

`lshr`:
https://alive2.llvm.org/ce/z/WCCBej

`ashr:
https://alive2.llvm.org/ce/z/egV4TR

---------

Co-authored-by: Ryan Buchner <rbuchner at ventanamicro.com>
Co-authored-by: Yingwei Zheng <dtcxzyw at qq.com>



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