[all-commits] [llvm/llvm-project] 18624a: [mlir][SliceAnalysis] Fix stack overflow in graph ...

[Krzysztof Parzyszek via All-commits]

  Branch: refs/heads/release/21.x
  Home:   https://github.com/llvm/llvm-project
  Commit: 18624ae54bc979e47ad990721eb20eb9ca982a2f
      https://github.com/llvm/llvm-project/commit/18624ae54bc979e47ad990721eb20eb9ca982a2f
  Author: Martin Erhart <martin.erhart at sifive.com>
  Date:   2025-07-16 (Wed, 16 Jul 2025)

  Changed paths:
    M mlir/include/mlir/Analysis/SliceAnalysis.h
    M mlir/lib/Analysis/SliceAnalysis.cpp
    M mlir/test/Dialect/Affine/slicing-utils.mlir

  Log Message:
  -----------
  [mlir][SliceAnalysis] Fix stack overflow in graph regions (#139694)

This analysis currently just crashes when applied to a graph region that
has a use-def cycle. This PR fixes that by keeping track of the
operations the DFS has already visited when following use-def edges and
stopping once we visit an operation again.


  Commit: 588b8130794f7ce53fe30237f6bf5614b7122f45
      https://github.com/llvm/llvm-project/commit/588b8130794f7ce53fe30237f6bf5614b7122f45
  Author: Sander de Smalen <sander.desmalen at arm.com>
  Date:   2025-07-16 (Wed, 16 Jul 2025)

  Changed paths:
    M llvm/lib/Target/AArch64/AArch64ExpandPseudoInsts.cpp
    M llvm/lib/Target/AArch64/AArch64InstrInfo.cpp
    M llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
    M llvm/test/CodeGen/AArch64/spillfill-sve.mir

  Log Message:
  -----------
  [AArch64] Use correct regclass for spills of ZPR2/ZPR4 (#148806)

Commit a6293228fdd5aba8c04c63f02f3d017443feb3f2 forced the register
class of ZPR[24]StridedOrContiguous for spills/fills of ZPR2 and ZPR4,
but this may result in issues when the regclass for the fill is a
ZPR2/ZPR4 which would allow the register allocator to pick `z1_z2`,
which is not a supported register for ZPR2StridedOrContiguous that only
supports tuples of the form (strided) `z0_z8`, `z1_z9` or (contiguous,
start at multiple of 2) `z0_z1`, `z2_z3`. For spills we could add a new
register class that supports any of the tuple forms, but I've decided
to use two pseudos similar to the fills for consistency.

Fixes https://github.com/llvm/llvm-project/issues/148655


  Commit: d1517ec62222584304951fcf63ce35d8fd0942f2
      https://github.com/llvm/llvm-project/commit/d1517ec62222584304951fcf63ce35d8fd0942f2
  Author: Sander de Smalen <sander.desmalen at arm.com>
  Date:   2025-07-16 (Wed, 16 Jul 2025)

  Changed paths:
    M llvm/lib/Target/AArch64/AArch64ExpandPseudoInsts.cpp
    M llvm/test/CodeGen/AArch64/sve-pseudos-expand-undef.mir

  Log Message:
  -----------
  [AArch64] Ensure bundle expansion of MOVPRFX gets correct implicit ops (#148824)

By finalizing the bundle _after_ copying over the implicit-ops, it also
adds any implicit-defs to the BUNDLE.

Fixes https://github.com/llvm/llvm-project/issues/148645


  Commit: 7d803c868ab96dabbd4cb47d0b3e60a78057e1b0
      https://github.com/llvm/llvm-project/commit/7d803c868ab96dabbd4cb47d0b3e60a78057e1b0
  Author: Sjoerd Meijer <smeijer at nvidia.com>
  Date:   2025-07-16 (Wed, 16 Jul 2025)

  Changed paths:
    M llvm/lib/Target/AArch64/AArch64Subtarget.cpp

  Log Message:
  -----------
  [AArch64] Set the cache line size to 64 for the V2 and V3. (#148213)

This sets the cache line size to 64 for the Neoverse V2 and V3. I've
tested this with loop-interchange: it doesn't result in extra
compile-times, but it does enable a lot more interchange.


  Commit: a0895b4581bac8634596263b42d49c7f2e2d957f
      https://github.com/llvm/llvm-project/commit/a0895b4581bac8634596263b42d49c7f2e2d957f
  Author: Krzysztof Parzyszek <Krzysztof.Parzyszek at amd.com>
  Date:   2025-07-16 (Wed, 16 Jul 2025)

  Changed paths:
    M llvm/include/llvm/Frontend/OpenMP/ConstructDecompositionT.h
    M llvm/include/llvm/Frontend/OpenMP/OMP.h

  Log Message:
  -----------
  [Frontend][OpenMP] Move isPrivatizingClause to OMP.h, NFC (#148644)


Compare: https://github.com/llvm/llvm-project/compare/6296ebd45d3f...a0895b4581ba

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