[all-commits] [llvm/llvm-project] 6260d8: [C++] Fix a failed assertion with nullability chec...
Fangrui Song via All-commits
all-commits at lists.llvm.org
Tue Jul 15 21:46:20 PDT 2025
Branch: refs/heads/users/MaskRay/spr/mc-restructure-mcfragment-as-a-fixed-part-and-a-variable-tail
Home: https://github.com/llvm/llvm-project
Commit: 6260d8ff8277d35ff783ba7c6febb1489eb94b24
https://github.com/llvm/llvm-project/commit/6260d8ff8277d35ff783ba7c6febb1489eb94b24
Author: Aaron Ballman <aaron at aaronballman.com>
Date: 2025-07-15 (Tue, 15 Jul 2025)
Changed paths:
M clang/docs/ReleaseNotes.rst
M clang/lib/Sema/TreeTransform.h
A clang/test/SemaTemplate/gh138371.cpp
Log Message:
-----------
[C++] Fix a failed assertion with nullability checking (#148881)
This fixes a failed assertion with an operator call expression which
comes from a macro expansion when performing analysis for nullability
attributes.
Fixes #138371
Commit: 0967957d7a94e1b5c749c6e963bdca25f3c6d749
https://github.com/llvm/llvm-project/commit/0967957d7a94e1b5c749c6e963bdca25f3c6d749
Author: David Green <david.green at arm.com>
Date: 2025-07-15 (Tue, 15 Jul 2025)
Changed paths:
M llvm/include/llvm/CodeGen/BasicTTIImpl.h
M llvm/test/Analysis/CostModel/AArch64/arith-overflow.ll
M llvm/test/Analysis/CostModel/AArch64/cmp.ll
M llvm/test/Analysis/CostModel/AArch64/fcmp.ll
M llvm/test/Analysis/CostModel/AArch64/fshl.ll
M llvm/test/Analysis/CostModel/AArch64/fshr.ll
M llvm/test/Analysis/CostModel/AArch64/sve-cmpsel.ll
M llvm/test/Analysis/CostModel/AArch64/sve-fcmp.ll
M llvm/test/Analysis/CostModel/AArch64/sve-intrinsics.ll
M llvm/test/Analysis/CostModel/AArch64/vector-select.ll
M llvm/test/Analysis/CostModel/AMDGPU/reduce-and.ll
M llvm/test/Analysis/CostModel/AMDGPU/reduce-or.ll
M llvm/test/Analysis/CostModel/ARM/arith-overflow.ll
M llvm/test/Analysis/CostModel/ARM/arith-ssat.ll
M llvm/test/Analysis/CostModel/ARM/arith-usat.ll
M llvm/test/Analysis/CostModel/ARM/cmps.ll
M llvm/test/Analysis/CostModel/ARM/intrinsic-cost-kinds.ll
M llvm/test/Analysis/CostModel/ARM/mve-abs.ll
M llvm/test/Analysis/CostModel/ARM/mve-minmax.ll
M llvm/test/Analysis/CostModel/ARM/select.ll
M llvm/test/CodeGen/Thumb2/mve-pred-vselect.ll
M llvm/test/CodeGen/X86/div-rem-pair-recomposition-unsigned.ll
M llvm/test/CodeGen/X86/test-shrink-bug.ll
M llvm/test/Transforms/SimplifyCFG/ARM/phi-eliminate.ll
Log Message:
-----------
[CostModel] Handle all cost kinds in getCmpSelInstrCost (#148233)
Currently we always produce a cost of 1 for all CostKinds that are not
RecipThroughput, which can underestimate the cost if the type has a
higher legalization cost (like larger vectors). This relaxes it to cover
all cost kinds.
Commit: 0d2e11f3e834e0c1803a6e00da35525b0d476eb2
https://github.com/llvm/llvm-project/commit/0d2e11f3e834e0c1803a6e00da35525b0d476eb2
Author: Brad Smith <brad at comstyle.com>
Date: 2025-07-15 (Tue, 15 Jul 2025)
Changed paths:
M clang/include/clang/Basic/TargetInfo.h
M clang/lib/AST/ASTContext.cpp
M clang/lib/Basic/CMakeLists.txt
M clang/lib/Basic/Targets.cpp
M clang/lib/Basic/Targets/ARM.cpp
M clang/lib/Basic/Targets/OSTargets.h
R clang/lib/Basic/Targets/PNaCl.cpp
R clang/lib/Basic/Targets/PNaCl.h
M clang/lib/CodeGen/CMakeLists.txt
M clang/lib/CodeGen/CodeGenModule.cpp
M clang/lib/CodeGen/TargetInfo.h
R clang/lib/CodeGen/Targets/PNaCl.cpp
M clang/lib/CodeGen/Targets/X86.cpp
M clang/lib/Driver/CMakeLists.txt
M clang/lib/Driver/Driver.cpp
R clang/lib/Driver/ToolChains/NaCl.cpp
R clang/lib/Driver/ToolChains/NaCl.h
M clang/lib/Lex/InitHeaderSearch.cpp
R clang/test/CodeGen/X86/x86_64-arguments-nacl.c
M clang/test/CodeGen/X86/x86_64-longdouble.c
M clang/test/CodeGen/arm-aapcs-vfp.c
M clang/test/CodeGen/ext-int-cc.c
M clang/test/CodeGen/long_double_fp128.cpp
R clang/test/CodeGen/malign-double-x86-nacl.c
M clang/test/CodeGen/target-data.c
R clang/test/CodeGenCXX/x86_64-arguments-nacl-x32.cpp
M clang/test/Driver/arm-alignment.c
R clang/test/Driver/nacl-direct.c
M clang/test/Driver/unsupported-target-arch.c
R clang/test/Driver/x86_64-nacl-defines.cpp
R clang/test/Frontend/x86_64-nacl-types.cpp
M clang/test/Preprocessor/predefined-macros-no-warnings.c
M llvm/include/llvm/BinaryFormat/ELF.h
M llvm/include/llvm/BinaryFormat/MinidumpConstants.def
M llvm/include/llvm/CodeGen/AtomicExpandUtils.h
M llvm/include/llvm/TargetParser/Triple.h
M llvm/lib/Target/ARM/ARMAsmPrinter.cpp
M llvm/lib/Target/ARM/ARMFastISel.cpp
M llvm/lib/Target/ARM/ARMFeatures.td
M llvm/lib/Target/ARM/ARMFrameLowering.cpp
M llvm/lib/Target/ARM/ARMISelLowering.cpp
M llvm/lib/Target/ARM/ARMInstrInfo.td
M llvm/lib/Target/ARM/ARMPredicates.td
M llvm/lib/Target/ARM/ARMSubtarget.cpp
M llvm/lib/Target/ARM/ARMSubtarget.h
M llvm/lib/Target/ARM/ARMTargetMachine.cpp
M llvm/lib/Target/ARM/ARMTargetTransformInfo.h
M llvm/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.cpp
M llvm/lib/Target/Mips/MCTargetDesc/CMakeLists.txt
R llvm/lib/Target/Mips/MCTargetDesc/MipsMCNaCl.h
M llvm/lib/Target/Mips/MCTargetDesc/MipsMCTargetDesc.cpp
R llvm/lib/Target/Mips/MCTargetDesc/MipsNaClELFStreamer.cpp
M llvm/lib/Target/Mips/MipsAsmPrinter.cpp
M llvm/lib/Target/Mips/MipsAsmPrinter.h
M llvm/lib/Target/Mips/MipsBranchExpansion.cpp
M llvm/lib/Target/Mips/MipsCallingConv.td
M llvm/lib/Target/Mips/MipsDelaySlotFiller.cpp
M llvm/lib/Target/Mips/MipsInstrFPU.td
M llvm/lib/Target/Mips/MipsInstrInfo.td
M llvm/lib/Target/Mips/MipsRegisterInfo.cpp
M llvm/lib/Target/Mips/MipsSubtarget.h
M llvm/lib/Target/X86/X86ExpandPseudo.cpp
M llvm/lib/Target/X86/X86FrameLowering.cpp
M llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
M llvm/lib/Target/X86/X86ISelLowering.cpp
M llvm/lib/Target/X86/X86InstrPredicates.td
M llvm/lib/Target/X86/X86Subtarget.cpp
M llvm/lib/Target/X86/X86Subtarget.h
M llvm/lib/Target/X86/X86TargetMachine.cpp
M llvm/lib/TargetParser/ARMTargetParser.cpp
M llvm/lib/TargetParser/Triple.cpp
M llvm/test/CodeGen/ARM/fast-isel-align.ll
M llvm/test/CodeGen/ARM/struct_byval.ll
M llvm/test/CodeGen/ARM/trap.ll
R llvm/test/CodeGen/ARM/varargs-spill-stack-align-nacl.ll
M llvm/test/CodeGen/Mips/fastcc.ll
M llvm/test/CodeGen/Mips/fp-indexed-ls.ll
M llvm/test/CodeGen/Mips/indirect-jump-hazard/long-branch.ll
M llvm/test/CodeGen/Mips/longbranch.ll
R llvm/test/CodeGen/Mips/nacl-align.ll
R llvm/test/CodeGen/Mips/nacl-branch-delay.ll
R llvm/test/CodeGen/Mips/nacl-reserved-regs.ll
M llvm/test/CodeGen/Thumb2/pacbti-m-outliner-1.ll
M llvm/test/CodeGen/X86/constructor.ll
M llvm/test/CodeGen/X86/fast-isel-x32.ll
M llvm/test/CodeGen/X86/frameaddr.ll
M llvm/test/CodeGen/X86/lea-2.ll
M llvm/test/CodeGen/X86/lea-3.ll
M llvm/test/CodeGen/X86/lea-4.ll
M llvm/test/CodeGen/X86/lea-5.ll
M llvm/test/CodeGen/X86/lea.ll
M llvm/test/CodeGen/X86/stack-align2.ll
M llvm/test/CodeGen/X86/x86-64-baseptr.ll
M llvm/test/CodeGen/X86/x86-64-stack-and-frame-ptr.ll
M llvm/test/MC/ARM/arm_instructions.s
R llvm/test/MC/Mips/nacl-mask.s
M llvm/test/MC/X86/AlignedBundling/labeloffset.s
R llvm/test/MC/X86/AlignedBundling/rodata-section.s
M llvm/unittests/TargetParser/TargetParserTest.cpp
Log Message:
-----------
Remove Native Client support (#133661)
Remove the Native Client support now that it has finally reached end of life.
Commit: 66850d0c06eef6d46b330af57bb675330b15b2cc
https://github.com/llvm/llvm-project/commit/66850d0c06eef6d46b330af57bb675330b15b2cc
Author: Thurston Dang <thurston at google.com>
Date: 2025-07-15 (Tue, 15 Jul 2025)
Changed paths:
M llvm/lib/Transforms/Instrumentation/MemorySanitizer.cpp
M llvm/test/Instrumentation/MemorySanitizer/X86/avx-intrinsics-x86.ll
M llvm/test/Instrumentation/MemorySanitizer/X86/avx512-intrinsics-upgrade.ll
M llvm/test/Instrumentation/MemorySanitizer/X86/avx512-intrinsics.ll
M llvm/test/Instrumentation/MemorySanitizer/X86/avx512bw-intrinsics-upgrade.ll
M llvm/test/Instrumentation/MemorySanitizer/X86/avx512bw-intrinsics.ll
M llvm/test/Instrumentation/MemorySanitizer/X86/avx512vl-intrinsics.ll
M llvm/test/Instrumentation/MemorySanitizer/X86/x86-vpermi2.ll
M llvm/test/Instrumentation/MemorySanitizer/i386/avx-intrinsics-i386.ll
Log Message:
-----------
[msan] Fix 'Simplify 'maskedCheckAVXIndexShadow' #147839' (#148785)
https://github.com/llvm/llvm-project/pull/147839/ incorrectly checked
the (lower bits of the) concrete value rather than the shadow.
Commit: 09f7cab9a34ed0837375f1677a4322d40b37ed5f
https://github.com/llvm/llvm-project/commit/09f7cab9a34ed0837375f1677a4322d40b37ed5f
Author: Deric C. <cheung.deric at gmail.com>
Date: 2025-07-15 (Tue, 15 Jul 2025)
Changed paths:
M llvm/lib/Target/DirectX/DXILLegalizePass.cpp
M llvm/test/CodeGen/DirectX/legalize-i8.ll
A llvm/test/CodeGen/DirectX/legalize-load-store-array-alloca.ll
Log Message:
-----------
[DirectX] Add a GEP to loads and stores on array allocas (#148059)
Fixes #147114 by inserting a GEP between any direct loads and stores on
an alloca.
Commit: d9e21a92a7b1b68bc61771c4a9320f879850ea90
https://github.com/llvm/llvm-project/commit/d9e21a92a7b1b68bc61771c4a9320f879850ea90
Author: RolandF77 <55763885+RolandF77 at users.noreply.github.com>
Date: 2025-07-15 (Tue, 15 Jul 2025)
Changed paths:
M clang/include/clang/Basic/BuiltinsPPC.def
M clang/lib/CodeGen/TargetBuiltins/PPC.cpp
M clang/test/CodeGen/PowerPC/builtins-ppc-dmf.c
A clang/test/CodeGen/PowerPC/ppc-dmf-future-builtin-err.c
A clang/test/CodeGen/PowerPC/ppc-dmf-mma-builtin-err.c
R clang/test/CodeGen/PowerPC/ppc-future-mma-builtin-err.c
Log Message:
-----------
[PowerPC] Add DMF basic builtins (#145372)
Add support for PPC Dense Math basic builtins dmsetdmrz, dmmr, dmxor.
Commit: 63d099af146a19bc8fd5a791d6184125e6cc42e7
https://github.com/llvm/llvm-project/commit/63d099af146a19bc8fd5a791d6184125e6cc42e7
Author: Craig Topper <craig.topper at sifive.com>
Date: 2025-07-15 (Tue, 15 Jul 2025)
Changed paths:
M llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
Log Message:
-----------
[RISCV] Remove incorrect and untested FrameIndex support from SelectAddrRegImm9. (#148779)
To fold a FrameIndex, we need to teach eliminateFrameIndex to respect
the uimm9 range.
Commit: c3dde3cf843656a08fced1702e09d8b80d2f6829
https://github.com/llvm/llvm-project/commit/c3dde3cf843656a08fced1702e09d8b80d2f6829
Author: Jordan Rupprecht <rupprecht at google.com>
Date: 2025-07-15 (Tue, 15 Jul 2025)
Changed paths:
M utils/bazel/llvm-project-overlay/libc/BUILD.bazel
M utils/bazel/llvm-project-overlay/libc/test/src/math/BUILD.bazel
M utils/bazel/llvm-project-overlay/libc/test/src/math/smoke/BUILD.bazel
Log Message:
-----------
[bazel] Add tanpif rules after #147192 (#148909)
Commit: fad0fbc9371c6a3289e6dc8a5018cc00733be14f
https://github.com/llvm/llvm-project/commit/fad0fbc9371c6a3289e6dc8a5018cc00733be14f
Author: S. VenkataKeerthy <31350914+svkeerthy at users.noreply.github.com>
Date: 2025-07-15 (Tue, 15 Jul 2025)
Changed paths:
M llvm/lib/Analysis/IR2Vec.cpp
Log Message:
-----------
[NFC][IR2Vec] Fix warnings on MSVC compilation (#148911)
Commit: bcd0a7ae2a3ae81545190a0b2796eb63656b5d42
https://github.com/llvm/llvm-project/commit/bcd0a7ae2a3ae81545190a0b2796eb63656b5d42
Author: jimingham <jingham at apple.com>
Date: 2025-07-15 (Tue, 15 Jul 2025)
Changed paths:
M lldb/include/lldb/Utility/Listener.h
M lldb/source/Utility/Broadcaster.cpp
M lldb/source/Utility/Listener.cpp
M lldb/unittests/Utility/ListenerTest.cpp
Log Message:
-----------
Revert "[lldb] Fix race condition in Process::WaitForProcessToStop() … (#148915)
…(#144919)"
This was causing a couple of failures on the Ubuntu bots. Reverting
while we wait on a fix for those issues.
This reverts commit 8612926c306c5191a5fb385dd11467728c59e982.
Commit: bc2004c2e42f633ee4099ea5652df41dba29c79c
https://github.com/llvm/llvm-project/commit/bc2004c2e42f633ee4099ea5652df41dba29c79c
Author: Luke Lau <luke at igalia.com>
Date: 2025-07-16 (Wed, 16 Jul 2025)
Changed paths:
M llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vsadd-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vsaddu-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vssub-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vssubu-vp.ll
Log Message:
-----------
[RISCV] Handle LHS == 0 in isVLKnownLE (#148860)
If a VL is zero then it's known to be less than or equal to every other
VL.
This looks weird on its own since a VL of zero isn't that common. The
test diffs come from a type being split resulting in a VP intrinsic's
EVL being zero.
The motivation for this is to split off part of an upcoming patch I plan
on submitting for RISCVVLOptimizer, which generalizes it to handle
recurrences, and needs to reason about an initial state of demanded VLs
set to zero.
Commit: c9f03b8c6ece968a6a413f5ea3a33e23f0aed5ef
https://github.com/llvm/llvm-project/commit/c9f03b8c6ece968a6a413f5ea3a33e23f0aed5ef
Author: Nico Weber <thakis at chromium.org>
Date: 2025-07-15 (Tue, 15 Jul 2025)
Changed paths:
M llvm/utils/gn/secondary/libcxx/include/BUILD.gn
Log Message:
-----------
[gn] port 5951c44573
Commit: 183f1ac412c1a0c69c7dc6aef85c28c0749609cb
https://github.com/llvm/llvm-project/commit/183f1ac412c1a0c69c7dc6aef85c28c0749609cb
Author: Rahul Joshi <rjoshi at nvidia.com>
Date: 2025-07-15 (Tue, 15 Jul 2025)
Changed paths:
M llvm/include/llvm/ADT/StringTable.h
M llvm/lib/IR/Intrinsics.cpp
M llvm/unittests/IR/IntrinsicsTest.cpp
Log Message:
-----------
[LLVM] Fix an ASAN error in `lookupLLVMIntrinsicByName` (#147444)
Fix unnecessary conversion of C-String to StringRef in the `Cmp` lambda
inside `lookupLLVMIntrinsicByName`. This both fixes an ASAN error in the
code that happens when the `Name` StringRef passed in is not a Null
terminated StringRef, and additionally can potentially speed up the code
as well by eliminating the unnecessary computation of string length
every time a C String is converted to StringRef in this code (It seems
practically this computation is eliminated in optimized builds, but this
will avoid it in O0 builds as well).
Added a unit test that demonstrates this issue by building LLVM with
these options:
```
CMAKE_BUILD_TYPE=Debug
LLVM_USE_SANITIZER=Address
LLVM_OPTIMIZE_SANITIZED_BUILDS=OFF
```
The error reported is as follows:
```
==462665==ERROR: AddressSanitizer: heap-buffer-overflow on address 0x5030000391a2 at pc 0x56525cc30bbf bp 0x7fff9e4ccc60 sp 0x7fff9e4cc428
READ of size 19 at 0x5030000391a2 thread T0
#0 0x56525cc30bbe in strlen (upstream-llvm-second/llvm-project/build/unittests/IR/IRTests+0x713bbe) (BuildId: 0651acf1e582a4d2)
#1 0x7f8ff22ad334 in std::char_traits<char>::length(char const*) /usr/bin/../lib/gcc/x86_64-linux-gnu/13/../../../../include/c++/13/bits/char_traits.h:399:9
#2 0x7f8ff22a34a0 in llvm::StringRef::StringRef(char const*) /home/rjoshi/upstream-llvm-second/llvm-project/llvm/include/llvm/ADT/StringRef.h:96:33
#3 0x7f8ff28ca184 in _ZZL25lookupLLVMIntrinsicByNameN4llvm8ArrayRefIjEENS_9StringRefES2_ENK3$_0clIjPKcEEDaT_T0_ upstream-llvm-second/llvm-project/llvm/lib/IR/Intrinsics.cpp:673:18
```
Commit: 041a8a9e5a00358491fb98e4f6156f0882bf5bea
https://github.com/llvm/llvm-project/commit/041a8a9e5a00358491fb98e4f6156f0882bf5bea
Author: Remy Farley <one-d-wide at protonmail.com>
Date: 2025-07-15 (Tue, 15 Jul 2025)
Changed paths:
M clang-tools-extra/docs/ReleaseNotes.rst
A clang-tools-extra/test/clang-query/trailing-comma.c
M clang/lib/ASTMatchers/Dynamic/Parser.cpp
Log Message:
-----------
[clang-query] Allow for trailing comma in matchers (#148018)
Allow AST matches in clang-query to have a trailing comma at the end of
matcher arguments. Makes it nicer to work with queries that span
multiple lines.
So, for example, the following is possible:
```clang-query
match namedDecl(
isExpansionInMainFile(),
anyOf(
varDecl().bind("var"),
functionDecl().bind("func"),
# enumDecl().bind("enum"),
),
)
```
Commit: edfec9c5829f4778bd38f3ca4019105eb481df49
https://github.com/llvm/llvm-project/commit/edfec9c5829f4778bd38f3ca4019105eb481df49
Author: bd1976bris <Ben.Dunbobbin at sony.com>
Date: 2025-07-15 (Tue, 15 Jul 2025)
Changed paths:
M clang/test/Driver/DTLTO/dtlto.c
Log Message:
-----------
[DTLTO][TEST] Fix Clang driver test failing on some build bots (#148908)
Not all builds name the compiler executable `clang`. For example, the
Fuchsia build bots use `llvm` as their single toolchain executable name,
as they combine everything together in a busybot-style binary.
Update the Clang driver test to simply check that a non-empty path is
provided for the `--thinlto-remote-compiler` argument, rather than
hardcoding the executable name. The cross-project test will verify that
the path is valid later.
Should fix #147265.
Commit: 339711fbd07bb2deb092800a5af20daa85e589af
https://github.com/llvm/llvm-project/commit/339711fbd07bb2deb092800a5af20daa85e589af
Author: Thurston Dang <thurston at google.com>
Date: 2025-07-15 (Tue, 15 Jul 2025)
Changed paths:
M llvm/docs/HowToSubmitABug.rst
Log Message:
-----------
[docs] Linkify llvm-reduce and mention it is multi-threaded (#148904)
Commit: a9021e5373f814a7bce561147828dcb7ec2abb24
https://github.com/llvm/llvm-project/commit/a9021e5373f814a7bce561147828dcb7ec2abb24
Author: Deric C. <cheung.deric at gmail.com>
Date: 2025-07-15 (Tue, 15 Jul 2025)
Changed paths:
M llvm/lib/Target/DirectX/DXILLegalizePass.cpp
M llvm/test/CodeGen/DirectX/legalize-memcpy.ll
M llvm/test/CodeGen/DirectX/legalize-memset.ll
Log Message:
-----------
Emit array GEPs in memcpy/memset legalization (#148886)
Fixes #148089
Commit: 95fa67603c4ab5d75a2f8df328d7da5580466d50
https://github.com/llvm/llvm-project/commit/95fa67603c4ab5d75a2f8df328d7da5580466d50
Author: nerix <nerixdev at outlook.de>
Date: 2025-07-15 (Tue, 15 Jul 2025)
Changed paths:
M lldb/packages/Python/lldbsuite/test/make/Makefile.rules
M lldb/test/API/functionalities/data-formatter/data-formatter-advanced/main.cpp
Log Message:
-----------
[LLDB] Compile API tests with exceptions enabled on Windows (#148691)
>From #148554 - compile tests with exceptions on Windows
(`-fno-exceptions` was added 11 years ago in
c7826524acda6a9c8816261d5c48b94dc92935ed). The variant test uses `try {}
catch {}` to create variants that are valueless by exception. On other
platforms, exceptions are enabled as well.
I have no clue why compiling with exceptions will optimize out
`a_long_guy` in the changed test (even with `-O0`). Taking the address
of that value will ensure it's kept.
Commit: efa94cf703a510083f411444650f3a8d21dfcfee
https://github.com/llvm/llvm-project/commit/efa94cf703a510083f411444650f3a8d21dfcfee
Author: Dmitry Vasilyev <dvassiliev at accesssoftek.com>
Date: 2025-07-15 (Tue, 15 Jul 2025)
Changed paths:
M llvm/lib/Support/rpmalloc/rpmalloc.c
Log Message:
-----------
[Support/rpmalloc] Updated fake atomics with Interlocked functions (#148303)
Most atomic functions used Interlocked functions in case of MSVC (since MSVC does not do C11 yet).
But few load/store functions are dummy.
Use Interlocked functions for these atomics to ensure they are thread-safe.
This PR fixes #146205.
LLVM is on VS 2019 version 16.7 currently and eventually we require VS 2022 if we wanted to use stdatomics in rpmalloc, etc. In the meanwhile, we use the Interlocked intrinsics when building with MSVC.
Commit: 28463928a9c355d6b5f8cd0e551235dda76acb14
https://github.com/llvm/llvm-project/commit/28463928a9c355d6b5f8cd0e551235dda76acb14
Author: LLVM GN Syncbot <llvmgnsyncbot at gmail.com>
Date: 2025-07-15 (Tue, 15 Jul 2025)
Changed paths:
M llvm/utils/gn/secondary/clang/lib/Basic/BUILD.gn
M llvm/utils/gn/secondary/clang/lib/CodeGen/BUILD.gn
M llvm/utils/gn/secondary/clang/lib/Driver/BUILD.gn
M llvm/utils/gn/secondary/llvm/lib/Target/Mips/MCTargetDesc/BUILD.gn
Log Message:
-----------
[gn build] Port 0d2e11f3e834
Commit: d64a236445d48ff55efb2278216e429bca746054
https://github.com/llvm/llvm-project/commit/d64a236445d48ff55efb2278216e429bca746054
Author: LLVM GN Syncbot <llvmgnsyncbot at gmail.com>
Date: 2025-07-15 (Tue, 15 Jul 2025)
Changed paths:
M llvm/utils/gn/secondary/llvm/unittests/BinaryFormat/BUILD.gn
Log Message:
-----------
[gn build] Port ee9b84f5bed7
Commit: 8917f84d293c2fa6b77536d7053b5c41f4e785b8
https://github.com/llvm/llvm-project/commit/8917f84d293c2fa6b77536d7053b5c41f4e785b8
Author: LLVM GN Syncbot <llvmgnsyncbot at gmail.com>
Date: 2025-07-15 (Tue, 15 Jul 2025)
Changed paths:
M llvm/utils/gn/secondary/lldb/source/Plugins/Language/CPlusPlus/BUILD.gn
Log Message:
-----------
[gn build] Port eec98bef84b8
Commit: d67d91a9906366585162cebf292f923a3f28c8a6
https://github.com/llvm/llvm-project/commit/d67d91a9906366585162cebf292f923a3f28c8a6
Author: Sudharsan Veeravalli <quic_svs at quicinc.com>
Date: 2025-07-15 (Tue, 15 Jul 2025)
Changed paths:
M llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
M llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td
M llvm/test/CodeGen/RISCV/xqcibm-cto-clo-brev.ll
M llvm/test/CodeGen/RISCV/xqcibm-insert.ll
Log Message:
-----------
[RISCV] Fix issues in ORI to QC.INSBI transformation (#148809)
The transformation done in #147349 was incorrect since we were not
passing the input node of the `OR` instruction to the `QC.INSBI`
instruction leading to the generated instruction doing the wrong thing.
In order to do this we first needed to add the output register to
`QC.INSBI` as being both an input and output.
The code produced after the above fix will need a copy (mv) to preserve
the register input to the OR instruction if it has more than one use
making the transformation net neutral ( `6-byte QC.E.ORI/ORAI` vs
`2-byte C.MV + 4-byte QC.INSB`I). Avoid doing the transformation if
there is more than one use of the input register to the OR instruction.
Commit: fccae859bc949ba390184614e07234267a734b86
https://github.com/llvm/llvm-project/commit/fccae859bc949ba390184614e07234267a734b86
Author: David Peixotto <peix at meta.com>
Date: 2025-07-15 (Tue, 15 Jul 2025)
Changed paths:
M lldb/include/lldb/Core/PluginManager.h
M lldb/include/lldb/Interpreter/CommandCompletions.h
M lldb/include/lldb/lldb-enumerations.h
M lldb/packages/Python/lldbsuite/test/lldbtest.py
M lldb/source/Commands/CommandCompletions.cpp
M lldb/source/Commands/CommandObjectPlugin.cpp
M lldb/source/Core/PluginManager.cpp
M lldb/test/API/commands/plugin/TestPlugin.py
Log Message:
-----------
[lldb] Add completions for plugin list/enable/disable (#147775)
This commit adds completion support for the plugin commands. It will try
to complete partial namespaces to the full namespace string. If the
completion input is already a full namespace string then it will add all
the matching plugins in that namespace as completions.
This lets the user complete to the namespace first and then tab-complete
to the next level if desired.
```
(lldb) plugin list a<tab>
Available completions:
abi
architecture
(lldb) plugin list ab<tab>
(lldb) plugin list abi<tab>
(lldb) plugin list abi.<tab>
Available completions:
abi.SysV-arm64
abi.ABIMacOSX_arm64
abi.SysV-arm
...
```
Commit: c592b61fc82c79366216ae12b25b0130359b0a26
https://github.com/llvm/llvm-project/commit/c592b61fc82c79366216ae12b25b0130359b0a26
Author: Jan Svoboda <jan_svoboda at apple.com>
Date: 2025-07-15 (Tue, 15 Jul 2025)
Changed paths:
M clang-tools-extra/clangd/ModulesBuilder.cpp
M clang/include/clang/Basic/CodeGenOptions.def
M clang/include/clang/Basic/CodeGenOptions.h
M clang/include/clang/Basic/DebugOptions.def
M clang/include/clang/Basic/DiagnosticSerializationKinds.td
M clang/include/clang/Basic/LangOptions.def
M clang/include/clang/Frontend/ASTUnit.h
M clang/include/clang/Frontend/CompilerInstance.h
M clang/include/clang/Serialization/ASTBitCodes.h
M clang/include/clang/Serialization/ASTReader.h
M clang/include/clang/Serialization/ASTWriter.h
M clang/lib/Basic/CodeGenOptions.cpp
M clang/lib/CodeGen/CGDebugInfo.cpp
M clang/lib/CodeGen/CGOpenMPRuntime.cpp
M clang/lib/CodeGen/CodeGenAction.cpp
M clang/lib/Frontend/ASTUnit.cpp
M clang/lib/Frontend/ChainedIncludesSource.cpp
M clang/lib/Frontend/CompilerInstance.cpp
M clang/lib/Frontend/CompilerInvocation.cpp
M clang/lib/Frontend/FrontendAction.cpp
M clang/lib/Frontend/FrontendActions.cpp
M clang/lib/Frontend/InitPreprocessor.cpp
M clang/lib/Frontend/PrecompiledPreamble.cpp
M clang/lib/Serialization/ASTReader.cpp
M clang/lib/Serialization/ASTWriter.cpp
M clang/lib/Serialization/GeneratePCH.cpp
M clang/test/PCH/no-validate-pch.cl
M lldb/source/Plugins/TypeSystem/Clang/TypeSystemClang.cpp
A llvm/clang/test/Modules/implicit-opt-level.c
Log Message:
-----------
[clang][modules] Serialize `CodeGenOptions` (#146422)
Some `LangOptions` duplicate their `CodeGenOptions` counterparts. My
understanding is that this was done solely because some infrastructure
(like preprocessor initialization, serialization, module compatibility
checks, etc.) were only possible/convenient for `LangOptions`. This PR
implements the missing support for `CodeGenOptions`, which makes it
possible to remove some duplicate `LangOptions` fields and simplify the
logic. Motivated by https://github.com/llvm/llvm-project/pull/146342.
Commit: 52432b02a9bdc234d1038ed2e72afe28779ca031
https://github.com/llvm/llvm-project/commit/52432b02a9bdc234d1038ed2e72afe28779ca031
Author: David Pagan <dave.pagan at amd.com>
Date: 2025-07-15 (Tue, 15 Jul 2025)
Changed paths:
M clang/lib/Basic/OpenMPKinds.cpp
Log Message:
-----------
[clang][NFC] Updated incorrect llvm-unreachable message in getOpenMPSimpleClauseType() (#148056)
Commit: 70e1a3ceada92c200e575e4fdcc1f27022b3c8f2
https://github.com/llvm/llvm-project/commit/70e1a3ceada92c200e575e4fdcc1f27022b3c8f2
Author: Paul Trojahn <paul.trojahn at gmail.com>
Date: 2025-07-15 (Tue, 15 Jul 2025)
Changed paths:
M llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
A llvm/test/CodeGen/AMDGPU/fold-commute-sgpr.mir
Log Message:
-----------
[AMDGPU] Check legality of both operands before swap (#148843)
When trying to fold an SGPR into the second operand to a DPP add,
si-fold-operands correctly determines that this is not possible and
attempts to swap the second and third operand. This succeeds even if the
third operand is an SGPR, creating an illegal dpp add with two SGPR
operands. We need to check both operands if they are legal in their new
position.
This causes a crash at compile time for a test in triton on gfx12:
https://github.com/triton-lang/triton/blob/345c633787e90a7f94864de3035346eb5de1781f/python/test/unit/language/test_core.py#L2718
Co-authored-by: Paul Trojahn <paul.trojahn at amd.com>
Commit: ad1cbc020493b39266f7b259737bf5c7ad0a3d56
https://github.com/llvm/llvm-project/commit/ad1cbc020493b39266f7b259737bf5c7ad0a3d56
Author: Jan Svoboda <jan_svoboda at apple.com>
Date: 2025-07-15 (Tue, 15 Jul 2025)
Changed paths:
M clang/include/clang/Basic/CodeGenOptions.h
Log Message:
-----------
[clang] Attempt to fix build after c592b61f
Commit: e5bc7e7df3adf1777194ccd4ffa4e69f39b811f0
https://github.com/llvm/llvm-project/commit/e5bc7e7df3adf1777194ccd4ffa4e69f39b811f0
Author: Philip Reames <preames at rivosinc.com>
Date: 2025-07-15 (Tue, 15 Jul 2025)
Changed paths:
M llvm/lib/Target/RISCV/RISCVInterleavedAccess.cpp
M llvm/test/Transforms/InterleavedAccess/RISCV/addrspace.ll
M llvm/test/Transforms/InterleavedAccess/RISCV/interleaved-accesses.ll
Log Message:
-----------
[RISCV][IA] Always generate masked versions of segment LD/ST [nfc-ish] (#148905)
Goal is to be able to eventually merge some of these code path. Having
the mask operand should get dropped cleanly via pattern match.
Commit: ba95df17ece2f6a137ccf88dd95841889e285953
https://github.com/llvm/llvm-project/commit/ba95df17ece2f6a137ccf88dd95841889e285953
Author: sribee8 <sriya.pratipati at gmail.com>
Date: 2025-07-15 (Tue, 15 Jul 2025)
Changed paths:
M libc/fuzzing/math/CMakeLists.txt
R libc/fuzzing/math/atan_fuzz.cpp
A libc/fuzzing/math/log10_fuzz.cpp
A libc/fuzzing/math/log1p_fuzz.cpp
A libc/fuzzing/math/log2_fuzz.cpp
A libc/fuzzing/math/log_fuzz.cpp
M libc/fuzzing/math/sincos_fuzz.cpp
A libc/fuzzing/math/sqrt_fuzz.cpp
Log Message:
-----------
[libc] sqrt and log functions fuzz tests (#148006)
added fuzz tests for sqrt and log functions
---------
Co-authored-by: Sriya Pratipati <sriyap at google.com>
Commit: 859dcfc17f0098ac52196af584b343f1416c19b0
https://github.com/llvm/llvm-project/commit/859dcfc17f0098ac52196af584b343f1416c19b0
Author: higher-performance <higher.performance.github at gmail.com>
Date: 2025-07-15 (Tue, 15 Jul 2025)
Changed paths:
M clang/docs/ReleaseNotes.rst
M clang/include/clang/AST/Decl.h
M clang/include/clang/ASTMatchers/ASTMatchers.h
M clang/lib/AST/Decl.cpp
M clang/unittests/ASTMatchers/ASTMatchersNarrowingTest.cpp
Log Message:
-----------
Check if clang::FieldDecl has constant-integer bit width before getting the width (#148692)
This avoids crashing due to template-dependent bit widths
Commit: dabc8e2ec1e15a46b7d8aaa9d216d002a2ce8b99
https://github.com/llvm/llvm-project/commit/dabc8e2ec1e15a46b7d8aaa9d216d002a2ce8b99
Author: Shilei Tian <i at tianshilei.me>
Date: 2025-07-15 (Tue, 15 Jul 2025)
Changed paths:
M clang/include/clang/Basic/BuiltinsAMDGPU.def
M clang/lib/CodeGen/TargetBuiltins/AMDGPU.cpp
M clang/test/CodeGenOpenCL/builtins-amdgcn-gfx1250.cl
M llvm/lib/Target/AMDGPU/VOP1Instructions.td
A llvm/test/CodeGen/AMDGPU/llvm.amdgcn.rcp.bf16.ll
M llvm/test/MC/AMDGPU/gfx1250_asm_vop1-fake16.s
M llvm/test/MC/AMDGPU/gfx1250_asm_vop1.s
M llvm/test/MC/AMDGPU/gfx1250_asm_vop1_dpp16-fake16.s
M llvm/test/MC/AMDGPU/gfx1250_asm_vop1_dpp16.s
M llvm/test/MC/AMDGPU/gfx1250_asm_vop1_dpp8-fake16.s
M llvm/test/MC/AMDGPU/gfx1250_asm_vop1_dpp8.s
M llvm/test/MC/AMDGPU/gfx1250_asm_vop3_from_vop1-fake16.s
M llvm/test/MC/AMDGPU/gfx1250_asm_vop3_from_vop1.s
M llvm/test/MC/AMDGPU/gfx1250_asm_vop3_from_vop1_dpp16-fake16.s
M llvm/test/MC/AMDGPU/gfx1250_asm_vop3_from_vop1_dpp16.s
M llvm/test/MC/AMDGPU/gfx1250_asm_vop3_from_vop1_dpp8-fake16.s
M llvm/test/MC/AMDGPU/gfx1250_asm_vop3_from_vop1_dpp8.s
M llvm/test/MC/Disassembler/AMDGPU/gfx1250_dasm_vop1.txt
M llvm/test/MC/Disassembler/AMDGPU/gfx1250_dasm_vop1_dpp16.txt
M llvm/test/MC/Disassembler/AMDGPU/gfx1250_dasm_vop1_dpp8.txt
M llvm/test/MC/Disassembler/AMDGPU/gfx1250_dasm_vop3_from_vop1.txt
M llvm/test/MC/Disassembler/AMDGPU/gfx1250_dasm_vop3_from_vop1_dpp16.txt
M llvm/test/MC/Disassembler/AMDGPU/gfx1250_dasm_vop3_from_vop1_dpp8.txt
Log Message:
-----------
[AMDGPU] Add support for `v_rcp_bf16` on gfx1250 (#148916)
Co-authored-by: Mekhanoshin, Stanislav <Stanislav.Mekhanoshin at amd.com>
Commit: 23ac7b938d08db633ae6b99dfbce84ec76c0e702
https://github.com/llvm/llvm-project/commit/23ac7b938d08db633ae6b99dfbce84ec76c0e702
Author: Shilei Tian <i at tianshilei.me>
Date: 2025-07-15 (Tue, 15 Jul 2025)
Changed paths:
M llvm/lib/Target/AMDGPU/SIISelLowering.cpp
M llvm/lib/Target/AMDGPU/VOP1Instructions.td
A llvm/test/CodeGen/AMDGPU/llvm.amdgcn.sqrt.bf16.ll
A llvm/test/CodeGen/AMDGPU/llvm.sqrt.bf16.ll
M llvm/test/MC/AMDGPU/gfx1250_asm_vop1-fake16.s
M llvm/test/MC/AMDGPU/gfx1250_asm_vop1.s
M llvm/test/MC/AMDGPU/gfx1250_asm_vop1_dpp16-fake16.s
M llvm/test/MC/AMDGPU/gfx1250_asm_vop1_dpp16.s
M llvm/test/MC/AMDGPU/gfx1250_asm_vop1_dpp8-fake16.s
M llvm/test/MC/AMDGPU/gfx1250_asm_vop1_dpp8.s
M llvm/test/MC/AMDGPU/gfx1250_asm_vop3_from_vop1-fake16.s
M llvm/test/MC/AMDGPU/gfx1250_asm_vop3_from_vop1.s
M llvm/test/MC/AMDGPU/gfx1250_asm_vop3_from_vop1_dpp16-fake16.s
M llvm/test/MC/AMDGPU/gfx1250_asm_vop3_from_vop1_dpp16.s
M llvm/test/MC/AMDGPU/gfx1250_asm_vop3_from_vop1_dpp8-fake16.s
M llvm/test/MC/AMDGPU/gfx1250_asm_vop3_from_vop1_dpp8.s
M llvm/test/MC/Disassembler/AMDGPU/gfx1250_dasm_vop1.txt
M llvm/test/MC/Disassembler/AMDGPU/gfx1250_dasm_vop1_dpp16.txt
M llvm/test/MC/Disassembler/AMDGPU/gfx1250_dasm_vop1_dpp8.txt
M llvm/test/MC/Disassembler/AMDGPU/gfx1250_dasm_vop3_from_vop1.txt
M llvm/test/MC/Disassembler/AMDGPU/gfx1250_dasm_vop3_from_vop1_dpp16.txt
M llvm/test/MC/Disassembler/AMDGPU/gfx1250_dasm_vop3_from_vop1_dpp8.txt
Log Message:
-----------
[AMDGPU] Add support for `v_sqrt_bf16` on gfx1250 (#148921)
Co-authored-by: Mekhanoshin, Stanislav <Stanislav.Mekhanoshin at amd.com>
Commit: 1fe366d884728e37aca216891c77b16dc21ed03a
https://github.com/llvm/llvm-project/commit/1fe366d884728e37aca216891c77b16dc21ed03a
Author: cmtice <cmtice at google.com>
Date: 2025-07-15 (Tue, 15 Jul 2025)
Changed paths:
M lldb/test/API/commands/frame/var-dil/basics/QualifiedId/TestFrameVarDILQualifiedId.py
Log Message:
-----------
[LLDB] Disable DIL QualifiedId test on Windows. (#148940)
The lldb-x86_64-win buildbot is failing on this one DIL test. Disable
the test on Windows until we can debug it on Windows.
Commit: 8d61073128f8becdfaf7fb931c40a86d23fdd8e8
https://github.com/llvm/llvm-project/commit/8d61073128f8becdfaf7fb931c40a86d23fdd8e8
Author: Finn Plummer <finn.c.plum at gmail.com>
Date: 2025-07-15 (Tue, 15 Jul 2025)
Changed paths:
M clang/lib/Sema/SemaHLSL.cpp
Log Message:
-----------
[NFC][SemaHLSL] Fix typo causing float to double conversion (#148941)
- it was noted,
[here](https://github.com/llvm/llvm-project/pull/145795#discussion_r2208118547),
that by accidently not specifying this explicitly as a float it will
cause a build warning on MSVC
- this commit resolves this by explicitly specifying it as a float
Commit: 1a940bfff9176fb38a71b0045d7ae25df9a4ca7d
https://github.com/llvm/llvm-project/commit/1a940bfff9176fb38a71b0045d7ae25df9a4ca7d
Author: Jordan Rupprecht <rupprecht at google.com>
Date: 2025-07-15 (Tue, 15 Jul 2025)
Changed paths:
M mlir/include/mlir/Bindings/Python/NanobindAdaptors.h
Log Message:
-----------
[mlir][py] Fix nanobind uninitialized values (#148944)
After #143866, we no longer always write to `value`, causing it to be
uninitialized. This can lead to mysterious crashes, e.g. in
`python_test.py` / `testCustomAttribute` when we attempt to evaluate
`TestAttr(42)`, it does not set `value`, but
`mlirAttributeIsNull(value)` happens to return false for garbage memory,
and we end up trying to interpret it as a function instead of skipping
it.
Fix this by only reading `value` if it has been assigned. If it hasn't,
`return false` seems the right choice for all these methods, i.e.
indicate that `from_python` failed.
Commit: 42d2ae1034b287eb60563c370dbf52c59b66db20
https://github.com/llvm/llvm-project/commit/42d2ae1034b287eb60563c370dbf52c59b66db20
Author: Ahmed Bougacha <ahmed at bougacha.org>
Date: 2025-07-15 (Tue, 15 Jul 2025)
Changed paths:
M llvm/lib/Transforms/InstCombine/InstCombineCalls.cpp
M llvm/lib/Transforms/InstCombine/InstCombineInternal.h
A llvm/test/Transforms/InstCombine/ptrauth-call.ll
Log Message:
-----------
[InstCombine] Combine ptrauth constant callee into bundle. (#94706)
Try to optimize a call to a ptrauth constant, into its ptrauth bundle:
call(ptrauth(f)), ["ptrauth"()] -> call f
as long as the key/discriminator are the same in constant and bundle.
Commit: b4e2272271ee85273ca871abac2f6e9342da143d
https://github.com/llvm/llvm-project/commit/b4e2272271ee85273ca871abac2f6e9342da143d
Author: Valentin Clement (バレンタイン クレメン) <clementval at gmail.com>
Date: 2025-07-15 (Tue, 15 Jul 2025)
Changed paths:
M flang/lib/Lower/ConvertVariable.cpp
M flang/test/Lower/CUDA/cuda-set-allocator.cuf
Log Message:
-----------
[flang][cuda] Move cuf.set_allocator_idx after derived-type init (#148936)
Derived type initialization overwrite the component descriptor. Place
the `cuf.set_allocator_idx` after the initialization is performed.
Commit: 7f2bcd97cf4afc94e4badb2f6acd229003ef5912
https://github.com/llvm/llvm-project/commit/7f2bcd97cf4afc94e4badb2f6acd229003ef5912
Author: Artem Belevich <tra at google.com>
Date: 2025-07-15 (Tue, 15 Jul 2025)
Changed paths:
M clang/lib/Headers/CMakeLists.txt
A clang/lib/Headers/cuda_wrappers/__utility/declval.h
Log Message:
-----------
[CUDA] add wrapper header for libc++'s __utlility/declval.h (#148918)
Since #116709 more libc++ code relies on std::declval() and it broke
some CUDA compilations.
The new wrapper adds GPU-side overloads for the declval() helper
functions which allows it to continue working when used from CUDA
sources.
Commit: bc187b82705f31b5cd04fe986170f594ab2a51d4
https://github.com/llvm/llvm-project/commit/bc187b82705f31b5cd04fe986170f594ab2a51d4
Author: Philip Reames <preames at rivosinc.com>
Date: 2025-07-15 (Tue, 15 Jul 2025)
Changed paths:
M llvm/lib/Target/RISCV/RISCVInterleavedAccess.cpp
Log Message:
-----------
[RISCV] Use early-return in lowerInterleaveIntrinsicToStore [nfc]
Commit: c0785ea8bd76c36125bc9e5fad7bf787433635a5
https://github.com/llvm/llvm-project/commit/c0785ea8bd76c36125bc9e5fad7bf787433635a5
Author: David Peixotto <peix at meta.com>
Date: 2025-07-15 (Tue, 15 Jul 2025)
Changed paths:
M lldb/test/API/commands/plugin/TestPlugin.py
Log Message:
-----------
[lldb] Fix plugin test to not rely on enabled targets (#148956)
The plugins completion test was checking completions for the abi
plugins. But the available abi plugins will depend on which
[targets](https://github.com/llvm/llvm-project/blob/42d2ae1034b287eb60563c370dbf52c59b66db20/lldb/source/Plugins/ABI/CMakeLists.txt#L7)
are enabled in the cmake build configuration.
This PR updates the test to check for the json object file instead which
should be enabled on all builds.
Commit: 91d82bf4ab6c57a56d5797b40140b7c72b3de705
https://github.com/llvm/llvm-project/commit/91d82bf4ab6c57a56d5797b40140b7c72b3de705
Author: Maksim Levental <maksim.levental at gmail.com>
Date: 2025-07-15 (Tue, 15 Jul 2025)
Changed paths:
M mlir/lib/Dialect/OpenMP/IR/OpenMPDialect.cpp
Log Message:
-----------
[mlir] Fix u_int64_t in OpenMPDialect.cpp (#148963)
Commit: 4aa78c79da557b3fe1d19d2ad008f9e8e1353f1b
https://github.com/llvm/llvm-project/commit/4aa78c79da557b3fe1d19d2ad008f9e8e1353f1b
Author: Rahul Joshi <rjoshi at nvidia.com>
Date: 2025-07-15 (Tue, 15 Jul 2025)
Changed paths:
Log Message:
-----------
Fix OpenMPDialect.cpp build error (#148952)
Commit: fd543b3c46844f02404cd3cc91738da8a18e3765
https://github.com/llvm/llvm-project/commit/fd543b3c46844f02404cd3cc91738da8a18e3765
Author: LLVM GN Syncbot <llvmgnsyncbot at gmail.com>
Date: 2025-07-15 (Tue, 15 Jul 2025)
Changed paths:
M llvm/utils/gn/secondary/clang/lib/Headers/BUILD.gn
Log Message:
-----------
[gn build] Port 7f2bcd97cf4a
Commit: e685e4a7715ec51575fa37bc9d6bd6cf420cf655
https://github.com/llvm/llvm-project/commit/e685e4a7715ec51575fa37bc9d6bd6cf420cf655
Author: Slava Zakharin <szakharin at nvidia.com>
Date: 2025-07-15 (Tue, 15 Jul 2025)
Changed paths:
M llvm/lib/TableGen/StringToOffsetTable.cpp
M llvm/test/TableGen/RuntimeLibcallEmitter.td
Log Message:
-----------
TableGen: Fixed the string table definitions visibility. (#148946)
This fixes the buildbots issues reported in #148839.
Commit: 77bcab835aca155b67548c4a3cb1ae583abb1a14
https://github.com/llvm/llvm-project/commit/77bcab835aca155b67548c4a3cb1ae583abb1a14
Author: Ahmed Bougacha <ahmed at bougacha.org>
Date: 2025-07-15 (Tue, 15 Jul 2025)
Changed paths:
M llvm/lib/Transforms/InstCombine/InstCombineCalls.cpp
M llvm/lib/Transforms/InstCombine/InstCombineInternal.h
A llvm/test/Transforms/InstCombine/ptrauth-intrinsics-call.ll
Log Message:
-----------
[InstCombine] Combine ptrauth intrin. callee into same-key bundle. (#94707)
Try to optimize a call to the result of a ptrauth intrinsic, potentially
into the ptrauth call bundle:
call(ptrauth.resign(p)), ["ptrauth"()] -> call p, ["ptrauth"()]
call(ptrauth.sign(p)), ["ptrauth"()] -> call p
as long as the key/discriminator are the same in sign and auth-bundle,
and we don't change the key in the bundle (to a potentially-invalid
key.)
Generating a plain call to a raw unauthenticated pointer is generally
undesirable, but if we ended up seeing a naked ptrauth.sign in the first
place, we already have suspicious code. Unauthenticated calls are also
easier to spot than naked signs, so let the indirect call shine.
Note that there is an arguably unsafe extension to this, where we don't
bother checking that the key in bundle and intrinsic are the same (and
also allow folding away an auth into a bundle.)
This can end up generating calls with a bundle that has an invalid key
(which an informed frontend wouldn't have otherwise done), which can be
problematic. The C that generates that is straightforward but arguably
unreasonable. That wouldn't be an issue if we were to bite the bullet
and make these fully AArch64-specific, allowing key knowledge to be
embedded here.
Commit: bec508ad1719dfc8f0d85c5343ce44c3d1f326e1
https://github.com/llvm/llvm-project/commit/bec508ad1719dfc8f0d85c5343ce44c3d1f326e1
Author: Valentin Clement (バレンタイン クレメン) <clementval at gmail.com>
Date: 2025-07-15 (Tue, 15 Jul 2025)
Changed paths:
M mlir/lib/Target/LLVMIR/Dialect/NVVM/NVVMToLLVMIRTranslation.cpp
Log Message:
-----------
[mlir][nvvm] Fix control reaches end of non-void function warning (#148965)
Commit: b64d7baf9c0d37893ebabbe2539e725eb70b46e9
https://github.com/llvm/llvm-project/commit/b64d7baf9c0d37893ebabbe2539e725eb70b46e9
Author: Craig Topper <craig.topper at sifive.com>
Date: 2025-07-15 (Tue, 15 Jul 2025)
Changed paths:
M llvm/lib/Target/RISCV/RISCVInstrFormats.td
M llvm/lib/Target/RISCV/RISCVInstrInfoZicbo.td
Log Message:
-----------
[RISCV] Change the InstFormat for Zicbop prefetch instructions to InstFormatOther. (#148934)
The lower 5-bits of the immediate are not part of the address unlike
other InstFormatS instructions.
We use InstFormatS in RISCVRegisterInfo::needsFrameBaseReg and
RISCVRegisterInfo::getFrameIndexInstrOffset which is not aware of this
special encoding. Force the format to InstFormatOther so those functions
will ignore it.
InstFormatS is also used by relocation emission, but I don't believe we
ever emit these instructions with a relocation because of the encoding.
Commit: c36156de45a0f5e24e7a4ee2259c3302ea814785
https://github.com/llvm/llvm-project/commit/c36156de45a0f5e24e7a4ee2259c3302ea814785
Author: Yuxuan Chen <ych at fb.com>
Date: 2025-07-15 (Tue, 15 Jul 2025)
Changed paths:
M clang/lib/CodeGen/CGCoroutine.cpp
M clang/test/CodeGenCoroutines/coro-gro.cpp
Log Message:
-----------
[Clang] Fix FE crash during CGCoroutine GRO Alloca Emission (#148962)
Fixes: https://github.com/llvm/llvm-project/issues/148953
Currently when coroutine return object type is const qualified, we don't
do direct emission. The regular emission logic assumed that the auto var
emission will always result in an `AllocaInst`. However, based on my
findings, NRVO var emissions don't result in `AllocaInst`s. Therefore,
this
[assertion](https://github.com/llvm/llvm-project/blob/1a940bfff9176fb38a71b0045d7ae25df9a4ca7d/clang/lib/CodeGen/CGCoroutine.cpp#L712)
will fail.
Since the NRVOed returned object don't live on the coroutine frame, we
won't have the problem of it outliving the coroutine frame, therefore,
we can safely omit this metadata.
Commit: ae3bba4d15a10646ea91c6c0795633b82939857b
https://github.com/llvm/llvm-project/commit/ae3bba4d15a10646ea91c6c0795633b82939857b
Author: Ryosuke Niwa <rniwa at webkit.org>
Date: 2025-07-15 (Tue, 15 Jul 2025)
Changed paths:
M clang/lib/StaticAnalyzer/Checkers/WebKit/ASTUtils.cpp
M clang/test/Analysis/Checkers/WebKit/unretained-call-args.mm
Log Message:
-----------
WebKit checkers: recgonize @YES / @NO as safe constants (#148721)
Commit: 868793fa8e2f5aedb76fae09df6ca2128a165861
https://github.com/llvm/llvm-project/commit/868793fa8e2f5aedb76fae09df6ca2128a165861
Author: Changpeng Fang <changpeng.fang at amd.com>
Date: 2025-07-15 (Tue, 15 Jul 2025)
Changed paths:
M llvm/include/llvm/IR/IntrinsicsAMDGPU.td
M llvm/lib/Target/AMDGPU/AMDGPUGISel.td
M llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp
M llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.h
M llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
M llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.h
M llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
M llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp
M llvm/lib/Target/AMDGPU/AMDGPUSearchableTables.td
M llvm/lib/Target/AMDGPU/SIISelLowering.cpp
M llvm/lib/Target/AMDGPU/SIInstrInfo.td
M llvm/lib/Target/AMDGPU/SISchedule.td
M llvm/lib/Target/AMDGPU/VOP3PInstructions.td
M llvm/test/Analysis/UniformityAnalysis/AMDGPU/intrinsics.ll
A llvm/test/CodeGen/AMDGPU/llvm.amdgcn.wmma.gfx1250.w32.ll
A llvm/test/CodeGen/AMDGPU/llvm.amdgcn.wmma.imm.gfx1250.w32.ll
A llvm/test/CodeGen/AMDGPU/llvm.amdgcn.wmma.imod.gfx1250.w32.ll
A llvm/test/CodeGen/AMDGPU/llvm.amdgcn.wmma.index.gfx1250.w32.ll
Log Message:
-----------
AMDGPU: Support intrinsic selection for gfx1250 wmma instructions (#148957)
Co-authored-by: Stanislav Mekhanoshin <Stanislav.Mekhanoshin at amd.com>
Co-authored-by: Shilei Tian <Shilei.Tian at amd.com>
Commit: 5c4877ee0d2b5afcf23038b5cb0e82a03297657d
https://github.com/llvm/llvm-project/commit/5c4877ee0d2b5afcf23038b5cb0e82a03297657d
Author: Thurston Dang <thurston at google.com>
Date: 2025-07-15 (Tue, 15 Jul 2025)
Changed paths:
M llvm/lib/Transforms/Instrumentation/MemorySanitizer.cpp
M llvm/test/Instrumentation/MemorySanitizer/or.ll
Log Message:
-----------
[msan] Re-fix disjoint OR instrumentation from #145990 (#148760)
When disjoint OR was specified and a bit position contained a 1 in both
operands, #145990 would set the corresponding shadow bit to
uninitialized. However, the output of the operation is (LLVM) 'poison'
for the entire result, hence the entire shadow ought to be
uninitialized. This patch corrects the issue.
Commit: 116110e1a93531a64d82f049b6e36403bc14f278
https://github.com/llvm/llvm-project/commit/116110e1a93531a64d82f049b6e36403bc14f278
Author: Eli Friedman <efriedma at quicinc.com>
Date: 2025-07-15 (Tue, 15 Jul 2025)
Changed paths:
M clang/tools/libclang/libclang.map
Log Message:
-----------
[libclang] Fix version for symbol clang_visitCXXMethods (#148958)
Happened to spot this while looking at libclang.map for other reasons.
clang_visitCXXMethods was added in LLVM 21, not LLVM 20.
Commit: 3b41e4d4b5e57e4dc1a48a55f3bb683227863d81
https://github.com/llvm/llvm-project/commit/3b41e4d4b5e57e4dc1a48a55f3bb683227863d81
Author: Nikolas Klauser <nikolasklauser at berlin.de>
Date: 2025-07-16 (Wed, 16 Jul 2025)
Changed paths:
M libcxx/include/barrier
M libcxx/src/barrier.cpp
Log Message:
-----------
[libc++] Annotate barrier functions that are defined in the dylib (#148542)
This can improve code gen slightly.
Commit: 66e707ec68d6dc8d8f70083b68daf52559a862c1
https://github.com/llvm/llvm-project/commit/66e707ec68d6dc8d8f70083b68daf52559a862c1
Author: Harald van Dijk <harald.vandijk at codeplay.com>
Date: 2025-07-15 (Tue, 15 Jul 2025)
Changed paths:
M clang/include/clang/AST/ASTContext.h
M clang/include/clang/Basic/TargetInfo.h
M clang/lib/AST/ASTContext.cpp
M clang/lib/Sema/SemaExprCXX.cpp
M clang/lib/Sema/SemaLookup.cpp
M clang/lib/Sema/SemaRISCV.cpp
Log Message:
-----------
[NFC] Remove getDefaultCallingConvention IsBuiltin (#145904)
ASTContext::getDefaultCallingConvention() was documented as returning
"the default calling convention for the current target", but did not do
this, and was never intended to do this, it has always been controlled
by command-line options to deviate from the target default.
This commit changes ASTContext::getDefaultCallingConvention() to reflect
the fact that it returns the context's default calling convention, not
the target's default calling convention. The IsBuiltin parameter, which
was used to return the target's default calling convention rather than
the context's, is removed in favor of
getTargetInfo().getDefaultCallingConv() which is more explicit of the
intent.
Commit: 91ee01fda8b8801805708a51bba90796da376ae7
https://github.com/llvm/llvm-project/commit/91ee01fda8b8801805708a51bba90796da376ae7
Author: Kazu Hirata <kazu at google.com>
Date: 2025-07-15 (Tue, 15 Jul 2025)
Changed paths:
M clang/lib/Sema/SemaDeclAttr.cpp
M clang/lib/Sema/SemaM68k.cpp
M clang/lib/Sema/SemaMSP430.cpp
M clang/lib/Sema/SemaType.cpp
Log Message:
-----------
[Sema] Remove unnecessary casts (NFC) (#148871)
getArgAsExpr already returns Expr *.
Commit: 4bd0e9e7f354e8824af506f4ee6816fb0351ed78
https://github.com/llvm/llvm-project/commit/4bd0e9e7f354e8824af506f4ee6816fb0351ed78
Author: Craig Topper <craig.topper at sifive.com>
Date: 2025-07-15 (Tue, 15 Jul 2025)
Changed paths:
M llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
Log Message:
-----------
[RISCV] Add early out to reduce indentation in SelectAddrRegRegScale. NFC
Commit: 0f1b16dd5f83fd931ecb111bb925ac9e1d56f589
https://github.com/llvm/llvm-project/commit/0f1b16dd5f83fd931ecb111bb925ac9e1d56f589
Author: Akshay Deodhar <adeodhar at nvidia.com>
Date: 2025-07-15 (Tue, 15 Jul 2025)
Changed paths:
M llvm/lib/Target/NVPTX/MCTargetDesc/NVPTXInstPrinter.cpp
M llvm/lib/Target/NVPTX/MCTargetDesc/NVPTXInstPrinter.h
M llvm/lib/Target/NVPTX/NVPTX.h
M llvm/lib/Target/NVPTX/NVPTXISelDAGToDAG.cpp
M llvm/lib/Target/NVPTX/NVPTXISelDAGToDAG.h
M llvm/lib/Target/NVPTX/NVPTXISelLowering.cpp
M llvm/lib/Target/NVPTX/NVPTXInstrInfo.td
M llvm/lib/Target/NVPTX/NVPTXIntrinsics.td
M llvm/lib/Target/NVPTX/NVPTXUtilities.h
M llvm/test/CodeGen/NVPTX/atomicrmw-expand.ll
M llvm/test/CodeGen/NVPTX/atomics-sm70.ll
M llvm/test/CodeGen/NVPTX/atomics-sm90.ll
M llvm/test/CodeGen/NVPTX/cmpxchg-sm60.ll
M llvm/test/CodeGen/NVPTX/cmpxchg-sm70.ll
M llvm/test/CodeGen/NVPTX/cmpxchg-sm90.ll
M llvm/test/CodeGen/NVPTX/cmpxchg.ll
M llvm/test/CodeGen/NVPTX/cmpxchg.py
M llvm/test/CodeGen/NVPTX/distributed-shared-cluster.ll
Log Message:
-----------
[NVPTX] Add syncscope support for cmpxchg (#140812)
This MR adds support for cmpxchg instructions with syncscope.
- Adds a new definition for atomic 3-operand instructions, with constant
operands for sem, scope and addsp.
- Lowers cmpxchg SDNodes populating sem, scope and addsp using
SDNodeXForms.
- Handle syncscope correctly for emulation loops in AtomicExpand, in
bracketInstructionWithFences.
- Modifies emitLeadingFence, emitTrailingFence to accept SyncScope as a
parameter. Modifies implementation of these in other backends, with the
parameter being ignored.
- Tests for a _slice_ of all possible combinations of the cmpxchg
instruction (with modifications to cmpxchg.py)
---------
Co-authored-by: gonzalobg <65027571+gonzalobg at users.noreply.github.com>
Commit: c7d1eae4fc442a99085bae16be53a8087b9e5f25
https://github.com/llvm/llvm-project/commit/c7d1eae4fc442a99085bae16be53a8087b9e5f25
Author: Philip Reames <preames at rivosinc.com>
Date: 2025-07-15 (Tue, 15 Jul 2025)
Changed paths:
M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
Log Message:
-----------
[RISCV] Use masked segment LD/ST intrinsics in (de)interleaveN lowering [nfc] (#148966)
Follow up on the work from e5bc7e7d, and extend it to the lowering used
for interleave and deinterleave when we can't combine with a nearby
memory operation.
Commit: 2d6534b7daa0483f11f84d218fa1dc65eee44a93
https://github.com/llvm/llvm-project/commit/2d6534b7daa0483f11f84d218fa1dc65eee44a93
Author: Stanislav Mekhanoshin <rampitec at users.noreply.github.com>
Date: 2025-07-15 (Tue, 15 Jul 2025)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp
M llvm/lib/Target/AMDGPU/AMDGPUISelLowering.h
M llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
M llvm/lib/Target/AMDGPU/AMDGPUMCInstLower.cpp
M llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUELFObjectWriter.cpp
M llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUMCAsmInfo.cpp
M llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUMCCodeEmitter.cpp
M llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUMCExpr.h
M llvm/lib/Target/AMDGPU/SIISelLowering.cpp
M llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
M llvm/lib/Target/AMDGPU/SIInstrInfo.h
M llvm/lib/Target/AMDGPU/SIInstrInfo.td
M llvm/lib/Target/AMDGPU/SIInstructions.td
A llvm/test/CodeGen/AMDGPU/global-address.ll
M llvm/test/CodeGen/MIR/AMDGPU/target-flags.mir
A llvm/test/MC/AMDGPU/fixup64.s
Log Message:
-----------
[AMDGPU] gfx1250 64-bit relocations and fixups (#148951)
Commit: 82d7405b3bb911c86d0b07c8a6bec5044acbdf66
https://github.com/llvm/llvm-project/commit/82d7405b3bb911c86d0b07c8a6bec5044acbdf66
Author: Stanislav Mekhanoshin <rampitec at users.noreply.github.com>
Date: 2025-07-15 (Tue, 15 Jul 2025)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPU.td
M llvm/lib/Target/AMDGPU/GCNSubtarget.h
M llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
M llvm/lib/Target/AMDGPU/SOPInstructions.td
A llvm/test/CodeGen/AMDGPU/branch-relaxation-gfx1250.ll
M llvm/test/MC/AMDGPU/gfx1250_asm_sop1.s
M llvm/test/MC/Disassembler/AMDGPU/gfx1250_dasm_sop1.txt
Log Message:
-----------
[AMDGPU] Use S_ADD_PC_I64 for long branches in gfx1250 (#148961)
Commit: 5458151817c5f46c05a6b7c472085e51aa55c892
https://github.com/llvm/llvm-project/commit/5458151817c5f46c05a6b7c472085e51aa55c892
Author: Florian Mayer <fmayer at google.com>
Date: 2025-07-15 (Tue, 15 Jul 2025)
Changed paths:
M llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
M llvm/test/CodeGen/X86/invalid-operand-bundle-call.ll
M llvm/test/CodeGen/X86/invalid-operand-bundle-callbr.ll
Log Message:
-----------
[SelectionDAG] improve error messages for invalid operator bundle (#148945)
Commit: b1a93cfc32fbe912bb9b97796145501ea453d1bd
https://github.com/llvm/llvm-project/commit/b1a93cfc32fbe912bb9b97796145501ea453d1bd
Author: Ross Kirsling <ross.kirsling at sony.com>
Date: 2025-07-16 (Wed, 16 Jul 2025)
Changed paths:
M llvm/lib/Transforms/InstCombine/InstCombineCompares.cpp
A llvm/test/Transforms/InstCombine/fold-icmp-without-constant-into-phi.ll
Log Message:
-----------
[InstCombine] foldOpIntoPhi should apply to icmp with non-constant operand (#147676)
Alive2: https://alive2.llvm.org/ce/z/4MeCzA
Fixes #146263.
Commit: 386f73d4fb67649d5518d9a0cd5a49498bf608ca
https://github.com/llvm/llvm-project/commit/386f73d4fb67649d5518d9a0cd5a49498bf608ca
Author: Ross Kirsling <ross.kirsling at sony.com>
Date: 2025-07-16 (Wed, 16 Jul 2025)
Changed paths:
M llvm/test/tools/llvm-objcopy/ELF/strip-preserve-atime.test
Log Message:
-----------
[llvm-objcopy] Explain that strip-preserve-atime.test fails with Crowdstrike (#145783)
Related to #82372.
Not a fix per se, but an acknowledgment and a workaround.
Commit: 4b81dc75f4a5b8651d6a4c4ac8840049dc9ae289
https://github.com/llvm/llvm-project/commit/4b81dc75f4a5b8651d6a4c4ac8840049dc9ae289
Author: Philip Reames <preames at rivosinc.com>
Date: 2025-07-15 (Tue, 15 Jul 2025)
Changed paths:
M llvm/include/llvm/CodeGen/TargetLowering.h
M llvm/lib/CodeGen/InterleavedAccessPass.cpp
M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
M llvm/lib/Target/AArch64/AArch64ISelLowering.h
M llvm/lib/Target/RISCV/RISCVISelLowering.h
M llvm/lib/Target/RISCV/RISCVInterleavedAccess.cpp
Log Message:
-----------
[IA] Use a single callback for lowerDeinterleaveIntrinsic [nfc] (#148978)
This essentially merges the handling for VPLoad - currently in
lowerInterleavedVPLoad which is shared between shuffle and intrinsic
based interleaves - into the existing dedicated routine.
My plan is that if we like this factoring is that I'll do the same for
the intrinsic store paths, and then remove the excess generality from
the shuffle paths since we don't need to support both modes in the
shared VPLoad/Store callbacks. We can probably even fold the VP versions
into the non-VP shuffle variants in the analogous way.
Commit: 01dd892734614cad30d7b50e5acc1c533a3fd39c
https://github.com/llvm/llvm-project/commit/01dd892734614cad30d7b50e5acc1c533a3fd39c
Author: Changpeng Fang <changpeng.fang at amd.com>
Date: 2025-07-15 (Tue, 15 Jul 2025)
Changed paths:
M llvm/include/llvm/IR/IntrinsicsAMDGPU.td
M llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp
M llvm/test/Analysis/UniformityAnalysis/AMDGPU/intrinsics.ll
Log Message:
-----------
AMDGPU: Remove a non-existent wmma instruction from gfx1250 (#148989)
Commit: c962f2b29d55138d0b3849a7b8b557108188bb4f
https://github.com/llvm/llvm-project/commit/c962f2b29d55138d0b3849a7b8b557108188bb4f
Author: Changpeng Fang <changpeng.fang at amd.com>
Date: 2025-07-15 (Tue, 15 Jul 2025)
Changed paths:
M clang/include/clang/Basic/BuiltinsAMDGPU.def
M clang/lib/CodeGen/TargetBuiltins/AMDGPU.cpp
A clang/test/CodeGenOpenCL/builtins-amdgcn-gfx1250-wmma-w32.cl
A clang/test/SemaOpenCL/builtins-amdgcn-error-gfx1250-wmma-w32-param.cl
Log Message:
-----------
AMDGPU: Implement builtins for gfx1250 wmma instructions (#148991)
Co-authored-by: Stanislav Mekhanoshin <Stanislav.Mekhanoshin at amd.com>
Co-authored-by: Shilei Tian <Shilei.Tian at amd.com>
Commit: 36e4174989f866c9f97acb35c0d3b80ef61e9459
https://github.com/llvm/llvm-project/commit/36e4174989f866c9f97acb35c0d3b80ef61e9459
Author: Craig Topper <craig.topper at sifive.com>
Date: 2025-07-15 (Tue, 15 Jul 2025)
Changed paths:
M llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
A llvm/test/CodeGen/AArch64/pr148949.ll
Log Message:
-----------
[DAGCombiner][AArch64] Prevent SimplifyVCastOp from creating illegal scalar types after type legalization. (#148970)
Fixes #148949
Commit: a87b8398f9e94ea363c170625e015074fecfd318
https://github.com/llvm/llvm-project/commit/a87b8398f9e94ea363c170625e015074fecfd318
Author: Craig Topper <craig.topper at sifive.com>
Date: 2025-07-15 (Tue, 15 Jul 2025)
Changed paths:
M llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
Log Message:
-----------
[RISCV] Simplify conversion from ISD::Constant to ISD::TargetConstant in SelectAddrRegRegScale. NFC
Directly copy the underlying ConstantInt instead of reconstructing it.
Commit: 5ff99f2757a62c52079397602dbd0c2e9d9f0ae7
https://github.com/llvm/llvm-project/commit/5ff99f2757a62c52079397602dbd0c2e9d9f0ae7
Author: Craig Topper <craig.topper at sifive.com>
Date: 2025-07-15 (Tue, 15 Jul 2025)
Changed paths:
M llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
Log Message:
-----------
[RISCV] Remove duplicate check in an if statement. NFC
Commit: 513a6465ba09d63ca179aa8122845e3abd5bd62b
https://github.com/llvm/llvm-project/commit/513a6465ba09d63ca179aa8122845e3abd5bd62b
Author: yronglin <yronglin777 at gmail.com>
Date: 2025-07-16 (Wed, 16 Jul 2025)
Changed paths:
M clang/test/CXX/module/module.interface/p1.cpp
Log Message:
-----------
[NFC][clang] Refactor CXX/module/module.interface/p1.cpp with split-file (#148861)
Refine CXX/module/module.interface/p1.cpp with split-file.
This MR is a part of https://github.com/llvm/llvm-project/pull/107168.
Signed-off-by: yronglin <yronglin777 at gmail.com>
Commit: 0f6a2db2594f5ffaf9bcd03f8233a850aa7d32af
https://github.com/llvm/llvm-project/commit/0f6a2db2594f5ffaf9bcd03f8233a850aa7d32af
Author: Harrison Hao <57025411+harrisonGPU at users.noreply.github.com>
Date: 2025-07-16 (Wed, 16 Jul 2025)
Changed paths:
A llvm/test/CodeGen/AMDGPU/merge-tbuffer-gfx10.mir
A llvm/test/CodeGen/AMDGPU/merge-tbuffer-gfx11.mir
A llvm/test/CodeGen/AMDGPU/merge-tbuffer-gfx9.mir
R llvm/test/CodeGen/AMDGPU/merge-tbuffer.mir
Log Message:
-----------
[NFC][AMDGPU] Split merge-tbuffer.mir into separate tests for gfx9, gfx10, and gfx11 (#148786)
For https://github.com/llvm/llvm-project/pull/145078
Commit: 28e1473e8e523150914e8c7ea50b44fb0d2a8d65
https://github.com/llvm/llvm-project/commit/28e1473e8e523150914e8c7ea50b44fb0d2a8d65
Author: Fangrui Song <i at maskray.me>
Date: 2025-07-15 (Tue, 15 Jul 2025)
Changed paths:
M llvm/include/llvm/MC/MCAssembler.h
M llvm/include/llvm/MC/MCELFStreamer.h
M llvm/include/llvm/MC/MCObjectStreamer.h
M llvm/include/llvm/MC/MCSection.h
M llvm/include/llvm/MC/MCStreamer.h
M llvm/lib/MC/MCAsmStreamer.cpp
M llvm/lib/MC/MCAssembler.cpp
M llvm/lib/MC/MCELFStreamer.cpp
M llvm/lib/MC/MCFragment.cpp
M llvm/lib/MC/MCObjectStreamer.cpp
M llvm/lib/MC/MCParser/AsmParser.cpp
M llvm/lib/MC/MCSection.cpp
M llvm/lib/MC/MCStreamer.cpp
M llvm/lib/Target/X86/MCTargetDesc/X86AsmBackend.cpp
R llvm/test/MC/ARM/AlignedBundling/group-bundle-arm.s
R llvm/test/MC/ARM/AlignedBundling/illegal-subtarget-change.s
R llvm/test/MC/ARM/AlignedBundling/lit.local.cfg
R llvm/test/MC/ARM/AlignedBundling/pad-align-to-bundle-end.s
R llvm/test/MC/ARM/AlignedBundling/subtarget-change.s
M llvm/test/MC/AsmParser/AArch64/directive-parse-err.s
R llvm/test/MC/X86/AlignedBundling/align-mode-argument-error.s
R llvm/test/MC/X86/AlignedBundling/asm-printing-bundle-directives.s
R llvm/test/MC/X86/AlignedBundling/autogen-inst-offset-align-to-end.s
R llvm/test/MC/X86/AlignedBundling/autogen-inst-offset-padding.s
R llvm/test/MC/X86/AlignedBundling/bundle-group-too-large-error.s
R llvm/test/MC/X86/AlignedBundling/bundle-lock-option-error.s
R llvm/test/MC/X86/AlignedBundling/bundle-subtarget-change-error.s
R llvm/test/MC/X86/AlignedBundling/different-sections.s
R llvm/test/MC/X86/AlignedBundling/labeloffset.s
R llvm/test/MC/X86/AlignedBundling/lit.local.cfg
R llvm/test/MC/X86/AlignedBundling/lock-without-bundle-mode-error.s
R llvm/test/MC/X86/AlignedBundling/long-nop-pad.s
R llvm/test/MC/X86/AlignedBundling/misaligned-bundle-group.s
R llvm/test/MC/X86/AlignedBundling/misaligned-bundle.s
R llvm/test/MC/X86/AlignedBundling/nesting.s
R llvm/test/MC/X86/AlignedBundling/pad-align-to-bundle-end.s
R llvm/test/MC/X86/AlignedBundling/pad-bundle-groups.s
R llvm/test/MC/X86/AlignedBundling/relax-at-bundle-end.s
R llvm/test/MC/X86/AlignedBundling/relax-in-bundle-group.s
R llvm/test/MC/X86/AlignedBundling/section-alignment.s
R llvm/test/MC/X86/AlignedBundling/single-inst-bundling.s
R llvm/test/MC/X86/AlignedBundling/switch-section-locked-error.s
R llvm/test/MC/X86/AlignedBundling/unlock-without-lock-error.s
R llvm/test/MC/X86/align-branch-bundle.s
Log Message:
-----------
MC: Remove bundle alignment mode
The being-removed PNaCl has a Software Fault Isolation mechanism, which
requires that certain instructions and groups of instructions do not
cross a bundle boundary. When `.bundle_align_mode` is in effect, each
instruction is placed in its own fragment, allowing flexible NOP
padding.
This feature has significantly complicated our refactoring of MCStreamer
and MCFragment, leading to considerable effort spent untangling
it (including flushPendingLabels (75006466296ed4b0f845cbbec4bf77c21de43b40),
MCAssembler iteration improvement, and recent MCFragment refactoring).
* Make MCObjectStreamer::emitInstToData non-virtual and delete
MCELFStreamer::emitInstTodata
* Delete MCELFStreamer::emitValueImpl and emitValueToAlignment
Minor instructions:u decrease for both -O0 -g and -O3 builds
https://llvm-compile-time-tracker.com/compare.php?from=c06d3a7b728293cbc53ff91239d6cd87c0982ffb&to=9b078c7f228bc5b6cdbfe839f751c9407f8aec3e&stat=instructions:u
Pull Request: https://github.com/llvm/llvm-project/pull/148781
Commit: 968d38d1d7d9de2d5717457876bba2663b36f620
https://github.com/llvm/llvm-project/commit/968d38d1d7d9de2d5717457876bba2663b36f620
Author: Peter Collingbourne <peter at pcc.me.uk>
Date: 2025-07-15 (Tue, 15 Jul 2025)
Changed paths:
M compiler-rt/test/lit.common.cfg.py
Log Message:
-----------
compiler-rt: test: Use the host instead of the target to select %expect_crash.
When running tests in a cross-compiled build, %expect_crash is
run on the host, not the target, so we need to check the host
OS. config.host_os surprisingly refers to the target OS because it
is derived from CMAKE_SYSTEM_NAME which specifies the target. See:
https://cmake.org/cmake/help/latest/variable/CMAKE_SYSTEM_NAME.html
Another speculative fix for:
https://lab.llvm.org/buildbot/#/builders/193/builds/9070
Commit: fa88c188de33b00e133973129338efd48a2c7d0b
https://github.com/llvm/llvm-project/commit/fa88c188de33b00e133973129338efd48a2c7d0b
Author: Uday Bondhugula <uday at polymagelabs.com>
Date: 2025-07-16 (Wed, 16 Jul 2025)
Changed paths:
M mlir/include/mlir/Dialect/Affine/Analysis/AffineAnalysis.h
M mlir/lib/Dialect/Affine/Analysis/Utils.cpp
Log Message:
-----------
[MLIR][Affine] Add default null init for mlir::affine::MemRefAccess (#147922)
Add default null init for `mlir::affine::MemRefAccess`. This is
consistent with various other MLIR structures and had been missing for
`mlir::affine::MemRefAccess`.
Commit: 8ec03f49dc417897a9ecffb3c5bc63c8e3e43ab7
https://github.com/llvm/llvm-project/commit/8ec03f49dc417897a9ecffb3c5bc63c8e3e43ab7
Author: Eli Friedman <efriedma at quicinc.com>
Date: 2025-07-15 (Tue, 15 Jul 2025)
Changed paths:
M llvm/docs/LangRef.rst
Log Message:
-----------
Clarify semantics for overflowing constrained lrint etc. (#148979)
This fixes llvm.experimental.constrained.lrint and friends to use the
same semantics as llvm.lrint and friends, as defined in
ba5c26da7ce85dbdcee3d964282e5f0981792702.
Commit: 156e4cb10e5863daf94154892e1d859ab1a4b57a
https://github.com/llvm/llvm-project/commit/156e4cb10e5863daf94154892e1d859ab1a4b57a
Author: Fangrui Song <i at maskray.me>
Date: 2025-07-15 (Tue, 15 Jul 2025)
Changed paths:
M llvm/lib/Target/NVPTX/MCTargetDesc/NVPTXInstPrinter.cpp
M llvm/lib/Target/NVPTX/NVPTX.h
Log Message:
-----------
NVPTX: Fix clang -Wcovered-switch-default
Commit: b43c30dbd97c563afd1c7d44860d592478703421
https://github.com/llvm/llvm-project/commit/b43c30dbd97c563afd1c7d44860d592478703421
Author: Fangrui Song <i at maskray.me>
Date: 2025-07-15 (Tue, 15 Jul 2025)
Changed paths:
M clang-tools-extra/clangd/ModulesBuilder.cpp
M clang-tools-extra/docs/ReleaseNotes.rst
A clang-tools-extra/test/clang-query/trailing-comma.c
M clang/docs/ReleaseNotes.rst
M clang/include/clang/AST/ASTContext.h
M clang/include/clang/AST/Decl.h
M clang/include/clang/ASTMatchers/ASTMatchers.h
M clang/include/clang/Basic/BuiltinsAMDGPU.def
M clang/include/clang/Basic/BuiltinsPPC.def
M clang/include/clang/Basic/CodeGenOptions.def
M clang/include/clang/Basic/CodeGenOptions.h
M clang/include/clang/Basic/DebugOptions.def
M clang/include/clang/Basic/DiagnosticSerializationKinds.td
M clang/include/clang/Basic/LangOptions.def
M clang/include/clang/Basic/TargetInfo.h
M clang/include/clang/Frontend/ASTUnit.h
M clang/include/clang/Frontend/CompilerInstance.h
M clang/include/clang/Serialization/ASTBitCodes.h
M clang/include/clang/Serialization/ASTReader.h
M clang/include/clang/Serialization/ASTWriter.h
M clang/lib/AST/ASTContext.cpp
M clang/lib/AST/Decl.cpp
M clang/lib/ASTMatchers/Dynamic/Parser.cpp
M clang/lib/Basic/CMakeLists.txt
M clang/lib/Basic/CodeGenOptions.cpp
M clang/lib/Basic/OpenMPKinds.cpp
M clang/lib/Basic/Targets.cpp
M clang/lib/Basic/Targets/ARM.cpp
M clang/lib/Basic/Targets/OSTargets.h
R clang/lib/Basic/Targets/PNaCl.cpp
R clang/lib/Basic/Targets/PNaCl.h
M clang/lib/CodeGen/CGCoroutine.cpp
M clang/lib/CodeGen/CGDebugInfo.cpp
M clang/lib/CodeGen/CGOpenMPRuntime.cpp
M clang/lib/CodeGen/CMakeLists.txt
M clang/lib/CodeGen/CodeGenAction.cpp
M clang/lib/CodeGen/CodeGenModule.cpp
M clang/lib/CodeGen/TargetBuiltins/AMDGPU.cpp
M clang/lib/CodeGen/TargetBuiltins/PPC.cpp
M clang/lib/CodeGen/TargetInfo.h
R clang/lib/CodeGen/Targets/PNaCl.cpp
M clang/lib/CodeGen/Targets/X86.cpp
M clang/lib/Driver/CMakeLists.txt
M clang/lib/Driver/Driver.cpp
R clang/lib/Driver/ToolChains/NaCl.cpp
R clang/lib/Driver/ToolChains/NaCl.h
M clang/lib/Frontend/ASTUnit.cpp
M clang/lib/Frontend/ChainedIncludesSource.cpp
M clang/lib/Frontend/CompilerInstance.cpp
M clang/lib/Frontend/CompilerInvocation.cpp
M clang/lib/Frontend/FrontendAction.cpp
M clang/lib/Frontend/FrontendActions.cpp
M clang/lib/Frontend/InitPreprocessor.cpp
M clang/lib/Frontend/PrecompiledPreamble.cpp
M clang/lib/Headers/CMakeLists.txt
A clang/lib/Headers/cuda_wrappers/__utility/declval.h
M clang/lib/Lex/InitHeaderSearch.cpp
M clang/lib/Sema/SemaDeclAttr.cpp
M clang/lib/Sema/SemaExprCXX.cpp
M clang/lib/Sema/SemaHLSL.cpp
M clang/lib/Sema/SemaLookup.cpp
M clang/lib/Sema/SemaM68k.cpp
M clang/lib/Sema/SemaMSP430.cpp
M clang/lib/Sema/SemaRISCV.cpp
M clang/lib/Sema/SemaType.cpp
M clang/lib/Sema/TreeTransform.h
M clang/lib/Serialization/ASTReader.cpp
M clang/lib/Serialization/ASTWriter.cpp
M clang/lib/Serialization/GeneratePCH.cpp
M clang/lib/StaticAnalyzer/Checkers/WebKit/ASTUtils.cpp
M clang/test/Analysis/Checkers/WebKit/unretained-call-args.mm
M clang/test/CXX/module/module.interface/p1.cpp
M clang/test/CodeGen/PowerPC/builtins-ppc-dmf.c
A clang/test/CodeGen/PowerPC/ppc-dmf-future-builtin-err.c
A clang/test/CodeGen/PowerPC/ppc-dmf-mma-builtin-err.c
R clang/test/CodeGen/PowerPC/ppc-future-mma-builtin-err.c
R clang/test/CodeGen/X86/x86_64-arguments-nacl.c
M clang/test/CodeGen/X86/x86_64-longdouble.c
M clang/test/CodeGen/arm-aapcs-vfp.c
M clang/test/CodeGen/ext-int-cc.c
M clang/test/CodeGen/long_double_fp128.cpp
R clang/test/CodeGen/malign-double-x86-nacl.c
M clang/test/CodeGen/target-data.c
R clang/test/CodeGenCXX/x86_64-arguments-nacl-x32.cpp
M clang/test/CodeGenCoroutines/coro-gro.cpp
A clang/test/CodeGenOpenCL/builtins-amdgcn-gfx1250-wmma-w32.cl
M clang/test/CodeGenOpenCL/builtins-amdgcn-gfx1250.cl
M clang/test/Driver/DTLTO/dtlto.c
M clang/test/Driver/arm-alignment.c
R clang/test/Driver/nacl-direct.c
M clang/test/Driver/unsupported-target-arch.c
R clang/test/Driver/x86_64-nacl-defines.cpp
R clang/test/Frontend/x86_64-nacl-types.cpp
M clang/test/PCH/no-validate-pch.cl
M clang/test/Preprocessor/predefined-macros-no-warnings.c
A clang/test/SemaOpenCL/builtins-amdgcn-error-gfx1250-wmma-w32-param.cl
A clang/test/SemaTemplate/gh138371.cpp
M clang/tools/libclang/libclang.map
M clang/unittests/ASTMatchers/ASTMatchersNarrowingTest.cpp
M compiler-rt/test/lit.common.cfg.py
M flang/lib/Lower/ConvertVariable.cpp
M flang/test/Lower/CUDA/cuda-set-allocator.cuf
M libc/fuzzing/math/CMakeLists.txt
R libc/fuzzing/math/atan_fuzz.cpp
A libc/fuzzing/math/log10_fuzz.cpp
A libc/fuzzing/math/log1p_fuzz.cpp
A libc/fuzzing/math/log2_fuzz.cpp
A libc/fuzzing/math/log_fuzz.cpp
M libc/fuzzing/math/sincos_fuzz.cpp
A libc/fuzzing/math/sqrt_fuzz.cpp
M libcxx/include/barrier
M libcxx/src/barrier.cpp
M lldb/include/lldb/Core/PluginManager.h
M lldb/include/lldb/Interpreter/CommandCompletions.h
M lldb/include/lldb/Utility/Listener.h
M lldb/include/lldb/lldb-enumerations.h
M lldb/packages/Python/lldbsuite/test/lldbtest.py
M lldb/packages/Python/lldbsuite/test/make/Makefile.rules
M lldb/source/Commands/CommandCompletions.cpp
M lldb/source/Commands/CommandObjectPlugin.cpp
M lldb/source/Core/PluginManager.cpp
M lldb/source/Plugins/TypeSystem/Clang/TypeSystemClang.cpp
M lldb/source/Utility/Broadcaster.cpp
M lldb/source/Utility/Listener.cpp
M lldb/test/API/commands/frame/var-dil/basics/QualifiedId/TestFrameVarDILQualifiedId.py
M lldb/test/API/commands/plugin/TestPlugin.py
M lldb/test/API/functionalities/data-formatter/data-formatter-advanced/main.cpp
M lldb/unittests/Utility/ListenerTest.cpp
A llvm/clang/test/Modules/implicit-opt-level.c
M llvm/docs/HowToSubmitABug.rst
M llvm/docs/LangRef.rst
M llvm/include/llvm/ADT/StringTable.h
M llvm/include/llvm/BinaryFormat/ELF.h
M llvm/include/llvm/BinaryFormat/MinidumpConstants.def
M llvm/include/llvm/CodeGen/AtomicExpandUtils.h
M llvm/include/llvm/CodeGen/BasicTTIImpl.h
M llvm/include/llvm/CodeGen/TargetLowering.h
M llvm/include/llvm/IR/IntrinsicsAMDGPU.td
M llvm/include/llvm/MC/MCAsmBackend.h
M llvm/include/llvm/MC/MCAssembler.h
M llvm/include/llvm/MC/MCELFStreamer.h
M llvm/include/llvm/MC/MCObjectStreamer.h
M llvm/include/llvm/MC/MCSection.h
M llvm/include/llvm/MC/MCStreamer.h
M llvm/include/llvm/MC/MCWasmStreamer.h
M llvm/include/llvm/TargetParser/Triple.h
M llvm/lib/Analysis/IR2Vec.cpp
M llvm/lib/CodeGen/InterleavedAccessPass.cpp
M llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
M llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
M llvm/lib/IR/Intrinsics.cpp
M llvm/lib/MC/MCAsmStreamer.cpp
M llvm/lib/MC/MCAssembler.cpp
M llvm/lib/MC/MCELFStreamer.cpp
M llvm/lib/MC/MCFragment.cpp
M llvm/lib/MC/MCObjectStreamer.cpp
M llvm/lib/MC/MCParser/AsmParser.cpp
M llvm/lib/MC/MCSection.cpp
M llvm/lib/MC/MCStreamer.cpp
M llvm/lib/MC/WasmObjectWriter.cpp
M llvm/lib/MC/WinCOFFObjectWriter.cpp
M llvm/lib/Support/rpmalloc/rpmalloc.c
M llvm/lib/TableGen/StringToOffsetTable.cpp
M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
M llvm/lib/Target/AArch64/AArch64ISelLowering.h
M llvm/lib/Target/AMDGPU/AMDGPU.td
M llvm/lib/Target/AMDGPU/AMDGPUGISel.td
M llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp
M llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.h
M llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp
M llvm/lib/Target/AMDGPU/AMDGPUISelLowering.h
M llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
M llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.h
M llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
M llvm/lib/Target/AMDGPU/AMDGPUMCInstLower.cpp
M llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp
M llvm/lib/Target/AMDGPU/AMDGPUSearchableTables.td
M llvm/lib/Target/AMDGPU/GCNSubtarget.h
M llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUELFObjectWriter.cpp
M llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUMCAsmInfo.cpp
M llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUMCCodeEmitter.cpp
M llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUMCExpr.h
M llvm/lib/Target/AMDGPU/SIISelLowering.cpp
M llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
M llvm/lib/Target/AMDGPU/SIInstrInfo.h
M llvm/lib/Target/AMDGPU/SIInstrInfo.td
M llvm/lib/Target/AMDGPU/SIInstructions.td
M llvm/lib/Target/AMDGPU/SISchedule.td
M llvm/lib/Target/AMDGPU/SOPInstructions.td
M llvm/lib/Target/AMDGPU/VOP1Instructions.td
M llvm/lib/Target/AMDGPU/VOP3PInstructions.td
M llvm/lib/Target/ARM/ARMAsmPrinter.cpp
M llvm/lib/Target/ARM/ARMFastISel.cpp
M llvm/lib/Target/ARM/ARMFeatures.td
M llvm/lib/Target/ARM/ARMFrameLowering.cpp
M llvm/lib/Target/ARM/ARMISelLowering.cpp
M llvm/lib/Target/ARM/ARMInstrInfo.td
M llvm/lib/Target/ARM/ARMPredicates.td
M llvm/lib/Target/ARM/ARMSubtarget.cpp
M llvm/lib/Target/ARM/ARMSubtarget.h
M llvm/lib/Target/ARM/ARMTargetMachine.cpp
M llvm/lib/Target/ARM/ARMTargetTransformInfo.h
M llvm/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.cpp
M llvm/lib/Target/DirectX/DXILLegalizePass.cpp
M llvm/lib/Target/Mips/MCTargetDesc/CMakeLists.txt
R llvm/lib/Target/Mips/MCTargetDesc/MipsMCNaCl.h
M llvm/lib/Target/Mips/MCTargetDesc/MipsMCTargetDesc.cpp
R llvm/lib/Target/Mips/MCTargetDesc/MipsNaClELFStreamer.cpp
M llvm/lib/Target/Mips/MipsAsmPrinter.cpp
M llvm/lib/Target/Mips/MipsAsmPrinter.h
M llvm/lib/Target/Mips/MipsBranchExpansion.cpp
M llvm/lib/Target/Mips/MipsCallingConv.td
M llvm/lib/Target/Mips/MipsDelaySlotFiller.cpp
M llvm/lib/Target/Mips/MipsInstrFPU.td
M llvm/lib/Target/Mips/MipsInstrInfo.td
M llvm/lib/Target/Mips/MipsRegisterInfo.cpp
M llvm/lib/Target/Mips/MipsSubtarget.h
M llvm/lib/Target/NVPTX/MCTargetDesc/NVPTXInstPrinter.cpp
M llvm/lib/Target/NVPTX/MCTargetDesc/NVPTXInstPrinter.h
M llvm/lib/Target/NVPTX/NVPTX.h
M llvm/lib/Target/NVPTX/NVPTXISelDAGToDAG.cpp
M llvm/lib/Target/NVPTX/NVPTXISelDAGToDAG.h
M llvm/lib/Target/NVPTX/NVPTXISelLowering.cpp
M llvm/lib/Target/NVPTX/NVPTXInstrInfo.td
M llvm/lib/Target/NVPTX/NVPTXIntrinsics.td
M llvm/lib/Target/NVPTX/NVPTXUtilities.h
M llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
M llvm/lib/Target/RISCV/RISCVISelLowering.h
M llvm/lib/Target/RISCV/RISCVInstrFormats.td
M llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
M llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td
M llvm/lib/Target/RISCV/RISCVInstrInfoZicbo.td
M llvm/lib/Target/RISCV/RISCVInterleavedAccess.cpp
M llvm/lib/Target/X86/MCTargetDesc/X86AsmBackend.cpp
M llvm/lib/Target/X86/X86ExpandPseudo.cpp
M llvm/lib/Target/X86/X86FrameLowering.cpp
M llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
M llvm/lib/Target/X86/X86ISelLowering.cpp
M llvm/lib/Target/X86/X86InstrPredicates.td
M llvm/lib/Target/X86/X86Subtarget.cpp
M llvm/lib/Target/X86/X86Subtarget.h
M llvm/lib/Target/X86/X86TargetMachine.cpp
M llvm/lib/TargetParser/ARMTargetParser.cpp
M llvm/lib/TargetParser/Triple.cpp
M llvm/lib/Transforms/InstCombine/InstCombineCalls.cpp
M llvm/lib/Transforms/InstCombine/InstCombineCompares.cpp
M llvm/lib/Transforms/InstCombine/InstCombineInternal.h
M llvm/lib/Transforms/Instrumentation/MemorySanitizer.cpp
M llvm/test/Analysis/CostModel/AArch64/arith-overflow.ll
M llvm/test/Analysis/CostModel/AArch64/cmp.ll
M llvm/test/Analysis/CostModel/AArch64/fcmp.ll
M llvm/test/Analysis/CostModel/AArch64/fshl.ll
M llvm/test/Analysis/CostModel/AArch64/fshr.ll
M llvm/test/Analysis/CostModel/AArch64/sve-cmpsel.ll
M llvm/test/Analysis/CostModel/AArch64/sve-fcmp.ll
M llvm/test/Analysis/CostModel/AArch64/sve-intrinsics.ll
M llvm/test/Analysis/CostModel/AArch64/vector-select.ll
M llvm/test/Analysis/CostModel/AMDGPU/reduce-and.ll
M llvm/test/Analysis/CostModel/AMDGPU/reduce-or.ll
M llvm/test/Analysis/CostModel/ARM/arith-overflow.ll
M llvm/test/Analysis/CostModel/ARM/arith-ssat.ll
M llvm/test/Analysis/CostModel/ARM/arith-usat.ll
M llvm/test/Analysis/CostModel/ARM/cmps.ll
M llvm/test/Analysis/CostModel/ARM/intrinsic-cost-kinds.ll
M llvm/test/Analysis/CostModel/ARM/mve-abs.ll
M llvm/test/Analysis/CostModel/ARM/mve-minmax.ll
M llvm/test/Analysis/CostModel/ARM/select.ll
M llvm/test/Analysis/UniformityAnalysis/AMDGPU/intrinsics.ll
A llvm/test/CodeGen/AArch64/pr148949.ll
A llvm/test/CodeGen/AMDGPU/branch-relaxation-gfx1250.ll
A llvm/test/CodeGen/AMDGPU/fold-commute-sgpr.mir
A llvm/test/CodeGen/AMDGPU/global-address.ll
A llvm/test/CodeGen/AMDGPU/llvm.amdgcn.rcp.bf16.ll
A llvm/test/CodeGen/AMDGPU/llvm.amdgcn.sqrt.bf16.ll
A llvm/test/CodeGen/AMDGPU/llvm.amdgcn.wmma.gfx1250.w32.ll
A llvm/test/CodeGen/AMDGPU/llvm.amdgcn.wmma.imm.gfx1250.w32.ll
A llvm/test/CodeGen/AMDGPU/llvm.amdgcn.wmma.imod.gfx1250.w32.ll
A llvm/test/CodeGen/AMDGPU/llvm.amdgcn.wmma.index.gfx1250.w32.ll
A llvm/test/CodeGen/AMDGPU/llvm.sqrt.bf16.ll
A llvm/test/CodeGen/AMDGPU/merge-tbuffer-gfx10.mir
A llvm/test/CodeGen/AMDGPU/merge-tbuffer-gfx11.mir
A llvm/test/CodeGen/AMDGPU/merge-tbuffer-gfx9.mir
R llvm/test/CodeGen/AMDGPU/merge-tbuffer.mir
M llvm/test/CodeGen/ARM/fast-isel-align.ll
M llvm/test/CodeGen/ARM/struct_byval.ll
M llvm/test/CodeGen/ARM/trap.ll
R llvm/test/CodeGen/ARM/varargs-spill-stack-align-nacl.ll
M llvm/test/CodeGen/DirectX/legalize-i8.ll
A llvm/test/CodeGen/DirectX/legalize-load-store-array-alloca.ll
M llvm/test/CodeGen/DirectX/legalize-memcpy.ll
M llvm/test/CodeGen/DirectX/legalize-memset.ll
M llvm/test/CodeGen/MIR/AMDGPU/target-flags.mir
M llvm/test/CodeGen/Mips/fastcc.ll
M llvm/test/CodeGen/Mips/fp-indexed-ls.ll
M llvm/test/CodeGen/Mips/indirect-jump-hazard/long-branch.ll
M llvm/test/CodeGen/Mips/longbranch.ll
R llvm/test/CodeGen/Mips/nacl-align.ll
R llvm/test/CodeGen/Mips/nacl-branch-delay.ll
R llvm/test/CodeGen/Mips/nacl-reserved-regs.ll
M llvm/test/CodeGen/NVPTX/atomicrmw-expand.ll
M llvm/test/CodeGen/NVPTX/atomics-sm70.ll
M llvm/test/CodeGen/NVPTX/atomics-sm90.ll
M llvm/test/CodeGen/NVPTX/cmpxchg-sm60.ll
M llvm/test/CodeGen/NVPTX/cmpxchg-sm70.ll
M llvm/test/CodeGen/NVPTX/cmpxchg-sm90.ll
M llvm/test/CodeGen/NVPTX/cmpxchg.ll
M llvm/test/CodeGen/NVPTX/cmpxchg.py
M llvm/test/CodeGen/NVPTX/distributed-shared-cluster.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vsadd-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vsaddu-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vssub-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vssubu-vp.ll
M llvm/test/CodeGen/RISCV/xqcibm-cto-clo-brev.ll
M llvm/test/CodeGen/RISCV/xqcibm-insert.ll
M llvm/test/CodeGen/Thumb2/mve-pred-vselect.ll
M llvm/test/CodeGen/Thumb2/pacbti-m-outliner-1.ll
M llvm/test/CodeGen/X86/constructor.ll
M llvm/test/CodeGen/X86/div-rem-pair-recomposition-unsigned.ll
M llvm/test/CodeGen/X86/fast-isel-x32.ll
M llvm/test/CodeGen/X86/frameaddr.ll
M llvm/test/CodeGen/X86/invalid-operand-bundle-call.ll
M llvm/test/CodeGen/X86/invalid-operand-bundle-callbr.ll
M llvm/test/CodeGen/X86/lea-2.ll
M llvm/test/CodeGen/X86/lea-3.ll
M llvm/test/CodeGen/X86/lea-4.ll
M llvm/test/CodeGen/X86/lea-5.ll
M llvm/test/CodeGen/X86/lea.ll
M llvm/test/CodeGen/X86/stack-align2.ll
M llvm/test/CodeGen/X86/test-shrink-bug.ll
M llvm/test/CodeGen/X86/x86-64-baseptr.ll
M llvm/test/CodeGen/X86/x86-64-stack-and-frame-ptr.ll
M llvm/test/Instrumentation/MemorySanitizer/X86/avx-intrinsics-x86.ll
M llvm/test/Instrumentation/MemorySanitizer/X86/avx512-intrinsics-upgrade.ll
M llvm/test/Instrumentation/MemorySanitizer/X86/avx512-intrinsics.ll
M llvm/test/Instrumentation/MemorySanitizer/X86/avx512bw-intrinsics-upgrade.ll
M llvm/test/Instrumentation/MemorySanitizer/X86/avx512bw-intrinsics.ll
M llvm/test/Instrumentation/MemorySanitizer/X86/avx512vl-intrinsics.ll
M llvm/test/Instrumentation/MemorySanitizer/X86/x86-vpermi2.ll
M llvm/test/Instrumentation/MemorySanitizer/i386/avx-intrinsics-i386.ll
M llvm/test/Instrumentation/MemorySanitizer/or.ll
A llvm/test/MC/AMDGPU/fixup64.s
M llvm/test/MC/AMDGPU/gfx1250_asm_sop1.s
M llvm/test/MC/AMDGPU/gfx1250_asm_vop1-fake16.s
M llvm/test/MC/AMDGPU/gfx1250_asm_vop1.s
M llvm/test/MC/AMDGPU/gfx1250_asm_vop1_dpp16-fake16.s
M llvm/test/MC/AMDGPU/gfx1250_asm_vop1_dpp16.s
M llvm/test/MC/AMDGPU/gfx1250_asm_vop1_dpp8-fake16.s
M llvm/test/MC/AMDGPU/gfx1250_asm_vop1_dpp8.s
M llvm/test/MC/AMDGPU/gfx1250_asm_vop3_from_vop1-fake16.s
M llvm/test/MC/AMDGPU/gfx1250_asm_vop3_from_vop1.s
M llvm/test/MC/AMDGPU/gfx1250_asm_vop3_from_vop1_dpp16-fake16.s
M llvm/test/MC/AMDGPU/gfx1250_asm_vop3_from_vop1_dpp16.s
M llvm/test/MC/AMDGPU/gfx1250_asm_vop3_from_vop1_dpp8-fake16.s
M llvm/test/MC/AMDGPU/gfx1250_asm_vop3_from_vop1_dpp8.s
R llvm/test/MC/ARM/AlignedBundling/group-bundle-arm.s
R llvm/test/MC/ARM/AlignedBundling/illegal-subtarget-change.s
R llvm/test/MC/ARM/AlignedBundling/lit.local.cfg
R llvm/test/MC/ARM/AlignedBundling/pad-align-to-bundle-end.s
R llvm/test/MC/ARM/AlignedBundling/subtarget-change.s
M llvm/test/MC/ARM/arm_instructions.s
M llvm/test/MC/AsmParser/AArch64/directive-parse-err.s
M llvm/test/MC/Disassembler/AMDGPU/gfx1250_dasm_sop1.txt
M llvm/test/MC/Disassembler/AMDGPU/gfx1250_dasm_vop1.txt
M llvm/test/MC/Disassembler/AMDGPU/gfx1250_dasm_vop1_dpp16.txt
M llvm/test/MC/Disassembler/AMDGPU/gfx1250_dasm_vop1_dpp8.txt
M llvm/test/MC/Disassembler/AMDGPU/gfx1250_dasm_vop3_from_vop1.txt
M llvm/test/MC/Disassembler/AMDGPU/gfx1250_dasm_vop3_from_vop1_dpp16.txt
M llvm/test/MC/Disassembler/AMDGPU/gfx1250_dasm_vop3_from_vop1_dpp8.txt
R llvm/test/MC/Mips/nacl-mask.s
R llvm/test/MC/X86/AlignedBundling/align-mode-argument-error.s
R llvm/test/MC/X86/AlignedBundling/asm-printing-bundle-directives.s
R llvm/test/MC/X86/AlignedBundling/autogen-inst-offset-align-to-end.s
R llvm/test/MC/X86/AlignedBundling/autogen-inst-offset-padding.s
R llvm/test/MC/X86/AlignedBundling/bundle-group-too-large-error.s
R llvm/test/MC/X86/AlignedBundling/bundle-lock-option-error.s
R llvm/test/MC/X86/AlignedBundling/bundle-subtarget-change-error.s
R llvm/test/MC/X86/AlignedBundling/different-sections.s
R llvm/test/MC/X86/AlignedBundling/labeloffset.s
R llvm/test/MC/X86/AlignedBundling/lit.local.cfg
R llvm/test/MC/X86/AlignedBundling/lock-without-bundle-mode-error.s
R llvm/test/MC/X86/AlignedBundling/long-nop-pad.s
R llvm/test/MC/X86/AlignedBundling/misaligned-bundle-group.s
R llvm/test/MC/X86/AlignedBundling/misaligned-bundle.s
R llvm/test/MC/X86/AlignedBundling/nesting.s
R llvm/test/MC/X86/AlignedBundling/pad-align-to-bundle-end.s
R llvm/test/MC/X86/AlignedBundling/pad-bundle-groups.s
R llvm/test/MC/X86/AlignedBundling/relax-at-bundle-end.s
R llvm/test/MC/X86/AlignedBundling/relax-in-bundle-group.s
R llvm/test/MC/X86/AlignedBundling/rodata-section.s
R llvm/test/MC/X86/AlignedBundling/section-alignment.s
R llvm/test/MC/X86/AlignedBundling/single-inst-bundling.s
R llvm/test/MC/X86/AlignedBundling/switch-section-locked-error.s
R llvm/test/MC/X86/AlignedBundling/unlock-without-lock-error.s
R llvm/test/MC/X86/align-branch-bundle.s
M llvm/test/TableGen/RuntimeLibcallEmitter.td
A llvm/test/Transforms/InstCombine/fold-icmp-without-constant-into-phi.ll
A llvm/test/Transforms/InstCombine/ptrauth-call.ll
A llvm/test/Transforms/InstCombine/ptrauth-intrinsics-call.ll
M llvm/test/Transforms/InterleavedAccess/RISCV/addrspace.ll
M llvm/test/Transforms/InterleavedAccess/RISCV/interleaved-accesses.ll
M llvm/test/Transforms/SimplifyCFG/ARM/phi-eliminate.ll
M llvm/test/tools/llvm-objcopy/ELF/strip-preserve-atime.test
M llvm/unittests/IR/IntrinsicsTest.cpp
M llvm/unittests/TargetParser/TargetParserTest.cpp
M llvm/utils/gn/secondary/clang/lib/Basic/BUILD.gn
M llvm/utils/gn/secondary/clang/lib/CodeGen/BUILD.gn
M llvm/utils/gn/secondary/clang/lib/Driver/BUILD.gn
M llvm/utils/gn/secondary/clang/lib/Headers/BUILD.gn
M llvm/utils/gn/secondary/libcxx/include/BUILD.gn
M llvm/utils/gn/secondary/lldb/source/Plugins/Language/CPlusPlus/BUILD.gn
M llvm/utils/gn/secondary/llvm/lib/Target/Mips/MCTargetDesc/BUILD.gn
M llvm/utils/gn/secondary/llvm/unittests/BinaryFormat/BUILD.gn
M mlir/include/mlir/Bindings/Python/NanobindAdaptors.h
M mlir/include/mlir/Dialect/Affine/Analysis/AffineAnalysis.h
M mlir/lib/Dialect/Affine/Analysis/Utils.cpp
M mlir/lib/Dialect/OpenMP/IR/OpenMPDialect.cpp
M mlir/lib/Target/LLVMIR/Dialect/NVVM/NVVMToLLVMIRTranslation.cpp
M utils/bazel/llvm-project-overlay/libc/BUILD.bazel
M utils/bazel/llvm-project-overlay/libc/test/src/math/BUILD.bazel
M utils/bazel/llvm-project-overlay/libc/test/src/math/smoke/BUILD.bazel
Log Message:
-----------
rebase
Created using spr 1.3.5-bogner
Compare: https://github.com/llvm/llvm-project/compare/11098bf999b4...b43c30dbd97c
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